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1.1 root 1: #include "../h/param.h"
2: #include "../h/inode.h"
3: #include "../h/pte.h"
4: #include "../h/uba.h"
5: #include "saio.h"
6:
7: #define EMULEX
8: #ifdef EMULEX
9: #define DELAY(N) { register int d; d = N; while (--d > 0); }
10: #else
11: #define DELAY(N)
12: #endif
13:
14: struct upregs {
15: short upcs1; /* Control and Status register 1 */
16: short upwc; /* Word count register */
17: short upba; /* UNIBUS address register */
18: short upda; /* Desired address register */
19: short upcs2; /* Control and Status register 2*/
20: short upds; /* Drive Status */
21: short uper1; /* Error register 1 */
22: short upas; /* Attention Summary */
23: short upla; /* Look ahead */
24: short updb; /* Data buffer */
25: short upmr; /* Maintenance register */
26: short updt; /* Drive type */
27: short upsn; /* Serial number */
28: short upof; /* Offset register */
29: short upca; /* Desired Cylinder address register*/
30: short upcc; /* Current Cylinder */
31: short uper2; /* Error register 2 */
32: short uper3; /* Error register 3 */
33: short uppos; /* Burst error bit position */
34: short uppat; /* Burst error bit pattern */
35: short upbae; /* 11/70 bus extension */
36: };
37:
38: #define UPADDR ((struct upregs *)(PHYSUMEM + 0776700 - UNIBASE))
39: char up_openf;
40:
41: /* Drive Commands */
42: #define GO 01
43: #define PRESET 020
44: #define RECAL 06
45: #define RCLR 010
46: #define OFFSET 014
47: #define RCOM 070
48: #define WCOM 060
49:
50: #define IENABLE 0100
51: #define READY 0200 /* upds - drive ready */
52: #define PIP 020000 /* upds - Positioning Operation in Progress */
53: #define ERR 040000 /* upcs1 - composite error */
54: #define DRY 0200 /* upcs1 - drive ready */
55:
56: #define DTE 010000 /* uper1 - Drive Timing Error */
57: #define OPI 020000 /* uper1 - Operation Incomplete */
58: #define DU 040000 /* uper1 - Drive Unsafe */
59:
60: /* Error Correction Code errors */
61: #define DCK 0100000 /* uper1 - Data Check error */
62: #define ECH 0100 /* uper1 - ECC hard error */
63:
64: #define CLR 040 /* upcs2 - Controller Clear */
65:
66: #define FMT22 010000 /* upof - 16 bit /word format */
67:
68: struct devsize {
69: daddr_t cyloff;
70: } up_sizes[] = {
71: 0, 27, 68, -1, -1, -1, -1, 82
72: };
73:
74: upopen(io)
75: register struct iob *io;
76: {
77:
78: if (up_sizes[io->i_boff].cyloff == -1 ||
79: io->i_boff < 0 || io->i_boff > 7)
80: _stop("up bad unit");
81: io->i_boff = up_sizes[io->i_boff].cyloff * 32 * 19;
82: }
83:
84: upstrategy(io, func)
85: register struct iob *io;
86: {
87: int unit, nspc, ns, cn, tn, sn;
88: daddr_t bn;
89: int info;
90: register short *rp;
91: int occ = io->i_cc;
92:
93: unit = io->i_unit;
94: bn = io->i_bn;
95: nspc = 32 * 19;
96: ns = 32;
97: cn = bn/nspc;
98: sn = bn%nspc;
99: tn = sn/ns;
100: sn = sn%ns;
101: if (!up_openf) {
102: up_openf++;
103: UPADDR->upcs2 = CLR;
104: DELAY(500);
105: UPADDR->upcs1 = RCLR|GO;
106: DELAY(500);
107: UPADDR->upcs1 = PRESET|GO;
108: DELAY(500);
109: UPADDR->upof = FMT22;
110: DELAY(500);
111: while ((UPADDR->upcs1 & DRY) == 0)
112: DELAY(500);
113: }
114: UPADDR->upcs2 = unit;
115: DELAY(500);
116: info = ubasetup(io, 1);
117: rp = (short *) &UPADDR->upda;
118: UPADDR->upca = cn;
119: *rp = (tn << 8) + sn;
120: *--rp = info;
121: *--rp = -io->i_cc / sizeof (short);
122: if (func == READ) {
123: *--rp = GO|RCOM;
124: } else {
125: *--rp = GO|WCOM;
126: }
127: DELAY(500);
128: do {
129: DELAY(200);
130: } while ((UPADDR->upcs1 & DRY) == 0);
131: DELAY(200);
132: if (UPADDR->upcs1&ERR) {
133: printf("disk error: cyl=%d track=%d sect=%d cs1=%X, er1=%X\n",
134: cn, tn, sn,
135: UPADDR->upcs1, UPADDR->uper1);
136: return (-1);
137: }
138: if (io->i_cc != occ)
139: printf("returned %d\n", io->i_cc);
140: ubafree(info);
141: return (io->i_cc);
142: }
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