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1.1 ! root 1: /* uba.h 4.1 11/9/80 */ ! 2: ! 3: /* ! 4: * Unibus adapter ! 5: */ ! 6: ! 7: #define UBA0 0x80060000 /* sys virt i/o for UBA 0 */ ! 8: #define UBA0_DEV (UBA0+0x2000-0160000) /* sys virt of device regs */ ! 9: ! 10: #define UNIBASE 0760000 /* UNIBUS phys base of i/o reg's */ ! 11: ! 12: /* UBA Configuration Register, CNFGR */ ! 13: #define PARFLT 0x80000000 /* SBI Parity Fault */ ! 14: #define WSQFLT 0x40000000 /* SBI Write Sequence Fault */ ! 15: #define URDFLT 0x20000000 /* SBI Unexpected Read Fault */ ! 16: #define ISQFLT 0x10000000 /* SBI Interlock Sequence Fault */ ! 17: #define MXTFLT 0x8000000 /* SBI Multiple Transmitter Fault */ ! 18: #define XMTFLT 0x4000000 /* UBA is transmit faulter */ ! 19: #define ADPDN 0x800000 /* Adapter Power Down */ ! 20: #define ADPUP 0x400000 /* Adapter Power Up */ ! 21: #define UBINIT 0x40000 /* UNIBUS INIT is asserted */ ! 22: #define UBPDN 0x20000 /* UNIBUS Power Down */ ! 23: #define UBIC 0x10000 /* UNIBUS Initialization */ ! 24: /* UNIBUS Ready */ ! 25: #define UBACOD 0xff /* UBA Code bits */ ! 26: ! 27: /* UBA Control Register, UBACR */ ! 28: ! 29: #define MRD16 0x40000000 /* Map Reg Disable Bit 4 */ ! 30: #define MRD8 0x20000000 /* Map Reg Disable Bit 3 */ ! 31: #define MRD4 0x10000000 /* Map Reg Disable Bit 2 */ ! 32: #define MRD2 0x8000000 /* Map Reg Disable Bit 1 */ ! 33: #define MRD1 0x4000000 /* Map Reg Disable Bit 0 */ ! 34: #define IFS 0x40 /* Interrupt Field Switch */ ! 35: #define BRIE 0x20 /* BR Interrupt Enable */ ! 36: #define USEFIE 0x10 /* UNIBUS to SBI Error Field IE */ ! 37: #define SUEFIE 0x8 /* SBI to UNIBUS Error Field IE */ ! 38: #define CNFIE 0x4 /* Configuration IE */ ! 39: #define UPF 0x2 /* UNIBUS Power Fail */ ! 40: #define ADINIT 0x1 /* Adapter Init */ ! 41: ! 42: /* UBA Status Register, UASR */ ! 43: #define BR7FULL 0x8000000 /* BR7 Receive Vector Rg Full */ ! 44: #define BR6FULL 0x4000000 /* BR6 Receive Vector Reg Full */ ! 45: #define BR5FULL 0x2000000 /* BR5 Receive Vector Reg Full */ ! 46: #define BR4FULL 0x1000000 /* BR4 Receive Vector Reg Full */ ! 47: #define RDTO 0x400 /* UNIBUS to SBI Read Data Timeout */ ! 48: #define RDS 0x200 /* Read Data Substitute */ ! 49: #define CRD 0x100 /* Corrected Read Data */ ! 50: #define CXTER 0x80 /* Command Transmit Error */ ! 51: #define CXTMO 0x40 /* Command Transmit Timeout */ ! 52: #define DPPE 0x20 /* Data Path Parity Error */ ! 53: #define IVMR 0x10 /* Invalid Map Register */ ! 54: #define MRPF 0x8 /* Map Register Parity Failure */ ! 55: #define LEB 0x4 /* Lost Error */ ! 56: #define UBSTO 0x2 /* UNIBUS Select Timeout */ ! 57: #define UBSSTO 0x1 /* UNIBUS Slave Sync Timeout */ ! 58: ! 59: /* Failed Map Entry Register, FMER */ ! 60: ! 61: #define FMRN 0x1ff /* Failed Map Reg. No. Field */ ! 62: ! 63: /* Failed UNIBUS Address Register, FUBAR */ ! 64: #define FUA 0xffff /* Failed UNIBUS Address Field */ ! 65: ! 66: /* BR Receive Vector register, BRRVR */ ! 67: #define AIRI 0x80000000 /* Adapter Interrupt Request */ ! 68: #define DIV 0xffff /* Device Interrupt Vector Field */ ! 69: ! 70: /* Data Path Register, DPR */ ! 71: #define BNE 0x80000000 /* Buffer Not Empty - Purge */ ! 72: #define BTE 0x40000000 /* Buffer Transfer Error */ ! 73: #define DPF 0x20000000 /* DP Function (RO) */ ! 74: #define BS 0x7f0000 /* Buffer State Field */ ! 75: #define BUBA 0xffff /* Buffered UNIBUS Address */ ! 76: ! 77: /* Map Register, MR */ ! 78: #define MRV 0x80000000 /* Map Register Valid */ ! 79: #define BO 0x2000000 /* Byte Offset Bit */ ! 80: #define DPDB 0x1e00000 /* Data Path Designator Field */ ! 81: #define SBIPFN 0xfffff /* SBI Page Address Field */ ! 82: ! 83: /* ! 84: * Unibus maps ! 85: */ ! 86: #ifdef KERNEL ! 87: #define UAMSIZ 50 ! 88: ! 89: struct map ubamap[UAMSIZ]; ! 90: char bdpwant; /* someone is waiting for buffered data path */ ! 91: struct map bdpmap[15]; ! 92: char umrwant; /* ... for unibus map registers */ ! 93: #endif ! 94: ! 95: /* ! 96: * UBA registers ! 97: */ ! 98: ! 99: struct uba_regs ! 100: { ! 101: int uba_cnfgr; ! 102: int uba_cr; ! 103: int uba_sr; ! 104: int uba_dcr; ! 105: int uba_fmer; ! 106: int uba_fubar; ! 107: int pad1[2]; ! 108: int uba_brsvr[4]; ! 109: int uba_brrvr[4]; ! 110: int uba_dpr[16]; ! 111: int pad2[480]; ! 112: struct pte uba_map[496]; ! 113: }; ! 114: ! 115: union ub_info { ! 116: struct ub_Info { ! 117: unsigned int Ub_off:18, ! 118: Ub_npf:10, ! 119: Ub_bdp:4; ! 120: } ub_I; ! 121: int ub_word; ! 122: }; ! 123: ! 124: #define ub_off ub_I.Ub_off ! 125: #define ub_npf ub_I.Ub_npf ! 126: #define ub_bdp ub_I.Ub_bdp
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