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1.1 root 1: /* tdump.c 3.4 10/5/80 */
2:
3: #include "../ch/param.h"
4: #include "../ch/vm.h"
5: #include "../ch/pte.h"
6: #include "../ch/map.h"
7: #include "../ch/uba.h"
8: #include "../ch/systm.h"
9: #include "../ch/cmap.h"
10: #include "../ch/mba.h"
11:
12: #ifdef HTDUMP
13: /*
14: * Dump core to magtape.
15: * Assumes memory mapping has been disabled
16: * and IPL has been set high ( > 0x15 )
17: */
18:
19: #define UBA 0x20006000
20: #define mba0 0x20010000
21: #define mba1 0x20012000
22:
23: struct mba_regs {
24: int mba_csr;
25: int mba_cr;
26: int mba_sr;
27: int mba_var;
28: int mba_bcr;
29: };
30:
31: struct device
32: {
33: int htcs1;
34: int htds;
35: int hter;
36: int htmr;
37: int htas;
38: int htfc;
39: int htdt;
40: int htck;
41: int htsn;
42: int httc;
43: };
44:
45: #define HTADDR ((struct device *)(mba1 + 0x400))
46: #define HTMAP ((struct pte *) (mba1 + 0x800))
47:
48: #define GO 01
49: #define WCOM 060
50: #define RCOM 070
51: #define NOP 0
52: #define WEOF 026
53: #define SFORW 030
54: #define SREV 032
55: #define ERASE 024
56: #define REW 06
57: #define DCLR 010
58: #define P800 01300 /* 800 + pdp11 mode */
59: #define P1600 02300 /* 1600 + pdp11 mode */
60: #define IENABLE 0100
61: #define RDY 0200
62: #define TM 04
63: #define DRY 0200
64: #define EOT 02000
65: #define CS 02000
66: #define COR 0100000
67: #define PES 040
68: #define WRL 04000
69: #define MOL 010000
70: #define ERR 040000
71: #define FCE 01000
72: #define TRE 040000
73: #define HARD 064023 /* UNS|OPI|NEF|FMT|RMR|ILR|ILF */
74:
75: #define SIO 1
76: #define SSFOR 2
77: #define SSREV 3
78: #define SRETRY 4
79: #define SCOM 5
80: #define SOK 6
81:
82: #define DBSIZE 20
83:
84: dump()
85: {
86:
87: HTADDR->httc = P800; /* set 800 bpi mode */
88:
89: htwall((char *)0, maxfree); /* write out memory */
90:
91: hteof();
92: hteof();
93: htrewind();
94: htwait();
95: }
96:
97: htwall(start, num)
98: char *start;
99: int num;
100: {
101: int blk;
102:
103: HTADDR->htcs1 = DCLR | GO;
104: while (num > 0) {
105: blk = num > DBSIZE ? DBSIZE : num;
106: htwrite(start, blk);
107: start += blk*NBPG;
108: num -= blk;
109: }
110: }
111:
112: htwrite(buf, num)
113: char *buf;
114: {
115: register struct pte *hpte = HTMAP;
116: register int i;
117:
118: htwait();
119: HTADDR->htfc = -(num*NBPG);
120: for (i = 0; i < num; i++)
121: *(int *)hpte++ = (btop(buf)+i) | PG_V;
122: ((struct mba_regs *)mba1)->mba_sr = -1;
123: ((struct mba_regs *)mba1)->mba_bcr = -(num*NBPG);
124: ((struct mba_regs *)mba1)->mba_var = 0;
125: HTADDR->htcs1 = WCOM | GO;
126: }
127:
128: htwait()
129: {
130: register s;
131:
132: do
133: s = HTADDR->htds;
134: while ((s & RDY) == 0);
135: }
136:
137: htrewind()
138: {
139:
140: htwait();
141: HTADDR->htcs1 = REW | GO;
142: }
143:
144: hteof()
145: {
146:
147: htwait();
148: HTADDR->htcs1 = WEOF | GO;
149: }
150:
151: #endif
152: #ifdef TMDUMP
153:
154: /*
155: * Dump core to magtape.
156: * Assumes memory mapping has been disabled
157: * and IPL has been set high ( > 0x15 )
158: */
159:
160: #define UBA 0x20006000
161: #define UBA_DEV (UBA+0x130000-0160000)
162: struct device
163: {
164: short tmer;
165: short tmcs;
166: short tmbc;
167: unsigned short tmba;
168: short tmdb;
169: short tmrd;
170: };
171:
172: #define TMADDR ((struct device*)(0x2013F550))
173:
174: #define GO 01
175: #define RCOM 02
176: #define WCOM 04
177: #define WEOF 06
178: #define NOP 0100
179: #define SFORW 010
180: #define SREV 012
181: #define WIRG 014
182: #define REW 016
183: #define DCLR 010000
184: #define D800 060000
185: #define D1600 0117777
186: #define IENABLE 0100
187:
188: #define GAPSD 010
189: #define CRDY 0200
190: #define TUR 1
191: #define HARD 0102200
192: #define RLE 0100
193: #define EOF 0040000
194: #define WL 04
195: #define RWS 02
196:
197: #define SSEEK 1
198: #define SIO 2
199: #define SCOM 3
200:
201: #define DBSIZE 20
202:
203: dump()
204: {
205:
206: tubainit();
207: tmwall(0, maxfree); /* write out memory */
208:
209: tmeof();
210: tmeof();
211: tmrewind();
212: tmwait();
213: }
214:
215: tmwall(start, num)
216: int start, num;
217: {
218: int blk;
219:
220: TMADDR->tmcs = DCLR | GO;
221: while (num > 0) {
222: blk = num > DBSIZE ? DBSIZE : num;
223: tmdwrite(start, blk);
224: start += blk;
225: num -= blk;
226: }
227: }
228:
229: tmdwrite(buf, num)
230: register buf, num;
231: {
232: register int *io, npf;
233: tmwait();
234: /* Flush buffered data path 0 */
235: ((struct uba_regs *)UBA)->uba_dpr[1] = 0;
236: ((struct uba_regs *)UBA)->uba_dpr[1] = BNE;
237: /* Map unibus address 0 to section of interest */
238: io = (int *)((struct uba_regs *)UBA)->uba_map;
239: npf = num+1;
240:
241: while(--npf != 0)
242: *io++ = (int)(buf++ | (1<<21) | MRV);
243: *io = 0;
244:
245: TMADDR->tmbc = -(num*NBPG);
246: TMADDR->tmba = 0;
247: TMADDR->tmcs = WCOM | GO | D800;
248: }
249:
250: tmwait()
251: {
252: register short s;
253:
254: do
255: s = TMADDR->tmcs;
256: while ((s & CRDY) == 0);
257: }
258:
259: tmrewind()
260: {
261:
262: tmwait();
263: TMADDR->tmcs = REW | GO;
264: }
265:
266: tmeof()
267: {
268:
269: tmwait();
270: TMADDR->tmcs = WEOF | GO | D800;
271: }
272:
273: tubainit()
274: {
275: register struct uba_regs *up = (struct uba_regs *)UBA;
276:
277: up->uba_cr = ADINIT;
278: up->uba_cr = IFS|BRIE|USEFIE|SUEFIE;
279: while ((up->uba_cnfgr & UBIC) == 0) ;
280: }
281: #endif
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