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1.1 root 1: /* scb.s 6.1 83/08/11 */
2:
3: #include "uba.h"
4:
5: /*
6: * System control block
7: */
8: .set INTSTK,1 # handle this interrupt on the interrupt stack
9: .set HALT,3 # halt if this interrupt occurs
10:
11: _scb: .globl _scb
12:
13: #define STRAY .long _Xstray+INTSTK
14: #define STRAY8 STRAY;STRAY;STRAY;STRAY;STRAY;STRAY;STRAY;STRAY
15: #define STRAY15 STRAY;STRAY;STRAY;STRAY;STRAY;STRAY;STRAY;STRAY8
16: #define KS(a) .long _X/**/a
17: #define IS(a) .long _X/**/a+INTSTK
18: #define STOP(a) .long _X/**/a+HALT
19:
20: /* 000 */ STRAY; IS(machcheck); IS(kspnotval); STOP(powfail);
21: /* 010 */ KS(privinflt); KS(xfcflt); KS(resopflt); KS(resadflt);
22: /* 020 */ KS(protflt); KS(transflt); KS(tracep); KS(bptflt);
23: /* 030 */ KS(compatflt); KS(arithtrap); STRAY; STRAY;
24: /* 040 */ KS(syscall); KS(chme); KS(chms); KS(chmu);
25: /* 050 */ STRAY; IS(cmrd); STRAY; STRAY;
26: /* 060 */ IS(wtime); STRAY; STRAY; STRAY;
27: /* 070 */ STRAY; STRAY; STRAY; STRAY;
28: /* 080 */ STRAY; STRAY; KS(astflt); STRAY;
29: /* 090 */ STRAY; STRAY; STRAY; STRAY;
30: /* 0a0 */ IS(softclock); STRAY; STRAY; STRAY;
31: /* 0b0 */ IS(netintr); STRAY; STRAY; STRAY;
32: /* 0c0 */ IS(hardclock); STRAY; STRAY; STRAY;
33: /* 0d0 */ STRAY; STRAY; STRAY; STRAY;
34: /* 0e0 */ STRAY; STRAY; STRAY; STRAY;
35: /* 0f0 */ IS(consdin); IS(consdout); IS(cnrint); IS(cnxint);
36: /* 100 */ IS(nexzvec); STRAY15; /* ipl 0x14, nexus 0-15 */
37: /* 140 */ IS(nexzvec); STRAY15; /* ipl 0x15, nexus 0-15 */
38: /* 180 */ IS(nexzvec); STRAY15; /* ipl 0x16, nexus 0-15 */
39: /* 1c0 */ IS(nexzvec); STRAY15; /* ipl 0x17, nexus 0-15 */
40:
41: .globl _UNIvec
42: _UNIvec: .space 512 # 750 unibus intr vector
43: # 1st UBA jump table on 780's
44: #if NUBA > 1
45: .globl _UNI1vec
46: _UNI1vec: .space 512 # 750 second unibus intr vector
47: # 2nd UBA jump table on 780's
48: #endif
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