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1.1 root 1: /* if_unreg.h 6.1 83/07/29 */
2:
3: /*
4: * Device registers and bit meanings
5: */
6:
7: struct undevice {
8: short wcr; /* word count */
9: short bar; /* bus address */
10: short csr; /* control & status (also error & info) */
11: short dar; /* input and output data register */
12: };
13:
14: /* CSR bits */
15: #define GO 0000001
16: #define FCN1 0000002 /* three function bits */
17: #define FCN2 0000004
18: #define FCN3 0000010
19: #define XBA 0000060 /* extended bus address (16&17) */
20: #define IE 0000100 /* interrupt enable */
21: #define RDY 0000200 /* ready */
22: #define CYCL 0000400 /* cycle */
23: #define STATC 0001000 /* Status bit C */
24: #define STATB 0002000 /* Status bit B */
25: #define STATA 0004000 /* Status bit A */
26: #define MNT 0010000 /* maintenance */
27: #define ATTN 0020000 /* attention (from device) */
28: #define NEX 0040000 /* non-existent memory */
29: #define ERR 0100000
30: #define XADD 4
31:
32: #define UNBITS "\10\20ERR\17NEX\16ATTN\15MNT\14STATA\13STATB\12STATC\
33: \11CYCL\10RDY\7IE\6XBA17\5XBA16\4FCN3\3FCN2\2FCN1\1GO"
34:
35: /* EIR bits */
36: #define RF 0000001 /* register flag 1 - verifies EIR */
37: #define NBST 0000400 /* N - cycle burst */
38: #define BDLT 0001000 /* burst data late */
39: #define PERR 0002000 /* parity error */
40: #define ACLO 0004000 /* power fail */
41: #define MCYC 0010000 /* multicycle request */
42: #define ATTN 0020000 /* attention (from device) */
43: #define NEX 0040000 /* non-existent memory */
44: #define ERR 0100000
45:
46: /* Network interface commands */
47: #define UNRESET 0
48: #define UNRDHDR FCN1
49: #define UNOUT FCN2
50: #define UNRDDG (FCN2|FCN1)
51: #define UNFLUSH FCN3
52: #define UNIDLE (FCN3|FCN2)
53:
54: /* Extended status bits (in dar) */
55: #define RESETACK 1 /* Reset cmd acknowledged */
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