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Annotation of 42BSD/sys/vaxuba/dhreg.h, revision 1.1.1.1

1.1       root        1: /*     dhreg.h 6.1     83/07/29        */
                      2: 
                      3: /* 
                      4:  * DH-11 device register definitions.
                      5:  */
                      6: struct dhdevice {
                      7:        union {
                      8:                short   dhcsr;          /* control-status register */
                      9:                char    dhcsrl;         /* low byte for line select */
                     10:        } un;
                     11:        short   dhrcr;                  /* receive character register */
                     12:        short   dhlpr;                  /* line parameter register */
                     13:        u_short dhcar;                  /* current address register */
                     14:        short   dhbcr;                  /* byte count register */
                     15:        u_short dhbar;                  /* buffer active register */
                     16:        short   dhbreak;                /* break control register */
                     17:        short   dhsilo;                 /* silo status register */
                     18: };
                     19: 
                     20: /* Bits in dhcsr */
                     21: #define        DH_TI   0100000         /* transmit interrupt */
                     22: #define        DH_SI   0040000         /* storage interrupt */
                     23: #define        DH_TIE  0020000         /* transmit interrupt enable */
                     24: #define        DH_SIE  0010000         /* storage interrupt enable */
                     25: #define        DH_MC   0004000         /* master clear */
                     26: #define        DH_NXM  0002000         /* non-existant memory */
                     27: #define        DH_MM   0001000         /* maintenance mode */
                     28: #define        DH_CNI  0000400         /* clear non-existant memory interrupt */
                     29: #define        DH_RI   0000200         /* receiver interrupt */
                     30: #define        DH_RIE  0000100         /* receiver interrupt enable */
                     31: 
                     32: /* Bits in dhlpr */
                     33: #define        BITS6   01
                     34: #define        BITS7   02
                     35: #define        BITS8   03
                     36: #define        TWOSB   04
                     37: #define        PENABLE 020
                     38: /* DEC manuals incorrectly say this bit causes generation of even parity. */
                     39: #define        OPAR    040
                     40: #define        HDUPLX  040000
                     41: 
                     42: #define        DH_IE   (DH_TIE|DH_SIE|DH_RIE)
                     43: 
                     44: /* Bits in dhrcr */
                     45: #define        DH_PE           0010000         /* parity error */
                     46: #define        DH_FE           0020000         /* framing error */
                     47: #define        DH_DO           0040000         /* data overrun */

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