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1.1 root 1: /* psreg.h 6.1 83/08/13 */
2:
3:
4: /*
5: * The Real Nitty Gritty Device Registers
6: */
7:
8: struct psdevice {
9: short int ps_data; /* data register */
10: short int ps_addr; /* address register */
11: short int ps_wcount; /* word count register */
12: short int ps_busaddr; /* unibus address register */
13: short int ps_iostat; /* io status register */
14: };
15:
16: /*
17: * Possible ioctl's
18: */
19: #define PSIOAUTOREFRESH _IO(p, 0) /* auto refresh */
20: #define PSIOSINGLEREFRESH _IO(p, 1) /* single refresh */
21: #define PSIOAUTOMAP _IO(p, 2) /* auto map */
22: #define PSIOSINGLEMAP _IO(p, 3) /* single map */
23: #define PSIODOUBLEBUFFER _IO(p, 4) /* double buffer */
24: #define PSIOSINGLEBUFFER _IO(p, 5) /* single buffer */
25: #define PSIOWAITREFRESH _IO(p, 6) /* await refresh */
26: #define PSIOWAITMAP _IO(p, 7) /* await map */
27: #define PSIOWAITHIT _IO(p, 8) /* await hit */
28: #define PSIOSTOPREFRESH _IO(p, 9) /* stop refresh */
29: #define PSIOSTOPMAP _IO(p,10) /* stop map */
30: #define PSIOGETADDR _IOR(p,11, int) /* get Unibus address */
31: #define PSIOTIMEREFRESH _IO(p,12) /* time refresh */
32:
33: /*
34: * Picture system io status register bits
35: */
36:
37: #define DIOREADY 0100000
38: #define PSAHOLD 040000
39: #define PSRESET 020000
40: #define DIORESET 010000
41: #define DMARESET 04000
42: #define PSIE 0400
43: #define DMAREADY 0200
44: #define DMAIE 0100
45: #define PASSIVE 010
46: #define DMAIN 04
47: #define NEXEM 02
48: #define GO 01
49:
50: /*
51: * Picture system memory mapping control registers: SCB 0177400-0177410
52: */
53:
54: #define EXMMR_DMA 0177400
55: #define EXMMR_DIO 0177404
56: #define EXMMR_RC 0177405
57: #define EXMMR_MAPOUT 0177406
58: #define EXMMR_MAPIN 0177407
59: #define EXMSR 0177410
60:
61: /*
62: * Extended memory status register bits
63: */
64:
65: #define DBERROR 0100000
66: #define SBERROR 040000
67: #define MEMREADY 0200
68: #define DBIE 0100
69: #define MMENBL 02
70: #define INITMEM 01
71:
72: /*
73: * Size of extended memory
74: */
75:
76: #define NEXMPAGES (256*2)
77: #define WORDSPERPAGE (256)
78:
79: /*
80: * MAP picture processor registers: SCB 0177750-0177753
81: */
82:
83: #define MAOL 0177750
84: #define MAOA 0177751
85: #define MAIA 0177752
86: #define MASR 0177753
87: #define MAMSR 0177754
88:
89: /*
90: * MAP status register bits
91: */
92:
93: #define PPDONE 0100000
94: #define FIFOFULL 040000
95: #define FIFOEMPTY 020000
96: #define HIT 010000
97: #define IB 04000
98: #define TAKE 02000
99: #define MMODE 01400
100: #define MOSTOPPED 0200
101: #define IOUT 0100
102: #define MAO 040
103: #define MAI 020
104: #define HIT_HOLD 010
105: #define RSR_HOLD 04
106: #define VEC_HOLD 02
107: #define MAP_RESET 01
108:
109: /*
110: * Refresh controller registers: SCB 0177730-0177737
111: */
112:
113: #define RFCSN 0177730
114: #define RFSN 0177731
115: #define RFAWA 0177732
116: #define RFAWL 0177733
117: #define RFAIA 0177734
118: #define RFASA 0177735
119: #define RFAIL 0177736
120: #define RFSR 0177737
121:
122: /*
123: * Refresh controller status register bits
124: */
125:
126: #define RFSTOPPED 0100000
127: #define RFHOLD 040000
128: #define RFSTART 020000
129: #define AUTOREF 010000
130: #define RFBLANK 04000
131: #define RIGHT 02000
132: #define LGFIFO_FULL 01000
133: #define NOT_EXEC 0200
134: #define SKIPSEG 0100
135: #define WRITEBACK 040
136: #define SEARCH 020
137: #define MATCH_HOLD 010
138: #define MATCH_DEC 04
139: #define SEARCH_MODE 03
140:
141: /*
142: * Interrupt control
143: */
144:
145: #define RTCREQ 0177760
146: #define RTCIE 0177761
147: #define SYSREQ 0177762
148: #define SYSIE 0177763
149: #define DEVREQ 0177764
150: #define DEVIE 0177765
151:
152: /*
153: * System interrupt request bits
154: */
155:
156: #define LPEN_REQ 0200
157: #define MATCH_REQ 0100
158: #define WBSTOP_REQ 040
159: #define RFSTOP_REQ 020
160: #define MOSTOP_REQ 010
161: #define JUMP_REQ 04
162: #define HIT_REQ 02
163: #define HALT_REQ 01
164:
165: /*
166: * Real-Time Clock registers
167: */
168:
169: #define RTCCNT 0177744
170: #define RTCSR 0177745
171:
172: /*
173: * Real-Time Clock status register bits
174: */
175:
176: #define HZ120 040
177: #define EXT 020
178: #define SYNC 010
179: #define EXTSEL2 04
180: #define EXTSEL1 02
181: #define RUN 01
182:
183: /*
184: * Control dials a/d registers
185: */
186:
187: #define ADDR0 0177500
188: #define ADDR1 0177501
189: #define ADDR2 0177502
190: #define ADDR3 0177503
191: #define ADDR4 0177504
192: #define ADDR5 0177505
193: #define ADDR6 0177506
194: #define ADDR7 0177507
195:
196: /*
197: * Function switches and lights
198: */
199:
200: #define FSWR 0177626
201: #define FSLR 0177627
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