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1.1 root 1: /* ubareg.h 6.2 83/09/29 */
2:
3: /*
4: * VAX UNIBUS adapter registers
5: */
6: #ifndef LOCORE
7: /*
8: * UBA hardware registers
9: */
10: struct uba_regs
11: {
12: int uba_cnfgr; /* configuration register */
13: int uba_cr; /* control register */
14: int uba_sr; /* status register */
15: int uba_dcr; /* diagnostic control register */
16: int uba_fmer; /* failed map entry register */
17: int uba_fubar; /* failed UNIBUS address register */
18: int pad1[2];
19: int uba_brsvr[4];
20: int uba_brrvr[4]; /* receive vector registers */
21: int uba_dpr[16]; /* buffered data path register */
22: int pad2[480];
23: struct pte uba_map[496]; /* unibus map register */
24: int pad3[16]; /* no maps for device address space */
25: };
26: #endif
27:
28: #if VAX780
29: /* uba_cnfgr */
30: #define UBACNFGR_UBINIT 0x00040000 /* unibus init asserted */
31: #define UBACNFGR_UBPDN 0x00020000 /* unibus power down */
32: #define UBACNFGR_UBIC 0x00010000 /* unibus init complete */
33:
34: /* uba_cr */
35: #define UBACR_MRD16 0x40000000 /* map reg disable bit 4 */
36: #define UBACR_MRD8 0x20000000 /* map reg disable bit 3 */
37: #define UBACR_MRD4 0x10000000 /* map reg disable bit 2 */
38: #define UBACR_MRD2 0x08000000 /* map reg disable bit 1 */
39: #define UBACR_MRD1 0x04000000 /* map reg disable bit 0 */
40: #define UBACR_IFS 0x00000040 /* interrupt field switch */
41: #define UBACR_BRIE 0x00000020 /* BR interrupt enable */
42: #define UBACR_USEFIE 0x00000010 /* UNIBUS to SBI error field IE */
43: #define UBACR_SUEFIE 0x00000008 /* SBI to UNIBUS error field IE */
44: #define UBACR_CNFIE 0x00000004 /* configuration IE */
45: #define UBACR_UPF 0x00000002 /* UNIBUS power fail */
46: #define UBACR_ADINIT 0x00000001 /* adapter init */
47:
48: /* uba_sr */
49: #define UBASR_BR7FULL 0x08000000 /* BR7 receive vector reg full */
50: #define UBASR_BR6FULL 0x04000000 /* BR6 receive vector reg full */
51: #define UBASR_BR5FULL 0x02000000 /* BR5 receive vector reg full */
52: #define UBASR_BR4FULL 0x01000000 /* BR4 receive vector reg full */
53: #define UBASR_RDTO 0x00000400 /* UNIBUS to SBI read data timeout */
54: #define UBASR_RDS 0x00000200 /* read data substitute */
55: #define UBASR_CRD 0x00000100 /* corrected read data */
56: #define UBASR_CXTER 0x00000080 /* command transmit error */
57: #define UBASR_CXTMO 0x00000040 /* command transmit timeout */
58: #define UBASR_DPPE 0x00000020 /* data path parity error */
59: #define UBASR_IVMR 0x00000010 /* invalid map register */
60: #define UBASR_MRPF 0x00000008 /* map register parity failure */
61: #define UBASR_LEB 0x00000004 /* lost error */
62: #define UBASR_UBSTO 0x00000002 /* UNIBUS select timeout */
63: #define UBASR_UBSSYNTO 0x00000001 /* UNIBUS slave sync timeout */
64:
65: #define UBASR_BITS \
66: "\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO"
67:
68: /* uba_brrvr[] */
69: #define UBABRRVR_AIRI 0x80000000 /* adapter interrupt request */
70: #define UBABRRVR_DIV 0x0000ffff /* device interrupt vector field */
71: #endif VAX780
72:
73: /* uba_dpr */
74: #if VAX780
75: #define UBADPR_BNE 0x80000000 /* buffer not empty - purge */
76: #define UBADPR_BTE 0x40000000 /* buffer transfer error */
77: #define UBADPR_DPF 0x20000000 /* DP function (RO) */
78: #define UBADPR_BS 0x007f0000 /* buffer state field */
79: #define UBADPR_BUBA 0x0000ffff /* buffered UNIBUS address */
80: #define UBA_PURGE780(uba, bdp) \
81: ((uba)->uba_dpr[bdp] |= UBADPR_BNE)
82: #endif VAX780
83: #if VAX750
84: #define UBADPR_ERROR 0x80000000 /* error occurred */
85: #define UBADPR_NXM 0x40000000 /* nxm from memory */
86: #define UBADPR_UCE 0x20000000 /* uncorrectable error */
87: #define UBADPR_PURGE 0x00000001 /* purge bdp */
88: /* the DELAY is for a hardware problem */
89: #define UBA_PURGE750(uba, bdp) { \
90: ((uba)->uba_dpr[bdp] |= (UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE)); \
91: DELAY(8); \
92: }
93: #endif VAX750
94:
95: /*
96: * Macros for fast buffered data path purging in time-critical routines.
97: *
98: * Too bad C pre-processor doesn't have the power of LISP in macro
99: * expansion...
100: */
101: #if defined(VAX780) && defined(VAX750)
102: #define UBAPURGE(uba, bdp) { \
103: switch (cpu) { \
104: case VAX_780: UBA_PURGE780((uba), (bdp)); break; \
105: case VAX_750: UBA_PURGE750((uba), (bdp)); break; \
106: } \
107: }
108: #endif
109: #if defined(VAX780) && !defined(VAX750)
110: #define UBAPURGE(uba, bdp) { \
111: if (cpu==VAX_780) { \
112: UBA_PURGE780((uba), (bdp)); \
113: } \
114: }
115: #endif
116: #if !defined(VAX780) && defined(VAX750)
117: #define UBAPURGE(uba, bdp) { \
118: if (cpu==VAX_750) { \
119: UBA_PURGE750((uba), (bdp)); \
120: } \
121: }
122: #endif
123: #if !defined(VAX780) && !defined(VAX750)
124: #define UBAPURGE(uba, bdp)
125: #endif
126:
127: /* uba_mr[] */
128: #define UBAMR_MRV 0x80000000 /* map register valid */
129: #define UBAMR_BO 0x02000000 /* byte offset bit */
130: #define UBAMR_DPDB 0x01e00000 /* data path designator field */
131: #define UBAMR_SBIPFN 0x000fffff /* SBI page address field */
132:
133: #define UBAMR_DPSHIFT 21 /* shift to data path designator */
134:
135: /*
136: * Number of UNIBUS map registers. We can't use the last 8k of UNIBUS
137: * address space for i/o transfers since it is used by the devices,
138: * hence have slightly less than 256K of UNIBUS address space.
139: */
140: #define NUBMREG 496
141:
142: /*
143: * Number of unibus buffered data paths and possible uba's per cpu type.
144: */
145: #define NBDP780 15
146: #define NBDP750 3
147: #define NBDP730 0
148: #define MAXNBDP 15
149:
150: #define NUBA780 4
151: #define NUBA750 1
152: #define NUBA730 1
153: #if VAX780
154: #define MAXNUBA 4
155: #else
156: #if VAX750
157: #define MAXNUBA 2
158: #else
159: #define MAXNUBA 1
160: #endif
161: #endif
162:
163: /*
164: * Symbolic addresses of UNIBUS memory for UBAs.
165: */
166: #if VAX730
167: #define UMEM730 ((u_short *)(0xfc0000))
168: #endif
169: #if VAX750
170: #define UMEM750(i) ((u_short *)(0xfc0000-(i)*0x40000))
171: #endif
172: #if VAX780
173: #define UMEM780(i) ((u_short *)(0x20100000+(i)*0x40000))
174: #endif
175:
176: /*
177: * Macro to offset a UNIBUS device address, often expressed as
178: * something like 0172520 by forcing it into the last 8K of UNIBUS space.
179: */
180: #define ubdevreg(addr) (0760000|((addr)&017777))
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