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1.1 ! root 1: /* @(#)if_qereg.h 7.1 (Berkeley) 6/5/86 */ ! 2: ! 3: /* @(#)if_qereg.h 1.2 (ULTRIX) 1/3/85 */ ! 4: ! 5: /**************************************************************** ! 6: * * ! 7: * Licensed from Digital Equipment Corporation * ! 8: * Copyright (c) * ! 9: * Digital Equipment Corporation * ! 10: * Maynard, Massachusetts * ! 11: * 1985, 1986 * ! 12: * All rights reserved. * ! 13: * * ! 14: * The Information in this software is subject to change * ! 15: * without notice and should not be construed as a commitment * ! 16: * by Digital Equipment Corporation. Digital makes no * ! 17: * representations about the suitability of this software for * ! 18: * any purpose. It is supplied "As Is" without expressed or * ! 19: * implied warranty. * ! 20: * * ! 21: * If the Regents of the University of California or its * ! 22: * licensees modify the software in a manner creating * ! 23: * diriviative copyright rights, appropriate copyright * ! 24: * legends may be placed on the drivative work in addition * ! 25: * to that set forth above. * ! 26: * * ! 27: ****************************************************************/ ! 28: /* --------------------------------------------------------------------- ! 29: * Modification History ! 30: * ! 31: * 13 Feb. 84 -- rjl ! 32: * ! 33: * Initial version of driver. derived from IL driver. ! 34: * ! 35: * --------------------------------------------------------------------- ! 36: */ ! 37: ! 38: /* ! 39: * Digital Q-BUS to NI Adapter ! 40: */ ! 41: struct qedevice { ! 42: u_short qe_sta_addr[2]; /* Station address (actually 6 */ ! 43: u_short qe_rcvlist_lo; /* Receive list lo address */ ! 44: u_short qe_rcvlist_hi; /* Receive list hi address */ ! 45: u_short qe_xmtlist_lo; /* Transmit list lo address */ ! 46: u_short qe_xmtlist_hi; /* Transmit list hi address */ ! 47: u_short qe_vector; /* Interrupt vector */ ! 48: u_short qe_csr; /* Command and Status Register */ ! 49: }; ! 50: ! 51: /* ! 52: * Command and status bits (csr) ! 53: */ ! 54: #define QE_RCV_ENABLE 0x0001 /* Receiver enable */ ! 55: #define QE_RESET 0x0002 /* Software reset */ ! 56: #define QE_NEX_MEM_INT 0x0004 /* Non existant mem interrupt */ ! 57: #define QE_LOAD_ROM 0x0008 /* Load boot/diag from rom */ ! 58: #define QE_XL_INVALID 0x0010 /* Transmit list invalid */ ! 59: #define QE_RL_INVALID 0x0020 /* Receive list invalid */ ! 60: #define QE_INT_ENABLE 0x0040 /* Interrupt enable */ ! 61: #define QE_XMIT_INT 0x0080 /* Transmit interrupt */ ! 62: #define QE_ILOOP 0x0100 /* Internal loopback */ ! 63: #define QE_ELOOP 0x0200 /* External loopback */ ! 64: #define QE_STIM_ENABLE 0x0400 /* Sanity timer enable */ ! 65: #define QE_POWERUP 0x1000 /* Tranceiver power on */ ! 66: #define QE_CARRIER 0x2000 /* Carrier detect */ ! 67: #define QE_RCV_INT 0x8000 /* Receiver interrupt */ ! 68: ! 69: /* ! 70: * Transmit and receive ring discriptor --------------------------- ! 71: * ! 72: * The QNA uses the flag, status1 and the valid bit as a handshake/semiphore ! 73: * mechinism. ! 74: * ! 75: * The flag word is written on ( bits 15,15 set to 1 ) when it reads the ! 76: * descriptor. If the valid bit is set it considers the address to be valid. ! 77: * When it uses the buffer pointed to by the valid address it sets status word ! 78: * one. ! 79: */ ! 80: struct qe_ring { ! 81: u_short qe_flag; /* Buffer utilization flags */ ! 82: u_short qe_addr_hi:6, /* Hi order bits of buffer addr */ ! 83: qe_odd_begin:1, /* Odd byte begin and end (xmit)*/ ! 84: qe_odd_end:1, ! 85: qe_fill1:4, ! 86: qe_setup:1, /* Setup packet */ ! 87: qe_eomsg:1, /* End of message flag */ ! 88: qe_chain:1, /* Chain address instead of buf */ ! 89: qe_valid:1; /* Address field is valid */ ! 90: u_short qe_addr_lo; /* Low order bits of address */ ! 91: short qe_buf_len; /* Negative buffer length */ ! 92: u_short qe_status1; /* Status word one */ ! 93: u_short qe_status2; /* Status word two */ ! 94: }; ! 95: ! 96: /* ! 97: * Status word definations (receive) ! 98: * word1 ! 99: */ ! 100: #define QE_OVF 0x0001 /* Receiver overflow */ ! 101: #define QE_CRCERR 0x0002 /* CRC error */ ! 102: #define QE_FRAME 0x0004 /* Framing alignment error */ ! 103: #define QE_SHORT 0x0008 /* Packet size < 10 bytes */ ! 104: #define QE_RBL_HI 0x0700 /* Hi bits of receive len */ ! 105: #define QE_RUNT 0x0800 /* Runt packet */ ! 106: #define QE_DISCARD 0x1000 /* Discard the packet */ ! 107: #define QE_ESETUP 0x2000 /* Looped back setup or eloop */ ! 108: #define QE_ERROR 0x4000 /* Receiver error */ ! 109: #define QE_LASTNOT 0x8000 /* Not the last in the packet */ ! 110: /* word2 */ ! 111: #define QE_RBL_LO 0x00ff /* Low bits of receive len */ ! 112: ! 113: /* ! 114: * Status word definations (transmit) ! 115: * word1 ! 116: */ ! 117: #define QE_CCNT 0x00f0 /* Collision count this packet */ ! 118: #define QE_FAIL 0x0100 /* Heart beat check failure */ ! 119: #define QE_ABORT 0x0200 /* Transmission abort */ ! 120: #define QE_STE16 0x0400 /* Sanity timer default on */ ! 121: #define QE_NOCAR 0x0800 /* No carrier */ ! 122: #define QE_LOSS 0x1000 /* Loss of carrier while xmit */ ! 123: /* word2 */ ! 124: #define QE_TDR 0x3fff /* Time domain reflectometry */ ! 125: ! 126: /* ! 127: * General constant definations ! 128: */ ! 129: #define QEALLOC 0 /* Allocate an mbuf */ ! 130: #define QENOALLOC 1 /* No mbuf allocation */ ! 131: #define QEDEALLOC 2 /* Release an mbuf chain */ ! 132: ! 133: #define QE_NOTYET 0x8000 /* Descriptor not in use yet */ ! 134: #define QE_INUSE 0x4000 /* Descriptor being used by QNA */ ! 135: #define QE_MASK 0xc000 /* Lastnot/error/used mask */
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