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1.1 root 1: /*
2: * Copyright (c) 1986 MICOM-Interlan, Inc., Boxborough Mass
3: * All rights reserved. The Berkeley software License Agreement
4: * specifies the terms and conditions for redistribution.
5: *
6: * @(#)npreg.h 7.1 (Berkeley) 6/5/86
7: */
8:
9: /*
10: * NPREG.H
11: *
12: * This file contain definitions of specific hardware interest
13: * to be used when communicating with the NI1510 Network Processor
14: * Board. More complete information can be found in the NI1510
15: * Multibus compatible Ethernet Communications Processor Hardware
16: * Specification.
17: */
18:
19:
20: #define NNPCNN 4 /* Number of connections per board */
21: #define NPUNIT(a) ((minor(a) >> 4) & 0x0F)
22: #define NPCONN(a) ((minor(a)) & 0x03)
23:
24: #define TRUE 1
25: #define FALSE 0
26:
27: #define IBOOTADDR 0xF8000l /* Addr of 80186 Boot ROM */
28: #define INETBOOT 0xF8087l
29: #define IXEQADDR 0x400 /* Where to begin Board image XEQ */
30: #define DIAGTIME 1200 /* Time for timeout /HZ seconds */
31:
32: #define DELAYTIME 1000000L /* delay count */
33: #define NPDELAY(N) {register int n = (N) >> 1; while(--n > 0); }
34:
35: /* Handy macros for talking to the Board */
36:
37: #define RESET(x) (WCSR3(x->iobase,0xff))
38: #define CLEARINT(x) {unsign16 y; y = RCSR2(x->iobase); }
39: #define INTNI(x) (WCSR1(x->iobase,0xFF))
40:
41: /* Command and Status Register (CSR) Definitions */
42:
43: /*
44: * CSR0 is the only direct means for data transfer between the host processor
45: * and the 3510. Access is controlled by the 80186 who sets the CSR1 Enable and
46: * Ready bits to allow writing here. Writing to this register will always
47: * result in an interrupt to the 80186.
48: */
49:
50: /*
51: * Bit definitions for CSR1.
52: */
53:
54: #define NPRFU 0x01 /* Reserved for Future Use */
55: #define NPHOK 0x02 /* Hardware OK */
56: #define NPLAN 0x04 /* Logic 0 indicates operational LAN exists */
57: #define NP_IP 0x08 /* Interrupt pending from this board */
58: #define NP_IE 0x10 /* Interrupts enabled for this board */
59: #define NPRDR 0x20 /* Set when 80186 writes data into CSR0 */
60: #define NPRDY 0x40 /* CSR0 ready to accept data */
61: #define NPENB 0x80 /* CSR0 available for use by the host */
62:
63: /*
64: * Bit defintions for CSR0 Command Block
65: */
66:
67: #define NPLST 0x20 /* Last Command */
68: #define NPCMD 0x80 /* Shared Memory Address */
69: #define NPBGN 0x200 /* Begin Execution in On-Board Memory */
70: #define NPCBI 0x800 /* Interrupt at completion of Command Block */
71: #define NPDMP 0x2000 /* Dump 80186 On-Board Memory to Multibus */
72: #define NPLD 0x8000 /* Load 80186 On-board Memory from Multibus */
73:
74: /*
75: * CSR0 Count definitions. These are the lengths of the Command Blocks for the
76: * CSR0 commands above (not counting the Command Word itself).
77: */
78:
79: #define LSTCNT 0
80: #define CMDCNT 2
81: #define BGNCNT 2
82: #define CBICNT 1
83: #define DMPCNT 5
84: #define LDCNT 5
85: #define IOCNT 5
86:
87: /* Macros for reading and writing CSR's (Control and Status Registers) */
88:
89: #define WCSR0(x,y) ((x)->CSR0 = y)
90: #define WCSR1(x,y) ((x)->CSR1 = y)
91: #define WCSR2(x,y) ((x)->CSR2 = y)
92: #define WCSR3(x,y) ((x)->CSR3 = y)
93:
94: #define RCSR0(x) ((x)->CSR0)
95: #define RCSR1(x) ((x)->CSR1)
96: #define RCSR2(x) ((x)->CSR2)
97: #define RCSR3(x) ((x)->CSR3)
98:
99: #define NPRESET 0x01 /* reset the board */
100: #define NPSTART 0x04 /* start board execution */
101: #define NPGPANIC 0x05 /* Get panic message */
102: #define NPINIT 0x06 /* initialize software on board */
103: #define NPSTATS 0x07
104: #define NPRCSR0 0x08 /* read CSR0 */
105: #define NPRCSR1 0x09 /* read CSR1 */
106: #define NPRCSR2 0x0a /* read CSR2 */
107: #define NPRCSR3 0x0b /* read CSR3 */
108: #define NPWCSR0 0x0c /* write CSR0 */
109: #define NPWCSR1 0x0d /* write CSR1 */
110: #define NPWCSR2 0x0e /* write CSR2 */
111: #define NPWCSR3 0x0f /* write CSR3 */
112: #define NPPOLL 0x10
113: #define NPKILL 0x11
114: #define NPSETPROT 0x12 /* set the protocol to use */
115: #define NPSETBOARD 0x13 /* set board to use */
116: #define NPSETNPDEB 0x14 /* set nc debuging level */
117: #define NPSETADDR 0x15 /* set host address */
118: #define NPNETBOOT 0x16 /* boot from the network */
119:
120: /* ICP Board Requests */
121:
122: #define ICPLOAD 0x02
123: #define ICPDUMP 0x03
124: #define ICPPANIC 0x05
125: #define ICPPOLL 0x10
126:
127: /*
128: * Typedefs for the VAX
129: */
130:
131: typedef short sign16; /* 16 bit signed value */
132: typedef unsigned short unsign16; /* 16 bit unsigned value */
133: typedef unsigned unsign32; /* 32 bit unsigned value */
134: typedef long paddr_t; /* Physical addresses */
135:
136:
137: /*
138: * Tunables
139: */
140:
141:
142: #define NUMCQE 40 /* Number of CQE's per board */
143:
144: /* Host configuration word in Status Block */
145:
146: /*
147: * To disable the lock/unlock internal function calls clear the 0x8000
148: * bit in the host configuration word (HOSTCONF)
149: */
150:
151: #define HOSTCONF 0x0109 /* See above */
152: #define LOWBYTE 1
153: #define HIGHBYTE 0
154: #define BUFFMAPPED 0
155:
156: /*
157: * Memory mapping definintions for PM68DUAL hardware.
158: */
159:
160: #ifdef PM68DUAL
161: #define PISHMEM 0x200000
162: #define PISHMEMSIZE 2
163: #define PIOFF 0x8000 /* change this to unique mem add. */
164: #define PIWINDOW MBUSBUFR + PIOFF
165: #define WINDOWSIZE 2
166: #endif
167: #define NPMAXXFR 32768 /* Maximum number of bytes / read */
168:
169: /*
170: * Define the protocols supported by the NP Driver.
171: */
172:
173: #define NONE 0x00 /* No protocols active for a process */
174: #define NPMAINT 0x01 /* Maintenance protocol, superusers only */
175: #define NPNTS 0x02 /* NTS Terminal Server */
176: #define NPDLA 0x04 /* Direct Datalink Access */
177: #define NPXNS 0x06 /* Xerox NS ITP */
178: #define NPTCP 0x08 /* TCP/IP */
179: #define NPISO 0x0A /* ISO */
180: #define NPCLCONN 0xFF /* Closed connection, i.e. no protocol */
181:
182: /*
183: * Convert the protocol to a value used in the Device Protocol Mask field
184: * of the Shared Memory Status Block.
185: */
186:
187: #define PROTOMASK(x) ( 1 << (x) )
188:
189: /*
190: * Special requests handled by the NP Driver
191: */
192:
193: #define OS_STP 03400 /* Shut down connection on I Board */
194: #define NPSTOP 3 /* Conversion from above (OS_STP) */
195: #define NPCHNGP 50 /* Change the protocol on a connection */
196: #define NPCHNGB 51 /* Change the Board number */
197:
198: /*
199: * Miscellaneous
200: */
201:
202: #define ON 0x8000 /* Used for Command Q's scan and change flag */
203: #define UBADDRMASK 0x3FFFF /* 18 bit UNIBUS address */
204: #define INTMASK 0xFFFFFFFC /* Used for address validation */
205: #define CMDMASK 0xFFFF /* Mask ioctl cmd field (see ioctl.h) */
206: #define NPPSADDR 0x324 /* Pointer to addr of on-board panic string */
207: #define PANLEN 133 /* length of the panic buffer */
208:
209: /*
210: * Map function code from user to I-Board format
211: */
212:
213: #define FUNCTMAP(x) (((x) << 6) | 077) /* Maps user function to NP funcs */
214:
215: /*
216: * Round up to a 16 byte boundary
217: */
218:
219: #define ROUND16(x) (((x) + 15) & (~0x0F)) /* Round to 16 byte boundary */
220: #define ADDR24 1 /* Used by iomalloc() to specify 24 bit address */
221:
222: #define NPERRSHIFT 8 /* Used in function ReqDone() */
223: #define NPOK 0
224:
225: #define LOWORD(X) (((ushort *)&(X))[0])
226: #define HIWORD(X) (((ushort *)&(X))[1])
227:
228: /* Everyday flag settings */
229:
230: #define NPSET 1
231: #define NPCLEAR 0
232:
233: /*
234: * Command Queue Elements are the primary data structure for passing data
235: * between the driver and the device.
236: */
237:
238: struct CQE {
239:
240: struct npreq *cqe_reqid;/* Address of asssociated npreq */
241: unsign32 cqe_famid; /* Family ID (Process ID) */
242: unsign16 cqe_func; /* I/O function to be performed */
243: #ifdef mc68000
244: char cqe_prot; /* Protocol type for I/O request */
245: char cqe_lenrpb; /* Length of the RPB in bytes */
246: #else
247: char cqe_lenrpb; /* Length of the RPB in bytes */
248: char cqe_prot; /* Protocol type for I/O request */
249: #endif
250: unsign16 cqe_ust0; /* Protocol status return */
251: unsign16 cqe_ust1; /* Protocol status return */
252: unsign16 cqe_devrsv; /* Reserved for use by device only! */
253: #ifdef mc68000
254: char cqe_char; /* CQE characteristics */
255: char cqe_sts; /* Status return from device to user */
256: char cqe_wind; /* Buffer mapping window size (page units) */
257: char cqe_nbuf; /* Number of data buffers for I/O */
258: #else
259: char cqe_sts; /* Status return from device to user */
260: char cqe_char; /* CQE characteristics */
261: char cqe_nbuf; /* Number of data buffers for I/O */
262: char cqe_wind; /* Buffer mapping window size (page units) */
263: #endif
264: unsign16 cqe_bcnt; /* Total number of bytes in the data buffer */
265: unsign16 cqe_unused; /* Unused */
266: unsign16 cqe_dma[2]; /* Address of the MULTIBUS data buffer */
267: unsign16 rpb1; /* Word 1 of protocol parameters */
268: unsign16 rpb2; /* Word 2 of protocol parameters */
269: unsign16 rpb3; /* Word 3 of protocol parameters */
270: unsign16 rpb4; /* Word 4 of protocol parameters */
271: unsign16 rpb5; /* Word 5 of protocol parameters */
272: unsign16 rpb6; /* Word 6 of protocol parameters */
273: unsign16 rpb7; /* Word 7 of protocol parameters */
274: unsign16 rpb8; /* Word 8 of protocol parameters */
275: unsign16 rpb9; /* Word 9 of protocol parameters */
276: unsign16 rpb10; /* Word 10 of protocol parameters */
277: unsign16 rpb11; /* Word 11 of protocol parameters */
278: unsign16 rpb12; /* Word 12 of protocol parameters */
279:
280: };
281:
282: /*
283: * NP Driver Request structure contains information about a request
284: * maintained solely by the driver. One per CQE, plus a header.
285: */
286:
287: struct npreq {
288:
289: struct npreq *forw; /* Forward pointer for active list */
290: struct npreq *back; /* Backward pointer for active list */
291: struct npreq *free; /* Next member on free list */
292: struct CQE *element; /* CQE associated with this request */
293: int flags; /* Always useful */
294: int reqcnt; /* Request count for reqtab */
295: int bufoffset; /* Offset into buffer for turns */
296: int bytecnt; /* Number of bytes to transfer */
297: caddr_t virtmem; /* Virtual address of buffer */
298: int mapbase; /* Address of the mapping register */
299: int mapsize; /* Size of mapped area */
300: caddr_t bufaddr; /* Address of the user buffer */
301: struct buf buf; /* Buf structure needed for mem. mgmt */
302: struct proc *procp; /* Pointer to process of requestor */
303: caddr_t user; /* Structure passed by user from itpuser.h */
304: int (*intr)(); /* Ptr to routine to call at interrupt time */
305: };
306:
307: /*
308: * Npmaster structure, one per device, is used for boardwise centralization
309: * of relevant information including queues, I/O addresses and request pools.
310: */
311:
312: struct npmaster {
313:
314: struct npmaster *next; /* Linked list of these, NULL terminator */
315: struct npspace *shmemp; /* Shared memory address (driver <-> device) */
316: struct uba_device *devp; /* UBA Device for this unit */
317: struct NPREG *iobase; /* I/O base address for this board */
318: struct npreq *reqtab; /* Header for pool of CQE requests */
319: int iomapbase; /* Base index of I/O map reg's allocated */
320: int flags; /* State of the Board */
321: int unit; /* Unit number of this device */
322: int vector; /* Interrupt vector for this unit */
323: };
324:
325: struct npconn {
326:
327: struct npmaster *unit; /* Unit number (board) of this connection */
328: unsign16 protocol; /* Protocol used on this connection */
329: struct buf np_wbuf; /* write buf structure for raw access */
330: struct buf np_rbuf; /* read buf structure for raw access */
331: };
332:
333: struct NPREG {
334: unsign16 CSR0; /* Control Status Register 0 */
335: unsign16 CSR1; /* Control Status Register 1 */
336: unsign16 CSR2; /* Control Status Register 2 */
337: unsign16 CSR3; /* Control Status Register 3 */
338:
339: };
340:
341: /*
342: * The following structures are used for communicating with the
343: * Intelligent Board and are located in Shared Memory.
344: */
345:
346: /*
347: * Status Block
348: */
349:
350: struct NpStat{
351:
352: unsign16 sb_drw; /* Device Request Word */
353: unsign16 sb_hcw; /* Host Configuration Word */
354: unsign16 sb_dcw; /* Device Configuration Word */
355: unsign16 sb_dpm; /* Device Protocol Mask */
356: unsign16 sb_dcq; /* Offset to Device CQ */
357: unsign16 sb_hcq; /* Offset to Host CQ */
358: };
359:
360: /*
361: * Command Queue, two per device. One is owned by the driver and the other
362: * is owned by the device.
363: */
364:
365: struct CmdQue {
366:
367: unsign16 scanflag; /* Scan Flag, MSB set if being scanned */
368: unsign16 chngflag; /* Change Flag, MSB set by initiator */
369: unsign16 cq_wrap; /* Offset to last CQE entry +2 */
370: unsign16 cq_add; /* Offset to add a CQE to the queue */
371: unsign16 cq_rem; /* Offset to remove a CQE from the queue */
372: unsign16 cq_cqe[NUMCQE]; /* Command Queue Element Offsets */
373: };
374:
375: /*
376: * Structure of the shared memory area per board. Declared this way to avoid
377: * compiler word alignment vagaries when computing offsets.
378: */
379:
380: struct npspace {
381:
382: struct NpStat statblock; /* Status Block */
383: struct CmdQue devcq; /* Device's Command Queue */
384: struct CmdQue hostcq; /* Host's Command Queue */
385: struct CQE elements[NUMCQE]; /* Shared Command Queue Elements */
386: unsign16 filler[8]; /* Here for 16 byte alignment */
387: };
388:
389: /*
390: * Structure of array of base addresses of I-Board controllers
391: * (See global data definitions in np.c)
392: */
393:
394: struct npbase {
395: caddr_t baseaddr;
396: };
397:
398: /* State of the NP Driver as kept in NpState */
399:
400: #define ICPAVAIL 0x01 /* ICP is waiting for a request */
401:
402: /* Tells ICP Process that there are no more requests for this board */
403:
404: #define BRDDONE 1
405:
406: /* Flags used by the driver (npreq structure) to monitor status of requests */
407:
408: #define REQDONE 0x01 /* Request completed */
409: #define IOIFC 0x02 /* Internal Function Code Request */
410: #define IOERR 0x04 /* Error on Request */
411: #define NPPEND 0x08 /* Unused at this time */
412: #define IOABORT 0x10 /* Request aborted by ICP */
413: #define KERNREQ 0x20 /* Request was from the kernel */
414: #define WANTREQ 0x40 /* Process is waiting for a npreq structure */
415: #define NPUIO 0x80 /* Process doing physio */
416:
417: /* Service Request Commands from the Intelligent Board */
418:
419: #define NOREQ 0x00 /* No service requested */
420: #define NPLOAD 0x01 /* Dump request */
421: #define NPDUMP 0x02 /* Load request */
422: #define NPPANIC 0x100 /* Panic request */
423:
424: /* Definitions of Status returned from the I-Board */
425:
426: #define NPDONE 0x01 /* Normal completion */
427: #define NPIFC 0x00 /* Internal Function Code request */
428: #define NPPERR 0x80 /* Protocol error */
429: #define NPMERR 0x82 /* Memory allocation failure on I-Board */
430:
431: /* Definitions of IFC type requests from I-Board */
432:
433: #define NPLOCK 0x64 /* Lock the process's data area */
434: #define NPUNLOCK 0xA4 /* Unlock the process */
435: #define NPREMAP 0x124 /* Window turn */
436:
437: /* Definition of flags for the Npmaster structure */
438:
439: #define CSRPEND 0x01 /* CSR0 command pending */
440: #define PANICREQ 0x02 /* Panic request */
441: #define DUMPREQ 0x04 /* Dump request */
442: #define LOADREQ 0x08 /* Load request */
443: #define BOARDREQ 0x10 /* Any request by the board */
444: #define BADBOARD 0x20 /* Board disabled */
445: #define AVAILABLE 0x40 /* Board available */
446: #define BRDRESET 0x80 /* Board is being reset */
447: #define PANIC1 0x100 /* Driver wants panic address */
448: #define PANIC2 0x200 /* Driver wants panic string */
449: #define PANIC3 0x400 /* Clear first byte of panic string */
450:
451: /*
452: * Debugging Constants
453: */
454:
455: #define DEBENTRY 0x0001 /* debug entry points */
456: #define DEBMEM 0x0002 /* debug memory */
457: #define DEBREQ 0x0004 /* debug requests */
458: #define DEBCQE 0x0008 /* debug cqe's */
459: #define DEBCQ 0x0010 /* debug cq's */
460: #define DEBMAINT 0x0020 /* debug maintainance requests */
461: #define DEBINTR 0x0040 /* debug interrupt routines */
462: #define DEBINIT 0x0080 /* debug initialization routines */
463: #define DEBIFC 0x0100 /* debug Internal function codes */
464: #define DEBIOCTL 0x0200 /* debug ioctl calls */
465: #define DEBOPEN 0x0400 /* debug open calls */
466: #define DEBIO 0x0800 /* debug read & write calls */
467: #define DEBCSR 0x1000 /* debug CSR commands */
468: #define DEBLOCK 0x2000 /* debug lock / unlock calls */
469: #define NOBOARD 0x4000 /* debug user/host interface */
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