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Annotation of 43BSDReno/sys/hp300/cpu.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * Copyright (c) 1988 University of Utah.
        !             3:  * Copyright (c) 1982, 1990 The Regents of the University of California.
        !             4:  * All rights reserved.
        !             5:  *
        !             6:  * This code is derived from software contributed to Berkeley by
        !             7:  * the Systems Programming Group of the University of Utah Computer
        !             8:  * Science Department.
        !             9:  *
        !            10:  * Redistribution is only permitted until one year after the first shipment
        !            11:  * of 4.4BSD by the Regents.  Otherwise, redistribution and use in source and
        !            12:  * binary forms are permitted provided that: (1) source distributions retain
        !            13:  * this entire copyright notice and comment, and (2) distributions including
        !            14:  * binaries display the following acknowledgement:  This product includes
        !            15:  * software developed by the University of California, Berkeley and its
        !            16:  * contributors'' in the documentation or other materials provided with the
        !            17:  * distribution and in all advertising materials mentioning features or use
        !            18:  * of this software.  Neither the name of the University nor the names of
        !            19:  * its contributors may be used to endorse or promote products derived from
        !            20:  * this software without specific prior written permission.
        !            21:  * THIS SOFTWARE IS PROVIDED AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
        !            22:  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
        !            23:  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
        !            24:  *
        !            25:  * from: Utah $Hdr: cpu.h 1.13 89/06/23$
        !            26:  *
        !            27:  *     @(#)cpu.h       7.2 (Berkeley) 5/25/90
        !            28:  */
        !            29: 
        !            30: /* values for machineid */
        !            31: #define HP_320         0       /* 16Mhz 68020+HP MMU+16K external cache */
        !            32: #define HP_330         1       /* 16Mhz 68020+68851 MMU */
        !            33: #define HP_350         2       /* 25Mhz 68020+HP MMU+32K external cache */
        !            34: #define HP_360         3       /* 25Mhz 68030 */
        !            35: #define HP_370         4       /* 33Mhz 68030+64K external cache */
        !            36: #define HP_340         5       /* 16Mhz 68030 */
        !            37: #define HP_375         6       /* 50Mhz 68030+32K external cache */
        !            38: 
        !            39: /* values for mmutype (assigned for quick testing) */
        !            40: #define MMU_68030      -1      /* 68030 on-chip subset of 68851 */
        !            41: #define MMU_HP         0       /* HP proprietary */
        !            42: #define MMU_68851      1       /* Motorola 68851 */
        !            43: 
        !            44: /* values for ectype */
        !            45: #define EC_PHYS                -1      /* external physical address cache */
        !            46: #define EC_NONE                0       /* no external cache */
        !            47: #define EC_VIRT                1       /* external virtual address cache */
        !            48: 
        !            49: /* values for cpuspeed (not really related to clock speed due to caches) */
        !            50: #define MHZ_8          1
        !            51: #define MHZ_16         2
        !            52: #define MHZ_25         3
        !            53: #define MHZ_33         4
        !            54: #define MHZ_50         6
        !            55: 
        !            56: #ifdef KERNEL
        !            57: extern int machineid, mmutype, ectype;
        !            58: extern int IObase;
        !            59: 
        !            60: /* what is this supposed to do? i.e. how is it different than startrtclock? */
        !            61: #define        enablertclock()
        !            62: 
        !            63: #endif
        !            64: 
        !            65: /* physical memory sections */
        !            66: #define ROMBASE                (0x00000000)
        !            67: #define IOBASE         (0x00200000)
        !            68: #define IOTOP          (0x01000000)
        !            69: #define MAXADDR                (0xFFFFF000)
        !            70: 
        !            71: /* IO space stuff */
        !            72: #define EXTIOBASE      (0x00600000)
        !            73: #define        IOCARDSIZE      (0x10000)
        !            74: #define        IOMAPSIZE       (btoc(IOTOP-IOBASE))
        !            75: #define        IOP(x)          ((x) - IOBASE)
        !            76: #define        IOV(x)          (((x) - IOBASE) + (int)&IObase)
        !            77: #define UNIOV(x)       ((x) - (int)&IObase + IOBASE)
        !            78: 
        !            79: /* DIO II uncached address space */
        !            80: #define DIOIIBASE      (0x01000000)
        !            81: #define DIOIITOP       (0x20000000)
        !            82: #define DIOIICSIZE     (0x00400000)
        !            83: 
        !            84: /* offsets for longword read/write */
        !            85: #define        MMUSSTP         IOP(0x5F4000)
        !            86: #define        MMUUSTP         IOP(0x5F4004)
        !            87: #define        MMUTBINVAL      IOP(0x5F4008)
        !            88: #define        MMUSTAT         IOP(0x5F400C)
        !            89: #define        MMUCMD          MMUSTAT
        !            90: 
        !            91: #define MMU_UMEN       0x0001  /* enable user mapping */
        !            92: #define MMU_SMEN       0x0002  /* enable supervisor mapping */
        !            93: #define MMU_CEN                0x0004  /* enable data cache */
        !            94: #define MMU_BERR       0x0008  /* bus error */
        !            95: #define MMU_IEN                0x0020  /* enable instruction cache */
        !            96: #define MMU_FPE                0x0040  /* enable 68881 FP coprocessor */
        !            97: #define MMU_WPF                0x2000  /* write protect fault */
        !            98: #define MMU_PF         0x4000  /* page fault */
        !            99: #define MMU_PTF                0x8000  /* page table fault */
        !           100: 
        !           101: #define MMU_FAULT      (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR)
        !           102: #define MMU_ENAB       (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE)
        !           103: 
        !           104: #define PMMU_LVLMASK   0x0007
        !           105: #define PMMU_INV       0x0400
        !           106: #define PMMU_WP                0x0800
        !           107: #define PMMU_ALV       0x1000
        !           108: #define PMMU_SO                0x2000
        !           109: #define PMMU_LV                0x4000
        !           110: #define PMMU_BE                0x8000
        !           111: 
        !           112: #define PMMU_FAULT     (PMMU_WP|PMMU_INV)
        !           113: 
        !           114: /* function code for user data space */
        !           115: #define        FC_USERD        1
        !           116: /* methinks the following is used to selectively clear TLB entries */
        !           117: #define FC_PURGE       3
        !           118: 
        !           119: /* fields in the 68020 cache control register */
        !           120: #define IC_ENABLE      0x0001  /* enable instruction cache */
        !           121: #define IC_FREEZE      0x0002  /* freeze instruction cache */
        !           122: #define IC_CE          0x0004  /* clear instruction cache entry */
        !           123: #define IC_CLR         0x0008  /* clear entire instruction cache */
        !           124: 
        !           125: /* additional fields in the 68030 cache control register */
        !           126: #define IC_BE          0x0010  /* instruction burst enable */
        !           127: #define DC_ENABLE      0x0100  /* data cache enable */
        !           128: #define DC_FREEZE      0x0200  /* data cache freeze */
        !           129: #define DC_CE          0x0400  /* clear data cache entry */
        !           130: #define DC_CLR         0x0800  /* clear entire data cache */
        !           131: #define DC_BE          0x1000  /* data burst enable */
        !           132: #define DC_WA          0x2000  /* write allocate */
        !           133: 
        !           134: #define CACHE_ON       (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
        !           135: #define CACHE_OFF      (DC_CLR|IC_CLR)
        !           136: #define CACHE_CLR      (CACHE_ON)
        !           137: #define IC_CLEAR       (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
        !           138: #define DC_CLEAR       (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)

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