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Annotation of 43BSDReno/sys/hpdev/dcareg.h, revision 1.1.1.1

1.1       root        1: /*
                      2:  * Copyright (c) 1982, 1986, 1990 Regents of the University of California.
                      3:  * All rights reserved.
                      4:  *
                      5:  * Redistribution is only permitted until one year after the first shipment
                      6:  * of 4.4BSD by the Regents.  Otherwise, redistribution and use in source and
                      7:  * binary forms are permitted provided that: (1) source distributions retain
                      8:  * this entire copyright notice and comment, and (2) distributions including
                      9:  * binaries display the following acknowledgement:  This product includes
                     10:  * software developed by the University of California, Berkeley and its
                     11:  * contributors'' in the documentation or other materials provided with the
                     12:  * distribution and in all advertising materials mentioning features or use
                     13:  * of this software.  Neither the name of the University nor the names of
                     14:  * its contributors may be used to endorse or promote products derived from
                     15:  * this software without specific prior written permission.
                     16:  * THIS SOFTWARE IS PROVIDED AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
                     17:  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
                     18:  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
                     19:  *
                     20:  *     @(#)dcareg.h    7.2 (Berkeley) 6/27/90
                     21:  */
                     22: 
                     23: struct dcadevice {
                     24:        u_char  dca_pad0;
                     25:        volatile u_char dca_irid;
                     26:        volatile short  dca_ic;
                     27:        volatile short  dca_ocbrc;
                     28:        volatile short  dca_lcsm;
                     29:        short   dca_pad1[4];
                     30:        u_char  dca_pad2;
                     31:        volatile u_char dca_data;
                     32:        volatile short  dca_ier;
                     33:        u_char  dca_pad4;
                     34:        volatile u_char dca_iir;
                     35:        volatile short  dca_cfcr;
                     36:        volatile short  dca_mcr;
                     37:        volatile short  dca_lsr;
                     38:        u_char  dca_pad3;
                     39:        volatile u_char dca_msr;
                     40: };
                     41: 
                     42: /* interface reset/id */
                     43: #define        DCAID0          0x02
                     44: #define DCAREMID0      0x82
                     45: #define        DCAID1          0x42
                     46: #define DCAREMID1      0xC2
                     47: 
                     48: /* interrupt control */
                     49: #define        DCAIPL(x)       ((((x) >> 4) & 3) + 3)
                     50: #define        IC_IR           0x40
                     51: #define        IC_IE           0x80
                     52: 
                     53: /* 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier) */
                     54: #define        DCABRD(x)       (153600 / (x))
                     55: 
                     56: /* interrupt enable register */
                     57: #define        IER_ERXRDY      0x1
                     58: #define        IER_ETXRDY      0x2
                     59: #define        IER_ERLS        0x4
                     60: #define        IER_EMSC        0x8
                     61: 
                     62: /* interrupt identification register */
                     63: #define        IIR_NOPEND      0x1
                     64: #define        IIR_IMASK       0x6
                     65: #define        IIR_RLS         6
                     66: #define        IIR_RXRDY       4
                     67: #define        IIR_TXRDY       2
                     68: #define        IIR_MLSC        0
                     69: 
                     70: /* character format control register */
                     71: #define        CFCR_DLAB       0x80
                     72: #define        CFCR_SBREAK     0x40
                     73: #define        CFCR_PZERO      0x30
                     74: #define        CFCR_PONE       0x20
                     75: #define        CFCR_PEVEN      0x10
                     76: #define        CFCR_PODD       0x00
                     77: #define        CFCR_PENAB      0x08
                     78: #define        CFCR_STOPB      0x04
                     79: #define        CFCR_8BITS      0x03
                     80: #define        CFCR_7BITS      0x02
                     81: #define        CFCR_6BITS      0x01
                     82: #define        CFCR_5BITS      0x00
                     83: 
                     84: /* modem control register */
                     85: #define        MCR_LOOPBACK    0x10
                     86: #define        MCR_SRTS        0x08
                     87: #define        MCR_DRS         0x04
                     88: #define        MCR_RTS         0x02
                     89: #define        MCR_DTR         0x01
                     90: 
                     91: /* line status register */
                     92: #define        LSR_TSRE        0x40
                     93: #define        LSR_TXRDY       0x20
                     94: #define        LSR_BI          0x10
                     95: #define        LSR_FE          0x08
                     96: #define        LSR_PE          0x04
                     97: #define        LSR_OE          0x02
                     98: #define        LSR_RXRDY       0x01
                     99: 
                    100: /* modem status register */
                    101: #define        MSR_DCD         0x80
                    102: #define        MSR_RI          0x40
                    103: #define        MSR_DSR         0x20
                    104: #define        MSR_CTS         0x10
                    105: #define        MSR_DDCD        0x08
                    106: #define        MSR_TERI        0x04
                    107: #define        MSR_DDSR        0x02
                    108: #define        MSR_DCTS        0x01
                    109: 
                    110: /*
                    111:  * WARNING: Serial console is assumed to be at SC9
                    112:  * and CONUNIT must be 0.
                    113:  */
                    114: #define CONADDR        ((struct dcadevice *)(IOV(EXTIOBASE + (9 * IOCARDSIZE))))
                    115: #define CONUNIT        (0)

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