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1.1 root 1: /*
2: * Copyright (c) 1988 University of Utah.
3: * Copyright (c) 1990 The Regents of the University of California.
4: * All rights reserved.
5: *
6: * This code is derived from software contributed to Berkeley by
7: * the Systems Programming Group of the University of Utah Computer
8: * Science Department.
9: *
10: * Redistribution is only permitted until one year after the first shipment
11: * of 4.4BSD by the Regents. Otherwise, redistribution and use in source and
12: * binary forms are permitted provided that: (1) source distributions retain
13: * this entire copyright notice and comment, and (2) distributions including
14: * binaries display the following acknowledgement: This product includes
15: * software developed by the University of California, Berkeley and its
16: * contributors'' in the documentation or other materials provided with the
17: * distribution and in all advertising materials mentioning features or use
18: * of this software. Neither the name of the University nor the names of
19: * its contributors may be used to endorse or promote products derived from
20: * this software without specific prior written permission.
21: * THIS SOFTWARE IS PROVIDED AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
22: * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
23: * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
24: *
25: * from: Utah $Hdr: grf_rbreg.h 1.8 89/08/25$
26: *
27: * @(#)grf_rbreg.h 7.1 (Berkeley) 5/8/90
28: */
29:
30: /*
31: * Map of the Renaissance frame buffer controller chip in memory ...
32: */
33:
34: #define rb_waitbusy(regaddr) \
35: while (((struct rboxfb *)(regaddr))->wbusy & 0x01) DELAY(100)
36:
37: #define CM1RED ((struct rencm *)(ip->regbase + 0x6400))
38: #define CM1GRN ((struct rencm *)(ip->regbase + 0x6800))
39: #define CM1BLU ((struct rencm *)(ip->regbase + 0x6C00))
40: #define CM2RED ((struct rencm *)(ip->regbase + 0x7400))
41: #define CM2GRN ((struct rencm *)(ip->regbase + 0x7800))
42: #define CM2BLU ((struct rencm *)(ip->regbase + 0x7C00))
43:
44: #define vu_char volatile u_char
45: #define vu_short volatile u_short
46: #define vu_int volatile u_int
47:
48: struct rencm {
49: u_char :8, :8, :8;
50: vu_char value;
51: };
52:
53: struct rboxfb {
54: u_char filler1[1];
55: vu_char reset; /* reset register 0x01 */
56: vu_char fb_address; /* frame buffer address 0x02 */
57: vu_char interrupt; /* interrupt register 0x03 */
58: u_char filler1a;
59: vu_char fbwmsb; /* frame buffer width MSB 0x05 */
60: u_char filler1b;
61: vu_char fbwlsb; /* frame buffer width MSB 0x07 */
62: u_char filler1c;
63: vu_char fbhmsb; /* frame buffer height MSB 0x09 */
64: u_char filler1d;
65: vu_char fbhlsb; /* frame buffer height MSB 0x0b */
66: u_char filler1e;
67: vu_char dwmsb; /* display width MSB 0x0d */
68: u_char filler1f;
69: vu_char dwlsb; /* display width MSB 0x0f */
70: u_char filler1g;
71: vu_char dhmsb; /* display height MSB 0x11 */
72: u_char filler1h;
73: vu_char dhlsb; /* display height MSB 0x13 */
74: u_char filler1i;
75: vu_char fbid; /* frame buffer id 0x15 */
76: u_char filler1j[0x47];
77: vu_char fbomsb; /* frame buffer offset MSB 0x5d */
78: u_char filler1k;
79: vu_char fbolsb; /* frame buffer offset LSB 0x5f */
80: u_char filler2[16359];
81: vu_char wbusy; /* window mover is active 0x4047 */
82: u_char filler3[0x405b - 0x4048];
83: vu_char scanbusy; /* scan converteris active 0x405B */
84: u_char filler3b[0x4083 - 0x405c];
85: vu_char video_enable; /* drive vid. refresh bus 0x4083 */
86: u_char filler4[3];
87: vu_char display_enable; /* enable the display 0x4087 */
88: u_char filler5[8];
89: vu_int write_enable; /* write enable register 0x4090 */
90: u_char filler6[11];
91: vu_char wmove; /* start window mover 0x409f */
92: u_char filler7[3];
93: vu_char blink; /* blink register 0x40a3 */
94: u_char filler8[15];
95: vu_char fold; /* fold register 0x40b3 */
96: vu_int opwen; /* overlay plane write enable 0x40b4 */
97: u_char filler9[3];
98: vu_char tmode; /* Tile mode size 0x40bb */
99: u_char filler9a[3];
100: vu_char drive; /* drive register 0x40bf */
101: u_char filler10[3];
102: vu_char vdrive; /* vdrive register 0x40c3 */
103: u_char filler10a[0x40cb-0x40c4];
104: vu_char zconfig; /* Z-buffer mode 0x40cb */
105: u_char filler11a[2];
106: vu_short tpatt; /* Transparency pattern 0x40ce */
107: u_char filler11b[3];
108: vu_char dmode; /* dither mode 0x40d3 */
109: u_char filler11c[3];
110: vu_char en_scan; /* enable scan board to DTACK 0x40d7 */
111: u_char filler11d[0x40ef-0x40d8];
112: vu_char rep_rule; /* replacement rule 0x40ef */
113: u_char filler12[2];
114: vu_short source_x; /* source x 0x40f2 */
115: u_char filler13[2];
116: vu_short source_y; /* source y 0x40f6 */
117: u_char filler14[2];
118: vu_short dest_x; /* dest x 0x40fa */
119: u_char filler15[2];
120: vu_short dest_y; /* dest y 0x40fe */
121: u_char filler16[2];
122: vu_short wwidth; /* window width 0x4102 */
123: u_char filler17[2];
124: vu_short wheight; /* window height 0x4106 */
125: u_char filler18[18];
126: vu_short patt_x; /* pattern x 0x411a */
127: u_char filler19[2];
128: vu_short patt_y; /* pattern y 0x411e */
129: u_char filler20[0x8012 - 0x4120];
130: vu_short te_status; /* transform engine status 0x8012 */
131: u_char filler21[0x1ffff-0x8014];
132: };
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