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Annotation of 43BSDReno/sys/tahoe/mem.h, revision 1.1.1.1

1.1       root        1: /*
                      2:  *     @(#)mem.h       7.1 (Berkeley) 5/21/88
                      3:  */
                      4: 
                      5: /*
                      6:  * Memory controller registers
                      7:  *
                      8:  */
                      9: 
                     10: 
                     11: /*
                     12:  * Some bits definition for MCR
                     13:  */
                     14: 
                     15: #define        EED     0x01            /* Enable error detection */
                     16: #define        EEC     0x02            /* Enable error correction */
                     17: #define        WMD     0x04            /* Write memory diagnostic */
                     18: #define        RMD     0x08            /* Read memory diagnostic */
                     19: #define        INT     0x20            /* Init = power on bit */
                     20: #define        CEC     0x40            /* Clear error count */
                     21: #define        CME     0x80            /* Clear memory error */
                     22: #define        CMEC    0xff00          /* Corrected memory error count (mask) */
                     23: 
                     24: /* shifts to get the values of MCR fields. */
                     25:  
                     26: #define        EECSHFT         0x01            /* Enable error correction */
                     27: #define        WMDSHFT         0x02            /* Write memory diagnostic */
                     28: #define        RMDSHFT         0x03            /* Read memory diagnostic */
                     29: #define        INTSHFT         0x05            /* Init = power on bit */
                     30: #define        CECSHFT         0x06            /* Clear error count */
                     31: #define        CMESHFT         0x07            /* Clear memory error */
                     32: #define        CMECSHFT        0x08            /* Corrected memory error count (mask) */
                     33: /*
                     34:  * MER bits
                     35:  */
                     36: 
                     37: #define        ERRCD   0x07            /* Error code (mask) */
                     38: #define    APE 1       /* Address parity error */
                     39: #define    DPE 2       /* Data parity error */
                     40: #define    DCE 3       /* Data check error */
                     41: #define    VTO 4       /* Versabus timeout */
                     42: #define    VBE 5       /* Versabus error */
                     43: #define    NEM 6       /* Non-existent memory */
                     44: 
                     45: #define        AXE     0x08            /* Adapter external error */
                     46: #define        ERM     0x10            /* Error master (0=CPU, 1=Versabus) */
                     47: #define        IVV     0x100           /* Illegal Versabus vector */
                     48: 
                     49: /*
                     50:  * MCBR bits
                     51:  */
                     52: 
                     53: #define        MCBR    0xffff0000
                     54: #define        MEAR    0xffff0000
                     55: 

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