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1.1 root 1: /*
2: * Copyright (c) 1988 The Regents of the University of California.
3: * All rights reserved.
4: *
5: * This code is derived from software contributed to Berkeley by
6: * Computer Consoles Inc.
7: *
8: * Redistribution is only permitted until one year after the first shipment
9: * of 4.4BSD by the Regents. Otherwise, redistribution and use in source and
10: * binary forms are permitted provided that: (1) source distributions retain
11: * this entire copyright notice and comment, and (2) distributions including
12: * binaries display the following acknowledgement: This product includes
13: * software developed by the University of California, Berkeley and its
14: * contributors'' in the documentation or other materials provided with the
15: * distribution and in all advertising materials mentioning features or use
16: * of this software. Neither the name of the University nor the names of
17: * its contributors may be used to endorse or promote products derived from
18: * this software without specific prior written permission.
19: * THIS SOFTWARE IS PROVIDED AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
20: * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
21: * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22: *
23: * @(#)drreg.h 7.3 (Berkeley) 6/28/90
24: */
25:
26: /*
27: ------------------------------------------
28: Must include <h/types.h> and <h/buf.h>
29: ------------------------------------------
30: */
31:
32: #define DRINTV 0x9c /* Has to match with ml/scb.s */
33: #define DRADDMOD 0x01 /* Addr modifier used to access TAHOE memory */
34: #define DR_ZERO 0
35: #define DRPRI (PZERO+1)
36:
37: #define DR_TICK 600 /* Default # of clock ticks between call
38: to local timer watchdog routine */
39: #define DR_TOCK 2 /* default # of calls to local watch dog
40: before an IO or wait is determined to
41: have timeout */
42:
43:
44: struct rsdevice {
45: ushort dr_cstat; /* Control & status registers */
46: ushort dr_data; /* Input/Ouptut data registers */
47: char dr_addmod; /* Address modifier for DMA */
48: char dr_intvect; /* Interrupt vector */
49: ushort dr_pulse; /* Pulse command register */
50: ushort dr_xx08; /* Not used */
51: ushort dr_xx0A; /* Not used */
52: ushort dr_xx0C; /* Not used */
53: ushort dr_xx0E; /* Not used */
54: ushort dr_xx10; /* Not used */
55: ushort dr_walo; /* Low DMA address register --when written-- */
56: ushort dr_range; /* DMA range counter */
57: ushort dr_ralo; /* Low DMA address register --when read-- */
58: ushort dr_xx18; /* Not used */
59: ushort dr_wahi; /* High DMA address register --when written-- */
60: ushort dr_xx1C; /* Not used */
61: ushort dr_rahi; /* High DMA address register --when read-- */
62: };
63:
64:
65: struct dr_aux {
66: struct rsdevice *dr_addr; /* Physical addr of currently active DR11 */
67: struct buf *dr_actf; /* Pointers to DR11's active buffers list */
68: unsigned int dr_flags; /* State: Hold open, active,... */
69: ushort dr_cmd; /* Hold cmd placed here by ioctl
70: for later execution by rsstrategy() */
71: ushort dr_op; /* Current operation: DR_READ/DR_WRITE */
72: long dr_bycnt; /* Total byte cnt of current operation */
73: /* decremented by completion interrupt */
74: caddr_t dr_oba; /* original xfer addr, count */
75: long dr_obc;
76: unsigned long
77: rtimoticks, /* No of ticks before timing out on no stall
78: read */
79: wtimoticks, /* No of ticks before timing out on no stall
80: write */
81: currenttimo; /* the number of current timeout call to
82: omrwtimo() */
83: ushort dr_istat; /* Latest interrupt status */
84: struct buf dr_buf;
85:
86: /*ushort dr_time; /* # of ticks until timeout */
87: /*ushort dr_tock; /* # of ticks accumulated */
88: /*ushort dr_cseq; /* Current sequence number */
89: /*ushort dr_lseq; /* Last sequence number */
90: };
91:
92: /* Command used by drioctl()
93: */
94: struct dr11io {
95: ushort arg[8];
96: };
97:
98: #define RSADDR(unit) ((struct rsdevice *)drinfo[unit]->ui_addr)
99:
100: /* Control register bits */
101: #define RDMA 0x8000 /* reset DMA end-of-range flag */
102: #define RATN 0x4000 /* reset attention flag */
103: #define RPER 0x2000 /* reset device parity error flag */
104: #define MCLR 0x1000 /* master clear board and INT device */
105: #define CYCL 0x0100 /* forces DMA cycle if DMA enabled */
106: #define IENB 0x0040 /* enables interrupt */
107: #define FCN3 0x0008 /* func. bit 3 to device (FNCT3 H) */
108: #define FCN2 0x0004 /* func. bit 2 to device (FNCT2 H) */
109: /* also asserts ACLO FCNT2 H to device */
110: #define FCN1 0x0002 /* func. bit 1 to device (FNCT1 H) */
111: #define GO 0x0001 /* enable DMA and pulse GO to device */
112:
113: /* Status register bits */
114: #define DMAF 0x8000 /* indicates DMA end-of-range */
115: #define ATTF 0x4000 /* indicates attention false-to-true */
116: #define ATTN 0x2000 /* current state of ATTENTION H input */
117: #define PERR 0x1000 /* Set by external parity error */
118: #define STTA 0x0800 /* STATUS A H input state */
119: #define STTB 0x0400 /* STATUS B H input state */
120: #define STTC 0x0200 /* STATUS C H input state */
121: #define REDY 0x0080 /* board ready for cmd (dma not on) */
122: #define IENF 0x0040 /* Interrupt enabled if on */
123: #define BERR 0x0020 /* Set if bus error during DMA */
124: #define TERR 0x0010 /* Set if bus timeout during DMA */
125: #define FC3S 0x0008 /* State of FCN3 latch */
126: #define FC2S 0x0004 /* State of FCN2 latch */
127: #define FC1S 0x0002 /* State of FCN1 latch */
128: #define DLFG 0x0001 /* 0 -> IKON-10083 *** 1 -> IKON-10077 */
129:
130: /* Pulse command register bits */
131: #define SMSK 0x0040 /* pulse interrupt mask on: Set IENB */
132: #define RMSK 0x0020 /* pulse interrupt mask off: Reset IENB */
133:
134:
135: /*
136: * DR11 driver's internal flags -- to be stored in dr_flags
137: */
138: #define DR_FMSK 0x0000E /* function bits mask */
139: #define DR_OPEN 0x00001 /* This dr11 has been opened */
140: #define DR_PRES 0x00002 /* This dr11 is present */
141: #define DR_ACTV 0x00004 /* waiting for end-of-range */
142: #define DR_ATWT 0x00008 /* waiting for attention interrupt */
143: #define DR_ATRX 0x00010 /* attn received-resets when read */
144: #define DR_TMDM 0x00020 /* timeout waiting for end-of-range */
145: #define DR_TMAT 0x00040 /* timeout waiting for attention */
146: #define DR_DMAX 0x00080 /* end-of-range interrupt received */
147: #define DR_PCYL 0x00100 /* set cycle with next go */
148: #define DR_DFCN 0x00200 /* donot update function bits until next go */
149: #define DR_DACL 0x00400 /* defer alco pulse until go */
150: #define DR_LOOPTST 0x02000 /* This dr11 is in loopback test mode */
151: #define DR_LNKMODE 0x04000 /* This dr11 is in link mode */
152: #define DR_NORSTALL 0x10000 /* Device is set to no stall mode for reads. */
153: #define DR_NOWSTALL 0x20000 /* Device is set to no stall mode for writes. */
154: #define DR_TIMEDOUT 0x40000 /* The device timed out on a stall mode R/W */
155:
156: /*
157: * DR11 driver's internal flags -- to be stored in dr_op
158: */
159: #define DR_READ FCN1
160: #define DR_WRITE 0
161:
162: /*
163: * Ioctl commands
164: */
165: #define DRWAIT _IOWR('d',1,long)
166: #define DRPIOW _IOWR('d',2,long)
167: #define DRPACL _IOWR('d',3,long)
168: #define DRDACL _IOWR('d',4,long)
169: #define DRPCYL _IOWR('d',5,long)
170: #define DRDFCN _IOWR('d',6,long)
171: #define DRRPER _IOWR('d',7,long)
172: #define DRRATN _IOWR('d',8,long)
173: #define DRRDMA _IOWR('d',9,long)
174: #define DRSFCN _IOWR('d',10,long)
175:
176: #define DRSETRSTALL _IOWR('d',13,long)
177: #define DRSETNORSTALL _IOWR('d',14,long)
178: #define DRGETRSTALL _IOWR('d',15,long)
179: #define DRSETRTIMEOUT _IOWR('d',16,long)
180: #define DRGETRTIMEOUT _IOWR('d',17,long)
181: #define DRSETWSTALL _IOWR('d',18,long)
182: #define DRSETNOWSTALL _IOWR('d',19,long)
183: #define DRGETWSTALL _IOWR('d',20,long)
184: #define DRSETWTIMEOUT _IOWR('d',21,long)
185: #define DRGETWTIMEOUT _IOWR('d',22,long)
186: #define DRWRITEREADY _IOWR('d',23,long)
187: #define DRREADREADY _IOWR('d',24,long)
188: #define DRBUSY _IOWR('d',25,long)
189: #define DRRESET _IOWR('d',26,long)
190:
191: /* The block size for buffering and DMA transfers. */
192: /* OM_BLOCKSIZE must be even and <= 32768. Multiples of 512 are prefered. */
193: #define OM_BLOCKSIZE 32768
194:
195:
196: /* --- Define ioctl call used by dr11 utility device -- */
197:
198: #define DR11STAT _IOWR('d',30,struct dr11io) /* Get status dr11, unit
199: number is dr11io.arg[0] */
200: #define DR11LOOP _IOR('d',31,struct dr11io) /* Perform loopback test */
201:
202: /* ---------------------------------------------------- */
203:
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