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1.1 root 1: /*
2: * Copyright (c) 1988 The Regents of the University of California.
3: * All rights reserved.
4: *
5: * This code is derived from software contributed to Berkeley by
6: * Harris Corp.
7: *
8: * Redistribution is only permitted until one year after the first shipment
9: * of 4.4BSD by the Regents. Otherwise, redistribution and use in source and
10: * binary forms are permitted provided that: (1) source distributions retain
11: * this entire copyright notice and comment, and (2) distributions including
12: * binaries display the following acknowledgement: This product includes
13: * software developed by the University of California, Berkeley and its
14: * contributors'' in the documentation or other materials provided with the
15: * distribution and in all advertising materials mentioning features or use
16: * of this software. Neither the name of the University nor the names of
17: * its contributors may be used to endorse or promote products derived from
18: * this software without specific prior written permission.
19: * THIS SOFTWARE IS PROVIDED AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
20: * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
21: * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22: *
23: * @(#)hdreg.h 7.4 (Berkeley) 6/28/90
24: */
25:
26: #ifndef COMPAT_42
27: #define COMPAT_42
28: #endif
29:
30: #define HDC_READ 0
31: #define HDC_WRITE 1
32:
33: #define HDC_MAXBUS 2 /* max# buses */
34: #define HDC_MAXCTLR 21 /* max# hdc controllers per bus */
35: #define HDC_MAXDRIVE 4 /* max# drives per hdc controller */
36: #define HDC_MAXMCBS 32 /* max# mcb's the hdc can handle */
37: #define HDC_MAXCHAIN 64 /* max# of data chains */
38: #define HDC_MAXBC 64*1024 /* max# byte count per data chain */
39: #define HDC_MAXFLAWS 8000 /* max# flaws per hdc disk */
40:
41: #define HDC_SPB 2 /* sectors per block for hdc's */
42: #define HDC_VDATA_SIZE 16 /* vendor data size (long words) */
43:
44: #define HDC_REG(x) (hd->reg->x) /* set an HDC register */
45: /* number of blocks per dump record */
46: #define HDC_DUMPSIZE (HDC_MAXBC/DEV_BSIZE*HDC_MAXCHAIN)
47:
48: /*
49: * These are the 4 hdc i/o register addresses. Writing to "master_mcb"
50: * tells the hdc controller where the master mcb is and initiates hdc
51: * operation. The hdc then reads the master mcb and all new mcb's in the
52: * active mcb queue. Writing to "module_id" causes the hdc to return the
53: * hdc's module id word in the location specified by the address written
54: * into the register. "soft_reset" causes orderly shutdown of HDC; it's
55: * unclear from the manual what "hard_reset" does, but it should never be
56: * used as use while the HDC is active may cause format errors.
57: */
58: struct registers {
59: u_long master_mcb, /* set the master mcb address */
60: module_id, /* returns hdc's module id (hdc_mid) */
61: soft_reset, /* shut down the hdc */
62: hard_reset; /* send a system reset to the hdc */
63: };
64:
65: /*
66: * Definition for the module id returned by the hdc when "module_id"
67: * is written to. The format is defined by the hdc microcode.
68: */
69: #define HID_HDC 0x01 /* hvme_id for HDC */
70: #define HDC_MID HID_HDC /* module id code for hdc's */
71: struct module_id {
72: u_char module_id, /* module id; hdc's return HDC_MID */
73: reserved,
74: code_rev, /* micro-code rev#; FF= not loaded */
75: fit; /* FIT test result; FF= no error */
76: };
77:
78: /*
79: * This structure defines the mcb's. A portion of this structure is used
80: * only by the software. The other portion is set up by software and sent
81: * to the hdc firmware to perform an operation; the order of this part of
82: * the mcb is determined by the controller firmware.
83: *
84: * "context" is the software context word. The hdc firmware copies the
85: * contents of this word to the master mcb whenever the mcb has been
86: * completed. The virtual address of the mcb is usually saved here.
87: *
88: * "forw_phaddr" forms a linked list of mcbs. The addresses are physical
89: * since they are used by the hdc firmware.
90: *
91: * Bits in device control word #1 define the hdc command and control the
92: * operation of the hdc. Bits in device control word #2 define the disk
93: * sector address for the operation defined in control word #1.
94: */
95: #define LWC_DATA_CHAIN 0x80000000 /* mask for data chain bit in wcount */
96: struct mcb {
97: u_long forw_phaddr; /* phys address of next mcb */
98: u_int priority : 8, /* device control word #1 */
99: interrupt : 1, /* " */
100: drive : 7, /* " */
101: command : 16, /* " (see HCMD_) */
102: cyl : 13, /* device control word #2 */
103: head : 9, /* " */
104: sector : 10; /* " */
105: u_long r1, r2,
106: context; /* software context word */
107: struct chain {
108: long wcount, /* word count */
109: memadr; /* transfer address */
110: } chain[HDC_MAXCHAIN]; /* data chain */
111: };
112: /* defines for the "command"s */
113: #define HCMD_STATUS 0x40 /* command: read drive status */
114: #define HCMD_READ 0x60 /* command: read data */
115: #define HCMD_VENDOR 0x6a /* command: read vendor data */
116: #define HCMD_VERIFY 0x6d /* command: verify a track */
117: #define HCMD_WRITE 0x70 /* command: write data */
118: #define HCMD_FORMAT 0x7e /* command: format a track */
119: #define HCMD_CERTIFY 0x7f /* command: certify a track */
120: #define HCMD_WCS 0xd0 /* command: write control store */
121:
122: /*
123: * This structure defines the master mcb - one per hdc controller.
124: * The order of this structure is determined by the controller firmware.
125: * "R" and "W" indicate read-only and write-only.
126: *
127: * Bits in the module control long word, "mcl", control the invocation of
128: * operations on the hdc.
129: *
130: * The hdc operates in queued mode or immediate mode. In queued mode, it
131: * grabs new mcb's, prioritizes them, and adds them to its queue; it knows
132: * if we've added any mcb's by checking forw_phaddr to see if any are
133: * linked off of there.
134: *
135: * Bits in the master mcb's status word, "mcs", indicate the status
136: * of the last-processed mcb. The MCS_ definitions define these bits.
137: * This word is set to zero when the mcb queue is passed to the hdc
138: * controller; the hdc controller then sets bits in this word.
139: * We cannot modify the mcb queue until the hdc has completed an mcb
140: * (the hdc sets the MCS_Q_DONE bit).
141: *
142: * The "context" word is copied from the context word of the completed
143: * mcb. It is currently the virtual pointer to the completed mcb.
144: */
145: /* definition of master mcb "mcl" */
146: #define MCL_QUEUED 0x00000010 /* start queued execution of mcb's */
147: #define MCL_IMMEDIATE 0x00000001 /* start immediate xqt of an mcb */
148: /* definition of master mcb "mcs" */
149: #define MCS_DONE 0x00000080 /* an mcb is done; status is valid */
150: #define MCS_FATALERROR 0x00000002 /* a fatal error occurred */
151: #define MCS_SOFTERROR 0x00000001 /* a recoverable error occurred */
152:
153: struct master_mcb {
154: u_long mcw, /* W module control word (MCL_) */
155: interrupt, /* W interrupt acknowledge word */
156: forw_phaddr, /* W physical address of first mcb */
157: r1, r2,
158: mcs, /* R status for last completed mcb */
159: cmcb_phaddr, /* W physical addr of completed mcb */
160: context, /* W software context word */
161: #define HDC_XSTAT_SIZE 128 /* size of extended status (lwords) */
162: xstatus[HDC_XSTAT_SIZE];/* R xstatus of last mcb */
163: };
164:
165: /*
166: * This structure defines the information returned by the hdc controller for
167: * a "read drive status" (HCMD_STATUS) command. The format of this structure
168: * is determined by the hdc firmware. r[1-11] are reserved for future use.
169: */
170: /* defines for drive_stat drs word */
171: #define DRS_FAULT 0x00000080 /* drive is reporting a fault */
172: #define DRS_RESERVED 0x00000040 /* drive is reserved by other port */
173: #define DRS_WRITE_PROT 0x00000020 /* drive is write protected */
174: #define DRS_ON_CYLINDER 0x00000002 /* drive heads are not moving now */
175: #define DRS_ONLINE 0x00000001 /* drive is available for operation */
176:
177: struct status {
178: u_long drs, /* drive status (see DRS_) */
179: r1, r2, r3;
180: u_short max_cyl, /* max logical cylinder address */
181: max_head, /* max logical head address */
182: r4,
183: max_sector, /* max logical sector address */
184: def_cyl, /* definition track cylinder address */
185: def_cyl_count, /* definition track cylinder count */
186: diag_cyl, /* diagnostic track cylinder address */
187: diag_cyl_count, /* diagnostic track cylinder count */
188: max_phys_cyl, /* max physical cylinder address */
189: max_phys_head, /* max physical head address */
190: r5,
191: max_phys_sector, /* max physical sector address */
192: r6,
193: id, /* drive id (drive model) */
194: r7,
195: bytes_per_sec, /* bytes/sector -vendorflaw conversn */
196: r8,
197: rpm; /* disk revolutions per minute */
198: u_long r9, r10, r11;
199: };
200:
201: #ifdef COMPAT_42
202: #define GB_ID "geometry"
203: #define GB_ID_LEN sizeof(GB_ID)-1
204: #define GB_MAXPART 8
205: #define GB_VERSION 1
206:
207: #define HDC_DEFPART GB_MAXPART-1 /* partition# of def and diag cyls */
208: #define BPS 512 /* bytes per sector */
209:
210: /*
211: * Geometry Block:
212: *
213: * The geometry block defines partition offsets and information about the
214: * flaw maps on the flaw map track. It resides on the first sector of the
215: * flaw map track. This structure is also used by vddc disk controllers.
216: * In this case, the block resides at sector 0 of the disk.
217: *
218: * The geometry_sector structure defines the sector containing the geometry
219: * block. This sector is checksumed independent of the geometry information.
220: * The fields in these structured which should never be moved are the id and
221: * version fields in the geometry_block structure and the checksum field in
222: * the geometry_sector structure. This will provide for easy extensions in
223: * the future.
224: */
225:
226: #define DRIVE_TYPE flaw_offset /* For VDDC Geometry Blocks Only */
227:
228: typedef struct {
229: char id[GB_ID_LEN]; /* identifies the geometry block */
230: long version, /* geometry block version number */
231: flaw_offset, /* flaw map byte offset in partition7 */
232: flaw_size, /* harris flaw map size in bytes */
233: flaw_checksum, /* sum of bytes in harris flaw map */
234: unused[3]; /* --- available for use */
235: struct par_tab {
236: long start, /* starting 1K block number */
237: length; /* partition size in 1K blocks */
238: } partition[GB_MAXPART]; /* partition definitions */
239: } geometry_block;
240:
241: typedef struct {
242: geometry_block geometry_block; /* disk geometry */
243: char filler[BPS - sizeof(geometry_block) - sizeof(long)];
244: long checksum; /* sector checksum */
245: } geometry_sector;
246:
247: /*
248: * GB_CHECKSUM:
249: *
250: * This macro computes the checksum for the geometry sector and returns the
251: * value. Input to this macro is a pointer to the geometry_sector. Pretty
252: * useless, should at least have done an XOR.
253: */
254: #define GB_CHECKSUM(_gs_ptr, _checksum) { \
255: register u_char *_ptr; \
256: register u_long _i, _xsum; \
257: _xsum = 0; \
258: _ptr = (u_char *)(_gs_ptr); \
259: for (_i = 0; _i < (sizeof(geometry_sector) - sizeof(long)); _i++) \
260: _xsum += * _ptr++; \
261: _checksum = _xsum; \
262: }
263: #endif /* COMPAT_42 */
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