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Annotation of 43BSDReno/sys/tahoevba/ikreg.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * Copyright (c) 1986 The Regents of the University of California.
        !             3:  * All rights reserved.
        !             4:  *
        !             5:  * Redistribution is only permitted until one year after the first shipment
        !             6:  * of 4.4BSD by the Regents.  Otherwise, redistribution and use in source and
        !             7:  * binary forms are permitted provided that: (1) source distributions retain
        !             8:  * this entire copyright notice and comment, and (2) distributions including
        !             9:  * binaries display the following acknowledgement:  This product includes
        !            10:  * software developed by the University of California, Berkeley and its
        !            11:  * contributors'' in the documentation or other materials provided with the
        !            12:  * distribution and in all advertising materials mentioning features or use
        !            13:  * of this software.  Neither the name of the University nor the names of
        !            14:  * its contributors may be used to endorse or promote products derived from
        !            15:  * this software without specific prior written permission.
        !            16:  * THIS SOFTWARE IS PROVIDED AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
        !            17:  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
        !            18:  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
        !            19:  *
        !            20:  *     @(#)ikreg.h     7.3 (Berkeley) 6/28/90
        !            21:  */
        !            22: 
        !            23: /*
        !            24:  * IKON DR-11W register definitions.
        !            25:  */
        !            26: struct ikdevice {
        !            27:        u_short ik_csr;         /* control status register */
        !            28:        u_short ik_data;        /* data in/out register */
        !            29:        u_char  ik_mod;         /* address modifier */
        !            30:        u_char  ik_vec;         /* interrupt vector */
        !            31:        u_short ik_pulse;       /* pulse commands (w) */
        !            32:        u_short ik_fill[5];
        !            33:        u_short ik_balo;        /* low word of dma beginning address (w) */
        !            34:        u_short ik_wc;          /* dma word count */
        !            35:        u_short ik_calo;        /* low word of dma current address (r) */
        !            36:        u_short ik_fill1;
        !            37:        u_short ik_bahi;        /* high word of dma beginning address (w) */
        !            38:        u_short ik_fill2;
        !            39:        u_short ik_cahi;        /* high word of dma current address (r) */
        !            40: };
        !            41: 
        !            42: /*
        !            43:  * CSR control definitions (write-only).
        !            44:  */
        !            45: #define IKCSR_GO       0x0001          /* start dma */
        !            46: #define IKCSR_FNC1     0x0002          /* function bit 1 */
        !            47: #define IKCSR_FNC2     0x0004          /* function bit 2 */
        !            48: #define IKCSR_FNC3     0x0008          /* function bit 3 */
        !            49: /* bits 4-5 are unused */
        !            50: #define IKCSR_IENA     0x0040          /* enable/disable interrupts */
        !            51: /* bit 7 is unused */
        !            52: #define IKCSR_CYCLE    0x0100          /* force dma to cycle */
        !            53: /* bits 9-11 are unused */
        !            54: #define IKCSR_MCLR     0x1000          /* master clear board */
        !            55: #define IKCSR_RPERR    0x2000          /* reset parity error */
        !            56: #define IKCSR_RATTF    0x4000          /* reset attention */
        !            57: #define IKCSR_RDMAF    0x8000          /* reset dma completion */
        !            58: 
        !            59: /*
        !            60:  * CSR status definitions (read-only).
        !            61:  */
        !            62: #define IKCSR_DEV      0x0001          /* device flag (0 = 10083, 1 = 10077) */
        !            63: /* bits 1-3 reflect the function latch state */
        !            64: #define IKCSR_TIMO     0x0010          /* bus timeout during dma */
        !            65: #define IKCSR_BERR     0x0020          /* bus error during dma */
        !            66: /* bit 6 reflects interrupt enable state */
        !            67: #define IKCSR_READY    0x0080          /* device ready for next command */
        !            68: /* bit 8 should be 0 */
        !            69: #define IKCSR_STATC    0x0200          /* status bit C */
        !            70: #define IKCSR_STATB    0x0400          /* status bit B */
        !            71: #define IKCSR_STATA    0x0800          /* status bit A */
        !            72: #define IKCSR_PERR     0x1000          /* parity error during pi/o or dma */
        !            73: #define IKCSR_ATTN     0x2000          /* current state of attention bit */
        !            74: #define IKCSR_ATTF     0x4000          /* latched attention t-f transition */
        !            75: #define IKCSR_DMAF     0x8000          /* dma completed or terminated */
        !            76: 
        !            77: #define IKCSR_BITS \
        !            78: "\020\1DEV\2FNC1\3FNC2\4FNC3\5TIMO\6BERR\7IENA\10READY\12STATC\13STATB\14STATA\
        !            79: \15PERR\16ATTN\17ATTF\20DMAF"
        !            80: 
        !            81: /*
        !            82:  * Pulse command register definitions (write-only).
        !            83:  */
        !            84: #define IKPULSE_GO     0x0001          /* enable dma */
        !            85: #define IKPULSE_FNC2   0x0004          /* pulse function bit 1 */
        !            86: #define IKPULSE_RIENA  0x0020          /* reset IKCSR_IENA */
        !            87: #define IKPULSE_SIENA  0x0040          /* set IKCSR_IENA */
        !            88: #define IKPULSE_CYCL   0x0100          /* force dma to cycle */
        !            89: #define IKPULSE_MCLR   0x1000          /* initialize interface */
        !            90: #define IKPULSE_RPERR  0x2000          /* reset IKCSR_PERR */
        !            91: #define IKPULSE_RATTF  0x4000          /* reset IKCSR_ATTF */
        !            92: #define IKPULSE_RDMAF  0x8000          /* reset IKCSR_DMAF */

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