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Annotation of 43BSDReno/sys/vax/ka650.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * Copyright (c) 1988 The Regents of the University of California.
        !             3:  * All rights reserved.
        !             4:  *
        !             5:  * This code is derived from software contributed to Berkeley by
        !             6:  * Mt. Xinu.
        !             7:  *
        !             8:  * Redistribution is only permitted until one year after the first shipment
        !             9:  * of 4.4BSD by the Regents.  Otherwise, redistribution and use in source and
        !            10:  * binary forms are permitted provided that: (1) source distributions retain
        !            11:  * this entire copyright notice and comment, and (2) distributions including
        !            12:  * binaries display the following acknowledgement:  This product includes
        !            13:  * software developed by the University of California, Berkeley and its
        !            14:  * contributors'' in the documentation or other materials provided with the
        !            15:  * distribution and in all advertising materials mentioning features or use
        !            16:  * of this software.  Neither the name of the University nor the names of
        !            17:  * its contributors may be used to endorse or promote products derived from
        !            18:  * this software without specific prior written permission.
        !            19:  * THIS SOFTWARE IS PROVIDED AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
        !            20:  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
        !            21:  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
        !            22:  *
        !            23:  *     @(#)ka650.h     7.5 (Berkeley) 6/28/90
        !            24:  */
        !            25: 
        !            26: /*
        !            27:  *
        !            28:  * Definitions specific to the ka650 (uVAX 3600/3602) cpu card.
        !            29:  */
        !            30: 
        !            31: #ifdef VAX650
        !            32: /*
        !            33:  * CAER: Memory System Error Register (IPR 39)
        !            34:  */
        !            35: #define CAER_DAL       0x00000040      /* CDAL or level 2 cache data parity */
        !            36: #define CAER_MCD       0x00000020      /* mcheck due to DAL parity error */
        !            37: #define CAER_MCC       0x00000010      /* mcheck due to 1st lev cache parity */
        !            38: #define CAER_DAT       0x00000002      /* data parity in 1st level cache */
        !            39: #define CAER_TAG       0x00000001      /* tag parity in 1st level cache */
        !            40: 
        !            41: /*
        !            42:  * CADR: Cache Disable Register (IPR 37)
        !            43:  */
        !            44: #define CADR_STMASK    0x000000f0      /* 1st level cache state mask */
        !            45: #define CADR_SEN2      0x00000080      /* 1st level cache set 2 enabled */
        !            46: #define CADR_SEN1      0x00000040      /* 1st level cache set 1 enabled */
        !            47: #define CADR_CENI      0x00000020      /* 1st level I-stream caching enabled */
        !            48: #define CADR_CEND      0x00000010      /* 1st level D-stream caching enabled */
        !            49: 
        !            50: /*
        !            51:  * Internal State Info 2: (for mcheck recovery)
        !            52:  */
        !            53: #define IS2_VCR                0x00008000      /* VAX Can't Restart flag */
        !            54: 
        !            55: /*
        !            56:  * DMA System Error Register (merr_dser)
        !            57:  */
        !            58: #define DSER_QNXM      0x00000080      /* Q-22 Bus NXM */
        !            59: #define DSER_QPE       0x00000020      /* Q-22 Bus parity Error */
        !            60: #define DSER_MEM       0x00000010      /* Main mem err due to ext dev DMA */
        !            61: #define DSER_LOST      0x00000008      /* Lost error: DSER <7,5,4,0> set */
        !            62: #define DSER_NOGRANT   0x00000004      /* No Grant timeout on cpu demand R/W */
        !            63: #define DSER_DNXM      0x00000001      /* DMA NXM */
        !            64: #define DSER_CLEAR     (DSER_QNXM | DSER_QPE | DSER_MEM |  \
        !            65:                         DSER_LOST | DSER_NOGRANT | DSER_DNXM)
        !            66: #define DMASER_BITS \
        !            67: "\20\20BHALT\17DCNEG\10QBNXM\6QBPE\5MEMERR\4LOSTERR\3NOGRANT\1DMANXM"
        !            68: 
        !            69: #ifndef LOCORE
        !            70: /*
        !            71:  * Local registers (in I/O space)
        !            72:  * This is done in disjoint sections.  Map names are set in locore.s
        !            73:  * and they are mapped in routine configcpu()
        !            74:  */
        !            75: 
        !            76: /*
        !            77:  * memory error & configuration registers
        !            78:  */
        !            79: struct ka650_merr {
        !            80:        u_long  merr_scr;       /* System Config Register */
        !            81:        u_long  merr_dser;      /* DMA System Error Register */
        !            82:        u_long  merr_qbear;     /* QBus Error Address Register */
        !            83:        u_long  merr_dear;      /* DMA Error Address Register */
        !            84:        u_long  merr_qbmbr;     /* Q Bus Map Base address Register */
        !            85:        u_long  pad[59];
        !            86:        u_long  merr_csr[16];   /* Main Memory Config Regs (16 banks) */
        !            87:        u_long  merr_errstat;   /* Main Memory Error Status */
        !            88:        u_long  merr_cont;      /* Main Memory Control */
        !            89: };
        !            90: #define KA650_MERR     0x20080000
        !            91: 
        !            92: /*
        !            93:  * Main Memory Error Status Register (merr_errstat)
        !            94:  */
        !            95: #define MEM_EMASK      0xe0000180      /* mask of all err bits */
        !            96: #define MEM_RDS                0x80000000      /* uncorrectable main memory */
        !            97: #define MEM_RDSHIGH    0x40000000      /* high rate RDS errors */
        !            98: #define MEM_CRD                0x20000000      /* correctable main memory */
        !            99: #define MEM_DMA                0x00000100      /* DMA read or write error */
        !           100: #define MEM_CDAL       0x00000080      /* CDAL Parity error on write */
        !           101: #define MEM_PAGE       0x1ffffe00      /* Offending Page Number */
        !           102: #define MEM_PAGESHFT   9               /* Shift to normalize page number */
        !           103: 
        !           104: /*
        !           105:  * Main Memory Control & Diag Status Reg (merr_cont)
        !           106:  */
        !           107: #define MEM_CRDINT     0x00001000      /* CRD interrupts enabled */
        !           108: #define MEM_REFRESH    0x00000800      /* Forced memory refresh */
        !           109: #define MEM_ERRDIS     0x00000400      /* error detect disable */
        !           110: #define MEM_DIAG       0x00000080      /* Diagnostics mode */
        !           111: #define MEM_CHECK      0x0000007f      /* check bits for diagnostic mode */
        !           112: 
        !           113: /*
        !           114:  * Main Memory Config Regs (merr_csr[0-15])
        !           115:  */
        !           116: #define MEM_BNKENBLE   0x80000000      /* Bank Enable */
        !           117: #define MEM_BNKNUM     0x03c00000      /* Physical map Bank number */
        !           118: #define MEM_BNKUSAGE   0x00000003      /* Bank Usage */
        !           119: 
        !           120: /*
        !           121:  * Cache Control & Boot/Diag registers
        !           122:  */
        !           123: struct ka650_cbd {
        !           124:        u_char  cbd_cacr;       /* Low byte: Cache Enable & Parity Err detect */
        !           125:        u_char  cbd_cdf1;       /* Cache diagnostic field (unused) */
        !           126:        u_char  cbd_cdf2;       /* Cache diagnostic field (unused) */
        !           127:        u_char  pad;
        !           128:        u_long  cbd_bdr;        /* Boot & Diagnostic Register (unused) */
        !           129: };
        !           130: #define KA650_CBD      0x20084000
        !           131: 
        !           132: /*
        !           133:  * CACR: Cache Control Register (2nd level cache) (cbd_cacr)
        !           134:  */
        !           135: #define CACR_CEN       0x00000010      /* Cache enable */
        !           136: #define CACR_CPE       0x00000020      /* Cache Parity Error */
        !           137: 
        !           138: /*
        !           139:  * System Support Chip (SSC) registers
        !           140:  */
        !           141: struct ka650_ssc {
        !           142:        u_long  ssc_sscbr;      /* SSC Base Addr Register */
        !           143:        u_long  pad1[3];
        !           144:        u_long  ssc_ssccr;      /* SSC Configuration Register */
        !           145:        u_long  pad2[3];
        !           146:        u_long  ssc_cbtcr;      /* CDAL Bus Timeout Control Register */
        !           147:        u_long  pad3[55];
        !           148:        u_long  ssc_tcr0;       /* timer control reg 0 */
        !           149:        u_long  ssc_tir0;       /* timer interval reg 0 */
        !           150:        u_long  ssc_tnir0;      /* timer next interval reg 0 */
        !           151:        u_long  ssc_tivr0;      /* timer interrupt vector reg 0 */
        !           152:        u_long  ssc_tcr1;       /* timer control reg 1 */
        !           153:        u_long  ssc_tir1;       /* timer interval reg 1 */
        !           154:        u_long  ssc_tnir1;      /* timer next interval reg 1 */
        !           155:        u_long  ssc_tivr1;      /* timer interrupt vector reg 1 */
        !           156:        u_long  pad4[184];
        !           157:        u_char  ssc_cpmbx;      /* Console Program Mail Box: Lang & Hact */
        !           158:        u_char  ssc_terminfo;   /* TTY info: Video Dev, MCS, CRT & ROM flags */
        !           159:        u_char  ssc_keyboard;   /* Keyboard code */
        !           160: };
        !           161: #define KA650_SSC      0x20140000
        !           162: 
        !           163: /*
        !           164:  * CBTCR: CDAL Bus Timeout Control Register (ssc_cbtcr)
        !           165:  */
        !           166: #define CBTCR_BTO      0x80000000      /* r/w unimp IPR or unack intr */
        !           167: #define CBTCR_RWT      0x40000000      /* CDAL Bus Timeout on CPU or DMA */
        !           168: 
        !           169: /*
        !           170:  * TCR0/TCR1: Programable Timer Control Registers (ssc_tcr[01])
        !           171:  * (The rest of the bits are the same as in the standard VAX
        !           172:  *     Interval timer and are defined in clock.h)
        !           173:  */
        !           174: #define TCR_STP                0x00000004      /* Stop after time-out */
        !           175: 
        !           176: /*
        !           177:  * Flags for Console Program Mail Box
        !           178:  */
        !           179: #define CPMB650_HALTACT        0x03    /* Field for halt action */
        !           180: #define CPMB650_RESTART        0x01    /* Restart */
        !           181: #define CPMB650_REBOOT 0x02    /* Reboot */
        !           182: #define CPMB650_HALT   0x03    /* Halt */
        !           183: #define CPMB650_BIP    0x04    /* Bootstrap in progress */
        !           184: #define CPMB650_RIP    0x08    /* Restart in progress */
        !           185: #define CPMB650_LANG   0xf0    /* Language field */
        !           186: 
        !           187: /*
        !           188:  * Inter Processor Communication Register
        !           189:  * To determine if memory error was from QBUS device DMA (as opposed to cpu).
        !           190:  */
        !           191: struct ka650_ipcr {
        !           192:        u_long  pad[80];
        !           193:        u_short ipcr0;          /* InterProcessor Comm Reg for arbiter */
        !           194: };
        !           195: #define KA650_IPCR     0x20001e00
        !           196: 
        !           197: #ifndef STANDALONE
        !           198: /*
        !           199:  * External declarations of the map names (declared in spt.s)
        !           200:  * for the local register space.
        !           201:  */
        !           202: extern struct pte KA650MERRmap[];
        !           203: extern struct ka650_merr ka650merr;    /* mem err & mem config regs */
        !           204: extern struct pte KA650CBDmap[];
        !           205: extern struct ka650_cbd ka650cbd;      /* cache control & boot/diag regs */
        !           206: extern struct pte KA650SSCmap[];
        !           207: extern struct ka650_ssc ka650ssc;      /* SSC regs (& console prog mail box) */
        !           208: extern struct pte KA650IPCRmap[];
        !           209: extern struct ka650_ipcr ka650ipcr;    /* InterProcessor Com Regs */
        !           210: extern struct pte KA650CACHEmap[];
        !           211: extern int     ka650cache[];           /* Cache Diagnostic space (for flush) */
        !           212: #endif STANDALONE
        !           213: #endif LOCORE
        !           214: 
        !           215: /*
        !           216:  * Physical start address of the Qbus memory.
        !           217:  * The q-bus memory size is 4 meg.
        !           218:  * Physical start address of the I/O space (where the 8Kbyte I/O page is).
        !           219:  */
        !           220: #define KA650_QMEM     0x30000000
        !           221: #define KA650_QMEMSIZE (512*8192)
        !           222: #define KA650_QDEVADDR 0x20000000
        !           223: 
        !           224: /*
        !           225:  * Mapping info for Cache Entries, including
        !           226:  * Size (in bytes) of 2nd Level Cache for cache flush operation
        !           227:  */
        !           228: #define KA650_CACHE    0x10000000
        !           229: #define KA650_CACHESIZE        (64*1024)
        !           230: 
        !           231: /*
        !           232:  * Useful ROM addresses
        !           233:  */
        !           234: #define        KA650ROM_SIDEX  0x20060004      /* system ID extension */
        !           235: #define        KA650ROM_GETC   0x20060008      /* (jsb) get character from console */
        !           236: #define        KA650ROM_PUTS   0x2006000c      /* (jsb) put string to console */
        !           237: #define        KA650ROM_GETS   0x20060010      /* (jsb) read string with prompt */
        !           238: #define KA650_CONSTYPE 0x20140401      /* byte at which console type resides */
        !           239: #endif

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