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Annotation of 43BSDReno/sys/vaxif/if_accreg.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * Copyright (c) 1982, 1986 Regents of the University of California.
        !             3:  * All rights reserved.
        !             4:  *
        !             5:  * Redistribution is only permitted until one year after the first shipment
        !             6:  * of 4.4BSD by the Regents.  Otherwise, redistribution and use in source and
        !             7:  * binary forms are permitted provided that: (1) source distributions retain
        !             8:  * this entire copyright notice and comment, and (2) distributions including
        !             9:  * binaries display the following acknowledgement:  This product includes
        !            10:  * software developed by the University of California, Berkeley and its
        !            11:  * contributors'' in the documentation or other materials provided with the
        !            12:  * distribution and in all advertising materials mentioning features or use
        !            13:  * of this software.  Neither the name of the University nor the names of
        !            14:  * its contributors may be used to endorse or promote products derived from
        !            15:  * this software without specific prior written permission.
        !            16:  * THIS SOFTWARE IS PROVIDED AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
        !            17:  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
        !            18:  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
        !            19:  *
        !            20:  *     @(#)if_accreg.h 7.3 (Berkeley) 6/28/90
        !            21:  */
        !            22: 
        !            23: /*
        !            24:  * ACC LH/DH-11 interface
        !            25:  */
        !            26: 
        !            27: struct accdma {
        !            28:        short   csr;    /* control and status */
        !            29:        short   db;     /* data buffer */
        !            30:        u_short ba;     /* buss address */
        !            31:        short   wc;     /* word count */
        !            32: };
        !            33: 
        !            34: struct accdevice {
        !            35:        struct  accdma input;
        !            36:        struct  accdma output;
        !            37: };
        !            38: 
        !            39: #define        icsr    input.csr
        !            40: #define        iba     input.ba
        !            41: #define        iwc     input.wc
        !            42: #define        ocsr    output.csr
        !            43: #define        oba     output.ba
        !            44: #define        owc     output.wc
        !            45: 
        !            46: /*
        !            47:  * Bits Common to both input and out CSR's
        !            48:  */
        !            49: #define        ACC_ERR         0x8000          /* error present */
        !            50: #define        ACC_NXM         0x4000          /* non-existant memory */
        !            51: #define        ACC_RDY         0x0080          /* ready */
        !            52: #define        ACC_IE          0x0040          /* interrupt enable */
        !            53: #define        ACC_RESET       0x0002          /* reset interface */
        !            54: #define        ACC_GO          0x0001          /* start operation */
        !            55: 
        !            56: /*
        !            57:  * Input Control Status Register
        !            58:  */
        !            59: #define IN_EOM         0x2000          /* end-of-message recieved */
        !            60: #define IN_HRDY                0x0800          /* host ready */
        !            61: #define IN_IMPBSY      0x0400          /* IMP not ready */
        !            62: #define IN_RMR         0x0200          /* receive master ready error */
        !            63: #define IN_IBF         0x0100          /* input data buffer full */
        !            64: #define IN_WEN         0x0008          /* write enable */
        !            65: #define IN_MRDY                0x0004          /* master ready */
        !            66: 
        !            67: #define ACC_INBITS \
        !            68: "\20\20ERR\17NXM\16EOM\14HRDY\13IMPBSY\12RMR\11IBF\10RDY\7IE\
        !            69: \4WEN\3MRDY\2RESET\1GO"
        !            70: 
        !            71: /*
        !            72:  * Output Control Status Register
        !            73:  */
        !            74: #define OUT_TMR                0x0200          /* transmit master ready error */
        !            75: #define OUT_BBACK      0x0008          /* bus back */
        !            76: #define OUT_ENLB       0x0004          /* enable last bit */
        !            77: 
        !            78: #define ACC_OUTBITS \
        !            79: "\20\20ERR\17NXM\12TMR\10RDY\7IE\4BBACK\3ENLB\2RESET\1GO"

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