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Annotation of 43BSDReno/sys/vaxif/if_cssreg.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * Copyright (c) 1982, 1986 Regents of the University of California.
        !             3:  * All rights reserved.
        !             4:  *
        !             5:  * Redistribution is only permitted until one year after the first shipment
        !             6:  * of 4.4BSD by the Regents.  Otherwise, redistribution and use in source and
        !             7:  * binary forms are permitted provided that: (1) source distributions retain
        !             8:  * this entire copyright notice and comment, and (2) distributions including
        !             9:  * binaries display the following acknowledgement:  This product includes
        !            10:  * software developed by the University of California, Berkeley and its
        !            11:  * contributors'' in the documentation or other materials provided with the
        !            12:  * distribution and in all advertising materials mentioning features or use
        !            13:  * of this software.  Neither the name of the University nor the names of
        !            14:  * its contributors may be used to endorse or promote products derived from
        !            15:  * this software without specific prior written permission.
        !            16:  * THIS SOFTWARE IS PROVIDED AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
        !            17:  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
        !            18:  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
        !            19:  *
        !            20:  *     @(#)if_cssreg.h 7.3 (Berkeley) 6/28/90
        !            21:  */
        !            22: 
        !            23: /* 
        !            24:  * DEC/CSS IMP11-A ARPAnet interface
        !            25:  */
        !            26: 
        !            27: struct cssdma {
        !            28:        short   wc;             /* word count */
        !            29:        u_short ba;             /* bus address (low 16 bits) */
        !            30:        short   csr;            /* status register */
        !            31:        short   db;             /* data buffer*/
        !            32: };
        !            33: 
        !            34: struct cssdevice {
        !            35:        struct  cssdma  css_output;     /* transmit DR11-B */
        !            36:        struct  cssdma  css_hole;       /* unclever gap */
        !            37:        struct  cssdma  css_input;      /* receive DR11-B */
        !            38: };
        !            39: 
        !            40: #define css_icsr        css_input.csr
        !            41: #define css_iba         css_input.ba
        !            42: #define css_iwc         css_input.wc
        !            43: #define css_ocsr        css_output.csr
        !            44: #define css_oba         css_output.ba
        !            45: #define css_owc         css_output.wc
        !            46: 
        !            47: /*
        !            48:  * Bits Common to both input and out CSR's
        !            49:  */
        !            50: #define CSS_ERR         0x8000          /* error present */
        !            51: #define CSS_NXM         0x4000          /* non-existant memory */
        !            52: #define        CSS_ATTN        0x2000          /* attention */
        !            53: #define        CSS_MAINT       0x1000          /* maintenance mode */
        !            54: #define        CSS_CYCLE       0x0100          /* force bus cycle */
        !            55: #define CSS_RDY         0x0080          /* ready */
        !            56: #define CSS_IE          0x0040          /* interrupt enable */
        !            57: #define        CSS_XA          0x0030          /* extended address bits */
        !            58: #define        CSS_CLR         0x0020          /* clear status (reset) */
        !            59: #define CSS_GO          0x0001          /* start operation */
        !            60: 
        !            61: /*
        !            62:  * Input Control Status Register
        !            63:  */
        !            64: #define IN_EOM          0x0800          /* end-of-message recieved */
        !            65: #define IN_IMPNR       0x0400          /* IMP not ready */
        !            66: #define IN_RLE          0x0200          /* ready line error */
        !            67: #define IN_WEN          0x0008          /* write enable */
        !            68: #define IN_HRDY         0x0004          /* host ready */
        !            69: 
        !            70: #define CSS_INBITS \
        !            71: "\20\20ERR\17NXM\16ATTN\15MAINT\14EOM\13IMPNR\12RLE\11CYCLE\10RDY\7IE\6XBA17\5XBA16\4WE\3HRDY\2CLR\1GO"
        !            72: 
        !            73: 
        !            74: /*
        !            75:  * Output Control Status Register
        !            76:  */
        !            77: #define OUT_TXEC       0x0008          /* tx error clear */
        !            78: #define OUT_ENLB       0x0004          /* enable last bit */
        !            79: 
        !            80: #define CSS_OUTBITS \
        !            81: "\20\20ERR\17NXM\16ATTN\15MAINT\11CYCLE\10RDY\7IE\6XBA17\5XBA16\4TXEC\3ENLB\2CLR\1GO"

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