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1.1 root 1: /*
2: * Copyright (c) 1982, 1986 Regents of the University of California.
3: * All rights reserved.
4: *
5: * Redistribution is only permitted until one year after the first shipment
6: * of 4.4BSD by the Regents. Otherwise, redistribution and use in source and
7: * binary forms are permitted provided that: (1) source distributions retain
8: * this entire copyright notice and comment, and (2) distributions including
9: * binaries display the following acknowledgement: This product includes
10: * software developed by the University of California, Berkeley and its
11: * contributors'' in the documentation or other materials provided with the
12: * distribution and in all advertising materials mentioning features or use
13: * of this software. Neither the name of the University nor the names of
14: * its contributors may be used to endorse or promote products derived from
15: * this software without specific prior written permission.
16: * THIS SOFTWARE IS PROVIDED AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
17: * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
18: * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
19: *
20: * @(#)if_dereg.h 7.3 (Berkeley) 6/28/90
21: */
22:
23: /*
24: * DEC DEUNA interface
25: */
26: struct dedevice {
27: union {
28: short p0_w;
29: char p0_b[2];
30: } u_p0;
31: #define pcsr0 u_p0.p0_w
32: #define pclow u_p0.p0_b[0]
33: #define pchigh u_p0.p0_b[1]
34: short pcsr1;
35: short pcsr2;
36: short pcsr3;
37: };
38:
39: /*
40: * PCSR 0 bit descriptions
41: */
42: #define PCSR0_SERI 0x8000 /* Status error interrupt */
43: #define PCSR0_PCEI 0x4000 /* Port command error interrupt */
44: #define PCSR0_RXI 0x2000 /* Receive done interrupt */
45: #define PCSR0_TXI 0x1000 /* Transmit done interrupt */
46: #define PCSR0_DNI 0x0800 /* Done interrupt */
47: #define PCSR0_RCBI 0x0400 /* Receive buffer unavail intrpt */
48: #define PCSR0_FATI 0x0100 /* Fatal error interrupt */
49: #define PCSR0_INTR 0x0080 /* Interrupt summary */
50: #define PCSR0_INTE 0x0040 /* Interrupt enable */
51: #define PCSR0_RSET 0x0020 /* DEUNA reset */
52: #define PCSR0_CMASK 0x000f /* command mask */
53:
54: #define PCSR0_BITS "\20\20SERI\17PCEI\16RXI\15TXI\14DNI\13RCBI\11FATI\10INTR\7INTE\6RSET"
55:
56: /* bits 0-3 are for the PORT_COMMAND */
57: #define CMD_NOOP 0x0
58: #define CMD_GETPCBB 0x1 /* Get PCB Block */
59: #define CMD_GETCMD 0x2 /* Execute command in PCB */
60: #define CMD_STEST 0x3 /* Self test mode */
61: #define CMD_START 0x4 /* Reset xmit and receive ring ptrs */
62: #define CMD_BOOT 0x5 /* Boot DEUNA */
63: #define CMD_PDMD 0x8 /* Polling demand */
64: #define CMD_TMRO 0x9 /* Sanity timer on */
65: #define CMD_TMRF 0xa /* Sanity timer off */
66: #define CMD_RSTT 0xb /* Reset sanity timer */
67: #define CMD_STOP 0xf /* Suspend operation */
68:
69: /*
70: * PCSR 1 bit descriptions
71: */
72: #define PCSR1_XPWR 0x8000 /* Transceiver power BAD */
73: #define PCSR1_ICAB 0x4000 /* Interconnect cabling BAD */
74: #define PCSR1_STCODE 0x3f00 /* Self test error code */
75: #define PCSR1_PCTO 0x0080 /* Port command timed out */
76: #define PCSR1_ILLINT 0x0040 /* Illegal interrupt */
77: #define PCSR1_TIMEOUT 0x0020 /* Timeout */
78: #define PCSR1_POWER 0x0010 /* Power fail */
79: #define PCSR1_RMTC 0x0008 /* Remote console reserved */
80: #define PCSR1_STMASK 0x0007 /* State */
81:
82: /* bit 0-3 are for STATE */
83: #define STAT_RESET 0x0
84: #define STAT_PRIMLD 0x1 /* Primary load */
85: #define STAT_READY 0x2
86: #define STAT_RUN 0x3
87: #define STAT_UHALT 0x5 /* UNIBUS halted */
88: #define STAT_NIHALT 0x6 /* NI halted */
89: #define STAT_NIUHALT 0x7 /* NI and UNIBUS Halted */
90:
91: #define PCSR1_BITS "\20\20XPWR\17ICAB\10PCTO\7ILLINT\6TIMEOUT\5POWER\4RMTC"
92:
93: /*
94: * Port Control Block Base
95: */
96: struct de_pcbb {
97: short pcbb0; /* function */
98: short pcbb2; /* command specific */
99: short pcbb4;
100: short pcbb6;
101: };
102:
103: /* PCBB function codes */
104: #define FC_NOOP 0x00 /* NO-OP */
105: #define FC_LSUADDR 0x01 /* Load and start microaddress */
106: #define FC_RDDEFAULT 0x02 /* Read default physical address */
107: #define FC_RDPHYAD 0x04 /* Read physical address */
108: #define FC_WTPHYAD 0x05 /* Write physical address */
109: #define FC_RDMULTI 0x06 /* Read multicast address list */
110: #define FC_WTMULTI 0x07 /* Read multicast address list */
111: #define FC_RDRING 0x08 /* Read ring format */
112: #define FC_WTRING 0x09 /* Write ring format */
113: #define FC_RDCNTS 0x0a /* Read counters */
114: #define FC_RCCNTS 0x0b /* Read and clear counters */
115: #define FC_RDMODE 0x0c /* Read mode */
116: #define FC_WTMODE 0x0d /* Write mode */
117: #define FC_RDSTATUS 0x0e /* Read port status */
118: #define FC_RCSTATUS 0x0f /* Read and clear port status */
119: #define FC_DUMPMEM 0x10 /* Dump internal memory */
120: #define FC_LOADMEM 0x11 /* Load internal memory */
121: #define FC_RDSYSID 0x12 /* Read system ID parameters */
122: #define FC_WTSYSID 0x13 /* Write system ID parameters */
123: #define FC_RDSERAD 0x14 /* Read load server address */
124: #define FC_WTSERAD 0x15 /* Write load server address */
125:
126: /*
127: * Unibus Data Block Base (UDBB) for ring buffers
128: */
129: struct de_udbbuf {
130: short b_tdrbl; /* Transmit desc ring base low 16 bits */
131: char b_tdrbh; /* Transmit desc ring base high 2 bits */
132: char b_telen; /* Length of each transmit entry */
133: short b_trlen; /* Number of entries in the XMIT desc ring */
134: short b_rdrbl; /* Receive desc ring base low 16 bits */
135: char b_rdrbh; /* Receive desc ring base high 2 bits */
136: char b_relen; /* Length of each receive entry */
137: short b_rrlen; /* Number of entries in the RECV desc ring */
138: };
139:
140: /*
141: * Transmit/Receive Ring Entry
142: */
143: struct de_ring {
144: short r_slen; /* Segment length */
145: short r_segbl; /* Segment address (low 16 bits) */
146: char r_segbh; /* Segment address (hi 2 bits) */
147: u_char r_flags; /* Status flags */
148: u_short r_tdrerr; /* Errors */
149: #define r_lenerr r_tdrerr
150: short r_rid; /* Request ID */
151: };
152:
153: #define XFLG_OWN 0x80 /* If 0 then owned by driver */
154: #define XFLG_ERRS 0x40 /* Error summary */
155: #define XFLG_MTCH 0x20 /* Address match on xmit request */
156: #define XFLG_MORE 0x10 /* More than one entry required */
157: #define XFLG_ONE 0x08 /* One collision encountered */
158: #define XFLG_DEF 0x04 /* Transmit deferred */
159: #define XFLG_STP 0x02 /* Start of packet */
160: #define XFLG_ENP 0x01 /* End of packet */
161:
162: #define XFLG_BITS "\10\10OWN\7ERRS\6MTCH\5MORE\4ONE\3DEF\2STP\1ENP"
163:
164: #define XERR_BUFL 0x8000 /* Buffer length error */
165: #define XERR_UBTO 0x4000 /* UNIBUS tiemout
166: #define XERR_LCOL 0x1000 /* Late collision */
167: #define XERR_LCAR 0x0800 /* Loss of carrier */
168: #define XERR_RTRY 0x0400 /* Failed after 16 retries */
169: #define XERR_TDR 0x03ff /* TDR value */
170:
171: #define XERR_BITS "\20\20BUFL\17UBTO\15LCOL\14LCAR\13RTRY"
172:
173: #define RFLG_OWN 0x80 /* If 0 then owned by driver */
174: #define RFLG_ERRS 0x40 /* Error summary */
175: #define RFLG_FRAM 0x20 /* Framing error */
176: #define RFLG_OFLO 0x10 /* Message overflow */
177: #define RFLG_CRC 0x08 /* CRC error */
178: #define RFLG_STP 0x02 /* Start of packet */
179: #define RFLG_ENP 0x01 /* End of packet */
180:
181: #define RFLG_BITS "\10\10OWN\7ERRS\6FRAM\5OFLO\4CRC\2STP\1ENP"
182:
183: #define RERR_BUFL 0x8000 /* Buffer length error */
184: #define RERR_UBTO 0x4000 /* UNIBUS tiemout */
185: #define RERR_NCHN 0x2000 /* No data chaining */
186: #define RERR_MLEN 0x0fff /* Message length */
187:
188: #define RERR_BITS "\20\20BUFL\17UBTO\16NCHN"
189:
190: /* mode description bits */
191: #define MOD_HDX 0x0001 /* Half duplex mode */
192: #define MOD_LOOP 0x0004 /* Enable internal loopback */
193: #define MOD_DTCR 0x0008 /* Disables CRC generation */
194: #define MOD_DMNT 0x0200 /* Disable maintenance features */
195: #define MOD_ECT 0x0400 /* Enable collision test */
196: #define MOD_TPAD 0x1000 /* Transmit message pad enable */
197: #define MOD_DRDC 0x2000 /* Disable data chaining */
198: #define MOD_ENAL 0x4000 /* Enable all multicast */
199: #define MOD_PROM 0x8000 /* Enable promiscuous mode */
200:
201: struct de_buf {
202: struct ether_header db_head; /* header */
203: char db_data[ETHERMTU]; /* packet data */
204: int db_crc; /* CRC - on receive only */
205: };
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