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1.1 ! root 1: /* ! 2: * Copyright (c) 1982, 1986 Regents of the University of California. ! 3: * All rights reserved. ! 4: * ! 5: * Redistribution is only permitted until one year after the first shipment ! 6: * of 4.4BSD by the Regents. Otherwise, redistribution and use in source and ! 7: * binary forms are permitted provided that: (1) source distributions retain ! 8: * this entire copyright notice and comment, and (2) distributions including ! 9: * binaries display the following acknowledgement: This product includes ! 10: * software developed by the University of California, Berkeley and its ! 11: * contributors'' in the documentation or other materials provided with the ! 12: * distribution and in all advertising materials mentioning features or use ! 13: * of this software. Neither the name of the University nor the names of ! 14: * its contributors may be used to endorse or promote products derived from ! 15: * this software without specific prior written permission. ! 16: * THIS SOFTWARE IS PROVIDED AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED ! 17: * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF ! 18: * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. ! 19: * ! 20: * @(#)if_enreg.h 7.3 (Berkeley) 6/28/90 ! 21: */ ! 22: ! 23: /* ! 24: * Xerox experimental ethernet registers. ! 25: * ! 26: * N.B.: status register and device address are read/write, ! 27: * device address is read-only, rest are WRITE ONLY! ! 28: */ ! 29: struct endevice { ! 30: short en_owc; /* output word count (10 bits) */ ! 31: short en_oba; /* output buffer address */ ! 32: short en_ostat; /* output control and status */ ! 33: short en_odelay; /* output start delay, 25usec units */ ! 34: short en_iwc; /* input word count */ ! 35: short en_iba; /* input buffer address */ ! 36: short en_istat; /* input csr */ ! 37: short en_addr; /* ~device address (low 8 bits) */ ! 38: }; ! 39: ! 40: /* ! 41: * Control and status bits. ! 42: */ ! 43: #define EN_IERROR 0x8000 /* CRC error, buf ovflo or overrun */ ! 44: #define EN_OERROR 0x8000 /* collision or output underrun */ ! 45: #define EN_OPDONE 0x0080 /* previous operation completed */ ! 46: #define EN_IEN 0x0040 /* enable interrupt when DONE */ ! 47: #define EN_PROMISCUOUS 0x0002 /* promiscuous, input any packet */ ! 48: #define EN_GO 0x0001 /* start op bit */ ! 49: ! 50: #define EN_BITS "\10\20ERR\10OPDONE\7IEN\2PROM\1GO" ! 51: ! 52: #define spl_enet() spl5()
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