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1.1 root 1: /*
2: * Copyright (c) 1988 Regents of the University of California.
3: * All rights reserved.
4: *
5: * This code is derived from software contributed to Berkeley by
6: * Advanced Computer Communications.
7: *
8: * Redistribution is only permitted until one year after the first shipment
9: * of 4.4BSD by the Regents. Otherwise, redistribution and use in source and
10: * binary forms are permitted provided that: (1) source distributions retain
11: * this entire copyright notice and comment, and (2) distributions including
12: * binaries display the following acknowledgement: This product includes
13: * software developed by the University of California, Berkeley and its
14: * contributors'' in the documentation or other materials provided with the
15: * distribution and in all advertising materials mentioning features or use
16: * of this software. Neither the name of the University nor the names of
17: * its contributors may be used to endorse or promote products derived from
18: * this software without specific prior written permission.
19: * THIS SOFTWARE IS PROVIDED AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
20: * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
21: * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22: *
23: * @(#)if_hdhreg.h 7.3 (Berkeley) 6/28/90
24: */
25:
26: /*
27: * ACC IF-11/HDH interface
28: */
29:
30: struct hdhregs { /* device registers */
31: u_short csr; /* control and status register */
32: u_char iochn; /* logical channel */
33: u_char ioadx; /* address extension (A16,A17) */
34: u_short ioadl; /* buffer address (A0-A15) */
35: u_short iocnt; /* byte count */
36: u_char iofcn; /* UMC funciton code */
37: u_char iosbf; /* UMC subfunction code */
38: u_char ioini; /* comm regs valid flag */
39: u_char staack; /* interrupt acknowledge flag */
40: u_char ionmi; /* NMI routine active flag */
41: u_char ioxfrg; /* UMR transfer grant flag */
42: u_char stachn; /* interrupt channel number */
43: u_char statyp; /* interrupt type code */
44: u_char stacc; /* completion function code */
45: u_char stacs; /* completion subfunction code */
46: u_short stacnt; /* completion byte count */
47: };
48:
49: /* defines for CSR */
50:
51: #define HDH_UER 0100000 /* UMC error condition */
52: #define HDH_NXM 0040000 /* non-existent memory error */
53: #define HDH_PER 0020000 /* UNIBUS parity error */
54: #define HDH_ZRUN 0010000 /* Z80 running */
55: #define HDH_ZGO 0004000 /* Z80 not in wait state */
56: #define HDH_MBLK 0000200 /* memory swap state (0=main, 1=srv) */
57: #define HDH_SRV 0000100 /* select UMC service memory */
58: #define HDH_MAIN 0000040 /* select UMC main memory */
59: #define HDH_DMA 0000020 /* DMA enable */
60: #define HDH_WRT 0000010 /* DMA write enable */
61: #define HDH_IEN 0000004 /* interrupt enable */
62: #define HDH_RST 0000002 /* reset */
63: #define HDH_NMI 0000001 /* cause NMI */
64:
65: #define HDH_BITS \
66: "\10\20UER\17NXM\16PER\15ZRUN\14ZGO\10MBLK\7SRV\6MAIN\5DMA\4WRT\3IEN\2RST\1NMI"
67:
68: /* start i/o function code definitions */
69:
70: #define HDHWRT 0 /* write to if-11 */
71: #define HDHRDB 1 /* read from if-11 */
72: #define HDHSTR 2 /* stream flag */
73: #define HDHEOS 6 /* end of stream flag */
74: #define HDHABT 8 /* abort flag */
75: #define HDHUMR 16 /* UMR protocol flag */
76:
77: /* interrupt type definitions */
78:
79: #define HDHSACK 0 /* start i/o ack */
80: #define HDHDONE 1 /* i/o completion */
81: #define HDHXREQ 2 /* UMR protocol transfer request */
82:
83: /* i/o completion codes */
84:
85: #define HDHIOCOK 0001 /* successful completion */
86: #define HDHIOCOKP 0002 /* successful completion, more data pending */
87: #define HDHIOCABT 0361 /* i/o aborted */
88: #define HDHIOCERR 0321 /* program error */
89: #define HDHIOCOVR 0363 /* overrun error */
90: #define HDHIOCUBE 0374 /* non-existant memory or unibus error */
91:
92: /* UMR protocol transfer grant code definitions */
93:
94: #define HDHXEVN 1 /* start with even address */
95: #define HDHXODD 2 /* start with odd address */
96: #define HDHNUMR 4 /* non-UMR transfer */
97: #define HDHXABT 8 /* abort transfer */
98:
99: /* HDH supervisor request code definitions */
100: #define HDHINIT 0x42 /* SYSINIT opcode */
101:
102: #define HDHSUP 0xf0 /* supervisor HDH status/line control prefix */
103: #define HDHIMP 0x400 /* IMP line up modifier */
104: #define HDHREFL 0x800 /* reflect mode modifier */
105: #define HDHINLB 0x1000 /* internal loopback modifier */
106: #define HDHEXLP 0x2000 /* external loopback modifier */
107: #define HDHRQST (HDHSUP+0x0000) /* line status request */
108: #define HDHRQUP (HDHSUP+0x0100) /* line up request */
109: #define HDHRQDN (HDHSUP+0x0200) /* line down request */
110:
111: /* HDH supervisor reply code definitions */
112:
113: #define HDHIACK (HDHSUP+0x4200) /* line init ack */
114: #define HDHLNUP (HDHSUP+0x0100) /* line up reply */
115: #define HDHLNDN (HDHSUP+0x0200) /* line down reply */
116: #define HDHLNACK (HDHSUP+0x0300) /* ack line up request (but line is down now) */
117: #define HDHTIMO (HDHSUP+0x0400) /* line timeout */
118: #define HDHLOOP (HDHSUP+0x0500) /* loopback message */
119: #define HDHDTERR (HDHSUP+0x0600) /* host data error detected */
120: #define HDHSQRCV (HDHSUP+0x0700) /* HDLC sequence error detected by IMP */
121: #define HDHSQERR (HDHSUP+0x0800) /* HDLC sequence error detected by if-11 */
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