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Annotation of 43BSDReno/sys/vaxif/if_pclreg.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * Copyright (c) 1982, 1986 Regents of the University of California.
        !             3:  * All rights reserved.
        !             4:  *
        !             5:  * Redistribution is only permitted until one year after the first shipment
        !             6:  * of 4.4BSD by the Regents.  Otherwise, redistribution and use in source and
        !             7:  * binary forms are permitted provided that: (1) source distributions retain
        !             8:  * this entire copyright notice and comment, and (2) distributions including
        !             9:  * binaries display the following acknowledgement:  This product includes
        !            10:  * software developed by the University of California, Berkeley and its
        !            11:  * contributors'' in the documentation or other materials provided with the
        !            12:  * distribution and in all advertising materials mentioning features or use
        !            13:  * of this software.  Neither the name of the University nor the names of
        !            14:  * its contributors may be used to endorse or promote products derived from
        !            15:  * this software without specific prior written permission.
        !            16:  * THIS SOFTWARE IS PROVIDED AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
        !            17:  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
        !            18:  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
        !            19:  *
        !            20:  *     @(#)if_pclreg.h 7.3 (Berkeley) 6/28/90
        !            21:  */
        !            22: 
        !            23: /*
        !            24:  * DEC CSS PCL-11B Parallel Communications Interface
        !            25:  */
        !            26: 
        !            27: struct pcldevice  {
        !            28:        u_short pcl_tcr;        /* Transmitter Command Register */
        !            29:        u_short pcl_tsr;        /* Transmitter Status Register */
        !            30:        u_short pcl_tsdb;       /* Transmitter Source Data Buffer */
        !            31:        short   pcl_tsbc;       /* Transmitter Source Byte Count */
        !            32:        u_short pcl_tsba;       /* Transmitter Source Bus Address */
        !            33:        u_short pcl_tmmr;       /* Transmitter Master/Maint Regs */
        !            34:        u_short pcl_tscrc;      /* Transmitter Source CRC */
        !            35:        u_short pcl_spare;
        !            36:        u_short pcl_rcr;        /* Receiver Command Register */
        !            37:        u_short pcl_rsr;        /* Receiver Status Register */
        !            38:        u_short pcl_rddb;       /* Receiver Destination Data Buffer */
        !            39:        short   pcl_rdbc;       /* Receiver Destination Byte Count */
        !            40:        u_short pcl_rdba;       /* Receiver Destination Bus Address */
        !            41:        u_short pcl_rdcrc;      /* Receiver Destination CRC */
        !            42: };
        !            43: 
        !            44: /* Transmitter Command and Status Bits */
        !            45: #define PCL_STTXM      (1<<0)          /* Start transmission */
        !            46: #define PCL_TXINIT     (1<<1)          /* Transmitter Initialize */
        !            47: #define PCL_IE         (1<<6)          /* Interrupt Enable */
        !            48: #define PCL_SNDWD      (1<<13)         /* Send word */
        !            49: #define PCL_TXNPR      (1<<14)         /* Transmitter NPR */
        !            50: #define PCL_RIB                (1<<15)         /* Retry if busy */
        !            51: 
        !            52: #define PCL_RESPA      (3<<0)          /* Response A bits (tsr & rsr) */
        !            53: #define PCL_RESPB      (3<<2)          /* Response B bits (tsr & rsr) */
        !            54: #define PCL_MSTDWN     (1<<11)         /* Master down */
        !            55: #define PCL_ERR                (1<<15)         /* Error summary */
        !            56: 
        !            57: #define PCL_MASTER     (1<<8)          /* Set MASTER status */
        !            58: #define PCL_AUTOADDR   (1<<12)         /* Auto time slicing */
        !            59: 
        !            60: /* Receiver Command and Status Bits */
        !            61: #define PCL_RCVDAT     (1<<0)          /* Receive data */
        !            62: #define PCL_RCINIT     (1<<1)          /* Receiver Initialize */
        !            63: #define PCL_RCVWD      (1<<13)         /* Receive word */
        !            64: #define PCL_RCNPR      (1<<14)         /* Receive NRP */
        !            65: #define PCL_REJ                (1<<15)         /* Reject transmission */
        !            66: 
        !            67: #define PCL_BCOFL      (1<<9)          /* Byte Counter Overflow */
        !            68: 
        !            69: #define PCL_TERRBITS   "\20\20ERR\17NXL\16MEM_OFL\15TXM_ERR\14MST_DWN\13TIM_OUT\12OVERRUN\11DTI_RDY\10SUC_TXF\07BUSY\06SOREJ\05TBS_BUSY"
        !            70: #define PCL_TCSRBITS   "\20\20RIB\17TX_NPR\16SND_WD\10RD_SILO\07IE\04DTO_RDY\03INH_ADI\02TX_INIT\01START_TXM"
        !            71: 
        !            72: #define PCL_RERRBITS   "\20\20ERR\17NXL\16MEM_OFL\15TXM_ERR\14PARITY\13TIM_OUT\12BC_OFL\11DTO_RDY\10SUC_TXF\07BUSY\06REJ_COMP\05CHN_OPN"
        !            73: #define PCL_RCSRBITS   "\20\20REJ\17RC_NPR\16RCV_WD\10LD_SILO\07IE\04DTI_RDY\03INH_ADI\02RC_INIT\01RCV_DAT"

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