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Annotation of 43BSDReno/sys/vaxuba/dhreg.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * Copyright (c) 1982, 1986 Regents of the University of California.
        !             3:  * All rights reserved.  The Berkeley software License Agreement
        !             4:  * specifies the terms and conditions for redistribution.
        !             5:  *
        !             6:  *     @(#)dhreg.h     7.1 (Berkeley) 6/5/86
        !             7:  */
        !             8: 
        !             9: /* 
        !            10:  * DH-11 device register definitions.
        !            11:  */
        !            12: struct dhdevice {
        !            13:        union {
        !            14:                short   dhcsr;          /* control-status register */
        !            15:                char    dhcsrl;         /* low byte for line select */
        !            16:        } un;
        !            17:        short   dhrcr;                  /* receive character register */
        !            18:        short   dhlpr;                  /* line parameter register */
        !            19:        u_short dhcar;                  /* current address register */
        !            20:        short   dhbcr;                  /* byte count register */
        !            21:        u_short dhbar;                  /* buffer active register */
        !            22:        short   dhbreak;                /* break control register */
        !            23:        short   dhsilo;                 /* silo status register */
        !            24: };
        !            25: 
        !            26: /* Bits in dhcsr */
        !            27: #define        DH_TI   0100000         /* transmit interrupt */
        !            28: #define        DH_SI   0040000         /* storage interrupt */
        !            29: #define        DH_TIE  0020000         /* transmit interrupt enable */
        !            30: #define        DH_SIE  0010000         /* storage interrupt enable */
        !            31: #define        DH_MC   0004000         /* master clear */
        !            32: #define        DH_NXM  0002000         /* non-existant memory */
        !            33: #define        DH_MM   0001000         /* maintenance mode */
        !            34: #define        DH_CNI  0000400         /* clear non-existant memory interrupt */
        !            35: #define        DH_RI   0000200         /* receiver interrupt */
        !            36: #define        DH_RIE  0000100         /* receiver interrupt enable */
        !            37: 
        !            38: /* Bits in dhlpr */
        !            39: #define        BITS6   01
        !            40: #define        BITS7   02
        !            41: #define        BITS8   03
        !            42: #define        TWOSB   04
        !            43: #define        PENABLE 020
        !            44: /* DEC manuals incorrectly say this bit causes generation of even parity. */
        !            45: #define        OPAR    040
        !            46: #define        HDUPLX  040000
        !            47: 
        !            48: #define        DH_IE   (DH_TIE|DH_SIE|DH_RIE)
        !            49: 
        !            50: /* Bits in dhrcr */
        !            51: #define        DH_PE           0010000         /* parity error */
        !            52: #define        DH_FE           0020000         /* framing error */
        !            53: #define        DH_DO           0040000         /* data overrun */

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