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1.1 root 1: /*
2: * Copyright (c) 1986 MICOM-Interlan, Inc., Boxborough Mass
3: * All rights reserved. The Berkeley software License Agreement
4: * specifies the terms and conditions for redistribution.
5: *
6: * @(#)npreg.h 7.2 (Berkeley) 4/8/87
7: *
8: * Merged header file for MICOM-Interlan NP100.
9: */
10:
11: /*
12: * np100.h version 1.3
13: *
14: * This version retrieved: 8/18/86 @ 18:58:44
15: * This delta created: 8/18/86 @ 18:27:32
16: */
17: /*
18: * Typedefs for the VAX
19: */
20:
21: typedef short sign16; /* 16 bit signed value */
22: typedef unsigned short unsign16; /* 16 bit unsigned value */
23: typedef unsigned unsign32; /* 32 bit unsigned value */
24: typedef long paddr_t; /* Physical addresses */
25:
26:
27: /*
28: * Tunables
29: */
30:
31:
32: #define NUMCQE 40 /* Number of CQE's per board */
33:
34: /* Host configuration word in Status Block */
35:
36: /*
37: * To disable the lock/unlock internal function calls clear the 0x8000
38: * bit in the host configuration word (HOSTCONF)
39: */
40:
41: #define HOSTCONF 0x0109 /* See above */
42: #define LOWBYTE 1
43: #define HIGHBYTE 0
44: #define BUFFMAPPED 0
45:
46: /*
47: * Memory mapping definintions for PM68DUAL hardware.
48: */
49:
50: #ifdef PM68DUAL
51: #define PISHMEM 0x200000
52: #define PISHMEMSIZE 2
53: #define PIOFF 0x8000 /* change this to unique mem add. */
54: #define PIWINDOW MBUSBUFR + PIOFF
55: #define WINDOWSIZE 2
56: #endif
57: #define NPMAXXFR 32768 /* Maximum number of bytes / read */
58:
59: /*
60: * Define the protocols supported by the NP Driver.
61: */
62:
63: #define NONE 0x00 /* No protocols active for a process */
64: #define NPMAINT 0x01 /* Maintenance protocol, superusers only */
65: #define NPNTS 0x02 /* NTS Terminal Server */
66: #define NPIDP 0x04 /* Direct Datalink Access */
67: #define NPDLA 0x04 /* Direct Datalink Access */
68: #define NPXNS 0x06 /* Xerox NS ITP */
69: #define NPTCP 0x08 /* TCP/IP */
70: #define NPISO 0x0A /* ISO */
71: #define NPCLCONN 0xFF /* Closed connection, i.e. no protocol */
72:
73: /*
74: * Convert the protocol to a value used in the Device Protocol Mask field
75: * of the Shared Memory Status Block.
76: */
77:
78: #define PROTOMASK(x) ( 1 << (x) )
79:
80: /*
81: * Special requests handled by the NP Driver
82: */
83:
84: #define OS_STP 03400 /* Shut down connection on I Board */
85: #define NPSTOP 3 /* Conversion from above (OS_STP) */
86: #define NPCHNGP 50 /* Change the protocol on a connection */
87: #define NPCHNGB 51 /* Change the Board number */
88:
89: /*
90: * Miscellaneous
91: */
92:
93: #define ON 0x8000 /* Used for Command Q's scan and change flag */
94: #define UBADDRMASK 0x3FFFF /* 18 bit UNIBUS address */
95: #define INTMASK 0xFFFFFFFC /* Used for address validation */
96: #define CMDMASK 0xFFFF /* Mask ioctl cmd field (see ioctl.h) */
97: #define NPPSADDR 0x324 /* Pointer to addr of on-board panic string */
98: #define PANLEN 133 /* length of the panic buffer */
99:
100: /*
101: * Map function code from user to I-Board format
102: */
103:
104: #define FUNCTMAP(x) (((x) << 6) | 077) /* Maps user function to NP funcs */
105:
106: /*
107: * Round up to a 16 byte boundary
108: */
109:
110: #define ROUND16(x) (((x) + 15) & (~0x0F)) /* Round to 16 byte boundary */
111: #define ADDR24 1 /* Used by iomalloc() to specify 24 bit address */
112:
113: #define NPERRSHIFT 8 /* Used in function ReqDone() */
114: #define NPOK 0
115:
116: #define LOWORD(X) (((ushort *)&(X))[0])
117: #define HIWORD(X) (((ushort *)&(X))[1])
118:
119: /* Everyday flag settings */
120:
121: #define NPSET 1
122: #define NPCLEAR 0
123:
124: /*
125: * Command Queue Elements are the primary data structure for passing data
126: * between the driver and the device.
127: */
128:
129: struct CQE {
130:
131: struct npreq *cqe_reqid;/* Address of asssociated npreq */
132: union {
133: unsign32 cqe_Famid; /* Family ID (Process ID) - wn */
134: unsign16 cqe_PrtSig[2]; /* port and signal - tn */
135: } u1;
136: #define cqe_famid u1.cqe_Famid
137: #define cqe_port u1.cqe_PrtSig[0]
138: #define cqe_signal u1.cqe_PrtSig[1]
139: unsign16 cqe_func; /* I/O function to be performed */
140: #ifdef mc68000
141: char cqe_prot; /* Protocol type for I/O request */
142: char cqe_lenrpb; /* Length of the RPB in bytes */
143: #else
144: char cqe_lenrpb; /* Length of the RPB in bytes */
145: char cqe_prot; /* Protocol type for I/O request */
146: #endif
147: union {
148: unsign16 cqe_ustS[2]; /* Protocol status return */
149: unsign32 cqe_ustL; /* Protocol status return */
150: } u2;
151: #define cqe_ust0 u2.cqe_ustS[0]
152: #define cqe_ust1 u2.cqe_ustS[1]
153: #define cqe_usts u2.cqe_ustL
154: unsign16 cqe_devrsv; /* Reserved for use by device only! */
155: #ifdef mc68000
156: char cqe_char; /* CQE characteristics */
157: char cqe_sts; /* Status return from device to user */
158: char cqe_wind; /* Buffer mapping window size (page units) */
159: char cqe_nbuf; /* Number of data buffers for I/O */
160: #else
161: char cqe_sts; /* Status return from device to user */
162: char cqe_char; /* CQE characteristics */
163: char cqe_nbuf; /* Number of data buffers for I/O */
164: char cqe_wind; /* Buffer mapping window size (page units) */
165: #endif
166: unsign16 cqe_bcnt; /* Total number of bytes in the data buffer */
167: union {
168: unsign16 cqe_Unused; /* Unused */
169: struct {
170: char cqe_Maxbcnt; /* Maximum size of buffer */
171: char cqe_Bflags; /* Used by the SPI */
172: } s;
173: } u3;
174: #define cqe_unused u3.cqe_Unused
175: #define cqe_maxbcnt u3.s.cqe_Maxbcnt
176: #define cqe_bflags u3.s.cqe_Bflags
177: unsign16 cqe_dma[2]; /* Address of the MULTIBUS data buffer */
178: unsign16 rpb1; /* Word 1 of protocol parameters */
179: unsign16 rpb2; /* Word 2 of protocol parameters */
180: unsign16 rpb3; /* Word 3 of protocol parameters */
181: unsign16 rpb4; /* Word 4 of protocol parameters */
182: unsign16 rpb5; /* Word 5 of protocol parameters */
183: unsign16 rpb6; /* Word 6 of protocol parameters */
184: unsign16 rpb7; /* Word 7 of protocol parameters */
185: unsign16 rpb8; /* Word 8 of protocol parameters */
186: unsign16 rpb9; /* Word 9 of protocol parameters */
187: unsign16 rpb10; /* Word 10 of protocol parameters */
188: unsign16 rpb11; /* Word 11 of protocol parameters */
189: unsign16 rpb12; /* Word 12 of protocol parameters */
190:
191: };
192:
193: /*
194: * NP Driver Request structure contains information about a request
195: * maintained solely by the driver. One per CQE, plus a header.
196: */
197:
198: struct npreq {
199:
200: struct npreq *forw; /* Forward pointer for active list */
201: struct npreq *back; /* Backward pointer for active list */
202: struct npreq *free; /* Next member on free list */
203: struct CQE *element; /* CQE associated with this request */
204: int flags; /* Always useful */
205: int reqcnt; /* Request count for reqtab */
206: int bufoffset; /* Offset into buffer for turns */
207: int bytecnt; /* Number of bytes to transfer */
208: caddr_t virtmem; /* Virtual address of buffer */
209: int mapbase; /* Address of the mapping register */
210: int mapsize; /* Size of mapped area */
211: caddr_t bufaddr; /* Address of the user buffer */
212: struct buf buf; /* Buf structure needed for mem. mgmt */
213: struct proc *procp; /* Pointer to process of requestor */
214: caddr_t user; /* Structure passed by user from itpuser.h */
215: int (*intr)(); /* Ptr to routine to call at interrupt time */
216: int int_param; /* Paramater to be used by above routine */
217: };
218:
219: /*
220: * Npmaster structure, one per device, is used for boardwise centralization
221: * of relevant information including queues, I/O addresses and request pools.
222: */
223:
224: struct npmaster {
225:
226: struct npmaster *next; /* Linked list of these, NULL terminator */
227: struct npspace *shmemp; /* Shared memory address (driver <-> device) */
228: struct uba_device *devp; /* UBA Device for this unit */
229: struct NPREG *iobase; /* I/O base address for this board */
230: struct npreq *reqtab; /* Header for pool of CQE requests */
231: int iomapbase; /* Base index of I/O map reg's allocated */
232: int flags; /* State of the Board */
233: int unit; /* Unit number of this device */
234: int vector; /* Interrupt vector for this unit */
235: };
236:
237: struct NPREG {
238: unsign16 CSR0; /* Control Status Register 0 */
239: unsign16 CSR1; /* Control Status Register 1 */
240: unsign16 CSR2; /* Control Status Register 2 */
241: unsign16 CSR3; /* Control Status Register 3 */
242:
243: };
244:
245: /*
246: * The following structures are used for communicating with the
247: * Intelligent Board and are located in Shared Memory.
248: */
249:
250: /*
251: * Status Block
252: */
253:
254: struct NpStat{
255:
256: unsign16 sb_drw; /* Device Request Word */
257: unsign16 sb_hcw; /* Host Configuration Word */
258: unsign16 sb_dcw; /* Device Configuration Word */
259: unsign16 sb_dpm; /* Device Protocol Mask */
260: unsign16 sb_dcq; /* Offset to Device CQ */
261: unsign16 sb_hcq; /* Offset to Host CQ */
262: };
263:
264: /*
265: * Command Queue, two per device. One is owned by the driver and the other
266: * is owned by the device.
267: */
268:
269: struct CmdQue {
270:
271: unsign16 scanflag; /* Scan Flag, MSB set if being scanned */
272: unsign16 chngflag; /* Change Flag, MSB set by initiator */
273: unsign16 cq_wrap; /* Offset to last CQE entry +2 */
274: unsign16 cq_add; /* Offset to add a CQE to the queue */
275: unsign16 cq_rem; /* Offset to remove a CQE from the queue */
276: unsign16 cq_cqe[NUMCQE]; /* Command Queue Element Offsets */
277: };
278:
279: /*
280: * Structure of the shared memory area per board. Declared this way to avoid
281: * compiler word alignment vagaries when computing offsets.
282: */
283:
284: struct npspace {
285:
286: struct NpStat statblock; /* Status Block */
287: struct CmdQue devcq; /* Device's Command Queue */
288: struct CmdQue hostcq; /* Host's Command Queue */
289: struct CQE elements[NUMCQE]; /* Shared Command Queue Elements */
290: unsign16 filler[8]; /* Here for 16 byte alignment */
291: };
292:
293: /*
294: * Structure of array of base addresses of I-Board controllers
295: * (See global data definitions in np.c)
296: */
297:
298: struct npbase {
299: caddr_t baseaddr;
300: };
301:
302: /* State of the NP Driver as kept in NpState */
303:
304: #define ICPAVAIL 0x01 /* ICP is waiting for a request */
305:
306: /* Tells ICP Process that there are no more requests for this board */
307:
308: #define BRDDONE 1
309:
310: /* Flags used by the driver (npreq structure) to monitor status of requests */
311:
312: #define REQDONE 0x01 /* Request completed */
313: #define IOIFC 0x02 /* Internal Function Code Request */
314: #define IOERR 0x04 /* Error on Request */
315: #define NPPEND 0x08 /* Unused at this time */
316: #define IOABORT 0x10 /* Request aborted by ICP */
317: #define KERNREQ 0x20 /* Request was from the kernel */
318: #define WANTREQ 0x40 /* Process is waiting for a npreq structure */
319: #define NPUIO 0x80 /* Process doing physio */
320: #define REQALOC 0x100 /* Request has been allocated */
321: #define REQUSE 0x200 /* Request is in request queue */
322:
323: /* Service Request Commands from the Intelligent Board */
324:
325: #define NOREQ 0x00 /* No service requested */
326: #define NPLOAD 0x01 /* Dump request */
327: #define NPDUMP 0x02 /* Load request */
328: #define NPPANIC 0x100 /* Panic request */
329:
330: /* Definitions of Status returned from the I-Board */
331:
332: #define NPDONE 0x01 /* Normal completion */
333: #define NPIFC 0x00 /* Internal Function Code request */
334: #define NPPERR 0x80 /* Protocol error */
335: #define NPMERR 0x82 /* Memory allocation failure on I-Board */
336:
337: /* Definitions of IFC type requests from I-Board */
338:
339: #define NPLOCK 0x64 /* Lock the process's data area */
340: #define NPUNLOCK 0xA4 /* Unlock the process */
341: #define NPREMAP 0x124 /* Window turn */
342:
343: /* Definition of flags for the Npmaster structure */
344:
345: #define CSRPEND 0x01 /* CSR0 command pending */
346: #define PANICREQ 0x02 /* Panic request */
347: #define DUMPREQ 0x04 /* Dump request */
348: #define LOADREQ 0x08 /* Load request */
349: #define BOARDREQ 0x10 /* Any request by the board */
350: #define BADBOARD 0x20 /* Board disabled */
351: #define AVAILABLE 0x40 /* Board available */
352: #define BRDRESET 0x80 /* Board is being reset */
353: #define PANIC1 0x100 /* Driver wants panic address */
354: #define PANIC2 0x200 /* Driver wants panic string */
355: #define PANIC3 0x400 /* Clear first byte of panic string */
356: #define LSTCMD 0x800 /* Clear last command during NPIO */
357: #define SCANNING 0x1000 /* We are scanning for cqe's */
358:
359: /*
360: * Debugging Constants
361: */
362:
363: #define DEBENTRY 0x0001 /* debug entry points */
364: #define DEBMEM 0x0002 /* debug memory */
365: #define DEBREQ 0x0004 /* debug requests */
366: #define DEBCQE 0x0008 /* debug cqe's */
367: #define DEBCQ 0x0010 /* debug cq's */
368: #define DEBMAINT 0x0020 /* debug maintainance requests */
369: #define DEBINTR 0x0040 /* debug interrupt routines */
370: #define DEBINIT 0x0080 /* debug initialization routines */
371: #define DEBIFC 0x0100 /* debug Internal function codes */
372: #define DEBIOCTL 0x0200 /* debug ioctl calls */
373: #define DEBOPEN 0x0400 /* debug open calls */
374: #define DEBIO 0x0800 /* debug read & write calls */
375: #define DEBCSR 0x1000 /* debug CSR commands */
376: #define DEBLOCK 0x2000 /* debug lock / unlock calls */
377: #define NOBOARD 0x4000 /* debug user/host interface */
378: #define DEBCANCEL 0x8000 /* debug cancel command */
379:
380: /*
381: * npreg.h version 1.3
382: *
383: * This version retrieved: 8/18/86 @ 18:58:46
384: * This delta created: 8/18/86 @ 18:27:42
385: */
386:
387: /*
388: * NPREG.H
389: *
390: * This file contain definitions of specific hardware interest
391: * to be used when communicating with the NI1510 Network Processor
392: * Board. More complete information can be found in the NI1510
393: * Multibus compatible Ethernet Communications Processor Hardware
394: * Specification.
395: */
396:
397: /*
398: * npcmd.h version 1.3
399: *
400: * This version retrieved: 8/18/86 @ 18:58:45
401: * This delta created: 8/18/86 @ 18:27:38
402: */
403: #ifndef IOC_VOID
404: # ifdef KERNEL
405: # include "../h/ioctl.h"
406: # else
407: # include <sys/ioctl.h>
408: # endif
409: #endif
410:
411: #ifdef KERNEL
412: # define IoVOID 0
413: #else
414: # define IoVOID IOC_VOID
415: #endif
416:
417: #define NPRESET (IoVOID|0x01) /* reset the board */
418: #define NPSTART (IoVOID|0x04) /* start board execution */
419: #define NPGPANIC (IoVOID|0x05) /* Get panic message */
420: #define NPINIT (IoVOID|0x06) /* initialize software on board */
421: #define NPSTATS (IoVOID|0x07)
422: #define NPRCSR0 (IoVOID|0x08) /* read CSR0 */
423: #define NPRCSR1 (IoVOID|0x09) /* read CSR1 */
424: #define NPRCSR2 (IoVOID|0x0a) /* read CSR2 */
425: #define NPRCSR3 (IoVOID|0x0b) /* read CSR3 */
426: #define NPWCSR0 (IoVOID|0x0c) /* write CSR0 */
427: #define NPWCSR1 (IoVOID|0x0d) /* write CSR1 */
428: #define NPWCSR2 (IoVOID|0x0e) /* write CSR2 */
429: #define NPWCSR3 (IoVOID|0x0f) /* write CSR3 */
430: #define NPPOLL (IoVOID|0x10)
431: #define NPKILL (IoVOID|0x11)
432: #define NPSETPROT (IoVOID|0x12) /* set the protocol to use */
433: #define NPSETBOARD (IoVOID|0x13) /* set board to use */
434: #define NPSETNPDEB (IoVOID|0x14) /* set nc debuging level */
435: #define NPSETADDR (IoVOID|0x15) /* set host address */
436: #define NPNETBOOT (IoVOID|0x16) /* boot from the network */
437: #define NPSETLAST (IoVOID|0x17) /* set last command flag in NPIO */
438: #define NPCLRICNT (IoVOID|0x18) /* clear interupt count */
439: #define NPGETICNT (IoVOID|0x19) /* get interupt count */
440: #define NPGETIVEC (IoVOID|0x1a) /* get interupt vector */
441: #define NPMAPMEM (IoVOID|0x1b) /* map user memory to shmem */
442:
443: #define NP_SET 1031 /* set memory mapping */
444: #define NP_USET 1032 /* unset memory mapping */
445:
446: struct np_mem {
447: long mem_type;
448: char *mem_addr;
449: long mem_count;
450: } ;
451:
452: #define NNPCNN 4 /* Number of connections per board */
453: #define NPUNIT(a) ((minor(a) >> 4) & 0x0F)
454: #define NPCONN(a) ((minor(a)) & 0x03)
455:
456: #define TRUE 1
457: #define FALSE 0
458:
459: #define IBOOTADDR 0xF8000l /* Addr of 80186 Boot ROM */
460: #define INETBOOT 0xF8087l
461: #define IXEQADDR 0x400 /* Where to begin Board image XEQ */
462: #define DIAGTIME 1200 /* Time for timeout /HZ seconds */
463:
464: #define DELAYTIME 1000000L /* delay count */
465: #define NPDELAY(N) {register int n = (N) >> 1; while(--n > 0); }
466:
467: /* Handy macros for talking to the Board */
468:
469: #define RESET(x) (WCSR3(x->iobase,0xff))
470: #define CLEARINT(x) {unsign16 y; y = RCSR2(x->iobase); }
471: #define INTNI(x) (WCSR1(x->iobase,0xFF))
472:
473: /* Command and Status Register (CSR) Definitions */
474:
475: /*
476: * CSR0 is the only direct means for data transfer between the host processor
477: * and the 3510. Access is controlled by the 80186 who sets the CSR1 Enable and
478: * Ready bits to allow writing here. Writing to this register will always
479: * result in an interrupt to the 80186.
480: */
481:
482: /*
483: * Bit definitions for CSR1.
484: */
485:
486: #define NPRFU 0x01 /* Reserved for Future Use */
487: #define NPHOK 0x02 /* Hardware OK */
488: #define NPLAN 0x04 /* Logic 0 indicates operational LAN exists */
489: #define NP_IP 0x08 /* Interrupt pending from this board */
490: #define NP_IE 0x10 /* Interrupts enabled for this board */
491: #define NPRDR 0x20 /* Set when 80186 writes data into CSR0 */
492: #define NPRDY 0x40 /* CSR0 ready to accept data */
493: #define NPENB 0x80 /* CSR0 available for use by the host */
494:
495: /*
496: * Bit defintions for CSR0 Command Block
497: */
498:
499: #define NPLST 0x20 /* Last Command */
500: #define NPCMD 0x80 /* Shared Memory Address */
501: #define NPBGN 0x200 /* Begin Execution in On-Board Memory */
502: #define NPCBI 0x800 /* Interrupt at completion of Command Block */
503: #define NPDMP 0x2000 /* Dump 80186 On-Board Memory to Multibus */
504: #define NPLD 0x8000 /* Load 80186 On-board Memory from Multibus */
505:
506: /*
507: * CSR0 Count definitions. These are the lengths of the Command Blocks for the
508: * CSR0 commands above (not counting the Command Word itself).
509: */
510:
511: #define LSTCNT 0
512: #define CMDCNT 2
513: #define BGNCNT 2
514: #define CBICNT 1
515: #define DMPCNT 5
516: #define LDCNT 5
517: #define IOCNT 5
518:
519: /* Macros for reading and writing CSR's (Control and Status Registers) */
520:
521: #define WCSR0(x,y) ((x)->CSR0 = y)
522: #define WCSR1(x,y) ((x)->CSR1 = y)
523: #define WCSR2(x,y) ((x)->CSR2 = y)
524: #define WCSR3(x,y) ((x)->CSR3 = y)
525:
526: #define RCSR0(x) ((x)->CSR0)
527: #define RCSR1(x) ((x)->CSR1)
528: #define RCSR2(x) ((x)->CSR2)
529: #define RCSR3(x) ((x)->CSR3)
530:
531: struct npconn {
532:
533: struct npmaster *unit; /* Unit number (board) of this connection */
534: unsign16 protocol; /* Protocol used on this connection */
535: struct buf np_wbuf; /* write buf structure for raw access */
536: struct buf np_rbuf; /* read buf structure for raw access */
537: };
538:
539: /* ICP Board Requests */
540:
541: #define ICPLOAD 0x02
542: #define ICPDUMP 0x03
543: #define ICPPANIC 0x05
544: #define ICPPOLL 0x10
545:
546: /*
547: * npdebug.h version 1.3
548: *
549: * This version retrieved: 8/18/86 @ 18:58:46
550: * This delta created: 8/18/86 @ 18:27:39
551: */
552:
553: /*
554: * Debugging Constants
555: */
556:
557: #define DEBENTRY 0x0001 /* debug entry points */
558: #define DEBMEM 0x0002 /* debug memory */
559: #define DEBREQ 0x0004 /* debug requests */
560: #define DEBCQE 0x0008 /* debug cqe's */
561: #define DEBCQ 0x0010 /* debug cq's */
562: #define DEBMAINT 0x0020 /* debug maintainance requests */
563: #define DEBINTR 0x0040 /* debug interrupt routines */
564: #define DEBINIT 0x0080 /* debug initialization routines */
565: #define DEBIFC 0x0100 /* debug Internal function codes */
566: #define DEBIOCTL 0x0200 /* debug ioctl calls */
567: #define DEBOPEN 0x0400 /* debug open calls */
568: #define DEBIO 0x0800 /* debug read & write calls */
569: #define DEBCSR 0x1000 /* debug CSR commands */
570: #define DEBLOCK 0x2000 /* debug lock / unlock calls */
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