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1.1 root 1: /*
2: * Copyright (c) 1982, 1986 Regents of the University of California.
3: * All rights reserved. The Berkeley software License Agreement
4: * specifies the terms and conditions for redistribution.
5: *
6: * @(#)ubareg.h 7.7 (Berkeley) 10/20/88
7: */
8:
9: /*
10: * VAX UNIBUS adapter registers
11: */
12:
13: /*
14: * "UNIBUS" adaptor types.
15: * This code is used for both UNIBUSes and Q-buses
16: * with different types of adaptors.
17: * Definition of a type includes support code for that type.
18: */
19: #if VAX780 || VAX8600
20: #define DW780 1 /* has adaptor regs, sr: 780/785/8600 */
21: #endif
22:
23: #if VAX750
24: #define DW750 2 /* has adaptor regs, no sr: 750, 730 */
25: #endif
26:
27: #if VAX730
28: #define DW730 3 /* has adaptor regs, no sr: 750, 730 */
29: #endif
30:
31: #if VAX630 || VAX650
32: #define QBA 4 /* 22-bit Q-bus, no adaptor regs: uVAX II */
33: #endif
34:
35: #if VAX8200 || VAX8500 || VAX8800
36: #define DWBUA 5 /* BI UNIBUS adaptor: 8200/8500/8800 */
37: #endif
38:
39: /*
40: * Size of unibus memory address space in pages
41: * (also number of map registers).
42: * QBAPAGES should be 8192, but we don't need nearly that much
43: * address space, and the return from the allocation routine
44: * can accommodate at most 2047 (ubavar.h: UBA_MAXMR);
45: * QBAPAGES must be at least UBAPAGES. Choose pragmatically.
46: */
47: #define UBAPAGES 496
48: #define NUBMREG 496
49: #if defined(GATEWAY) && !defined(QNIVERT)
50: #define QBAPAGES 1024
51: #else
52: #define QBAPAGES UBAPAGES
53: #endif
54: #define UBAIOADDR 0760000 /* start of I/O page */
55: #define UBAIOPAGES 16
56:
57: #ifndef LOCORE
58: /*
59: * DWBUA hardware registers.
60: */
61: struct dwbua_regs {
62: int pad1[456]; /* actually bii regs + pad */
63: int bua_csr; /* control and status register */
64: int bua_offset; /* vector offset register */
65: int bua_fubar; /* failed UNIBUS address register */
66: int bua_bifar; /* BI failed address register */
67: int bua_udiag[5]; /* micro diagnostics (R/O) */
68: int pad2[3];
69: /* dpr[0] is for DDP; dpr's 1 through 5 are for BPD's 1 through 5 */
70: int bua_dpr[6]; /* data path registers */
71: int pad3[10];
72: int bua_bdps[20]; /* buffered data path space *//*???*/
73: int pad4[8];
74: struct pte bua_map[UBAPAGES]; /* unibus map registers */
75: int pad5[UBAIOPAGES]; /* no maps for device address space */
76: };
77:
78: #ifdef DWBUA
79: /* bua_csr */
80: #define BUACSR_ERR 0x80000000 /* composite error */
81: #define BUACSR_BIF 0x10000000 /* BI failure */
82: #define BUACSR_SSYNTO 0x08000000 /* slave sync timeout */
83: #define BUACSR_UIE 0x04000000 /* unibus interlock error */
84: #define BUACSR_IVMR 0x02000000 /* invalid map register */
85: #define BUACSR_BADBDP 0x01000000 /* bad BDP select */
86: #define BUACSR_BUAEIE 0x00100000 /* bua error interrupt enable (?) */
87: #define BUACSR_UPI 0x00020000 /* unibus power init */
88: #define BUACSR_UREGDUMP 0x00010000 /* microdiag register dump */
89: #define BUACSR_IERRNO 0x000000ff /* mask for internal errror number */
90:
91: /* bua_offset */
92: #define BUAOFFSET_MASK 0x00003e00 /* hence max offset = 15872 */
93:
94: /* bua_dpr */
95: #define BUADPR_DPSEL 0x00e00000 /* data path select (?) */
96: #define BUADPR_PURGE 0x00000001 /* purge bdp */
97:
98: /* bua_map -- in particular, those bits that are not in DW780s & DW750s */
99: #define BUAMR_IOADR 0x40000000 /* I/O address space */
100: #define BUAMR_LAE 0x04000000 /* longword access enable */
101: /* I see no reason to use either one, though ... act 6 Aug 1987 */
102:
103: #define UBA_PURGEBUA(uba, bdp) \
104: (((struct dwbua_regs *)(uba))->bua_dpr[bdp] |= BUADPR_PURGE)
105: #else
106: #define UBA_PURGEBUA(uba, bdp)
107: #endif
108:
109: /*
110: * DW780/DW750 hardware registers
111: */
112: struct uba_regs {
113: int uba_cnfgr; /* configuration register */
114: int uba_cr; /* control register */
115: int uba_sr; /* status register */
116: int uba_dcr; /* diagnostic control register */
117: int uba_fmer; /* failed map entry register */
118: int uba_fubar; /* failed UNIBUS address register */
119: int pad1[2];
120: int uba_brsvr[4];
121: int uba_brrvr[4]; /* receive vector registers */
122: int uba_dpr[16]; /* buffered data path register */
123: int pad2[480];
124: struct pte uba_map[UBAPAGES]; /* unibus map register */
125: int pad3[UBAIOPAGES]; /* no maps for device address space */
126: };
127: #endif
128:
129: #ifdef DW780
130: /* uba_cnfgr */
131: #define UBACNFGR_UBINIT 0x00040000 /* unibus init asserted */
132: #define UBACNFGR_UBPDN 0x00020000 /* unibus power down */
133: #define UBACNFGR_UBIC 0x00010000 /* unibus init complete */
134:
135: #define UBACNFGR_BITS \
136: "\40\40PARFLT\37WSQFLT\36URDFLT\35ISQFLT\34MXTFLT\33XMTFLT\30ADPDN\27ADPUP\23UBINIT\22UBPDN\21UBIC"
137:
138: /* uba_cr */
139: #define UBACR_MRD16 0x40000000 /* map reg disable bit 4 */
140: #define UBACR_MRD8 0x20000000 /* map reg disable bit 3 */
141: #define UBACR_MRD4 0x10000000 /* map reg disable bit 2 */
142: #define UBACR_MRD2 0x08000000 /* map reg disable bit 1 */
143: #define UBACR_MRD1 0x04000000 /* map reg disable bit 0 */
144: #define UBACR_IFS 0x00000040 /* interrupt field switch */
145: #define UBACR_BRIE 0x00000020 /* BR interrupt enable */
146: #define UBACR_USEFIE 0x00000010 /* UNIBUS to SBI error field IE */
147: #define UBACR_SUEFIE 0x00000008 /* SBI to UNIBUS error field IE */
148: #define UBACR_CNFIE 0x00000004 /* configuration IE */
149: #define UBACR_UPF 0x00000002 /* UNIBUS power fail */
150: #define UBACR_ADINIT 0x00000001 /* adapter init */
151:
152: /* uba_sr */
153: #define UBASR_BR7FULL 0x08000000 /* BR7 receive vector reg full */
154: #define UBASR_BR6FULL 0x04000000 /* BR6 receive vector reg full */
155: #define UBASR_BR5FULL 0x02000000 /* BR5 receive vector reg full */
156: #define UBASR_BR4FULL 0x01000000 /* BR4 receive vector reg full */
157: #define UBASR_RDTO 0x00000400 /* UNIBUS to SBI read data timeout */
158: #define UBASR_RDS 0x00000200 /* read data substitute */
159: #define UBASR_CRD 0x00000100 /* corrected read data */
160: #define UBASR_CXTER 0x00000080 /* command transmit error */
161: #define UBASR_CXTMO 0x00000040 /* command transmit timeout */
162: #define UBASR_DPPE 0x00000020 /* data path parity error */
163: #define UBASR_IVMR 0x00000010 /* invalid map register */
164: #define UBASR_MRPF 0x00000008 /* map register parity failure */
165: #define UBASR_LEB 0x00000004 /* lost error */
166: #define UBASR_UBSTO 0x00000002 /* UNIBUS select timeout */
167: #define UBASR_UBSSYNTO 0x00000001 /* UNIBUS slave sync timeout */
168:
169: #define UBASR_BITS \
170: "\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO"
171:
172: /* uba_brrvr[] */
173: #define UBABRRVR_AIRI 0x80000000 /* adapter interrupt request */
174: #define UBABRRVR_DIV 0x0000ffff /* device interrupt vector field */
175: #endif
176:
177: /* uba_dpr */
178: #ifdef DW780
179: #define UBADPR_BNE 0x80000000 /* buffer not empty - purge */
180: #define UBADPR_BTE 0x40000000 /* buffer transfer error */
181: #define UBADPR_DPF 0x20000000 /* DP function (RO) */
182: #define UBADPR_BS 0x007f0000 /* buffer state field */
183: #define UBADPR_BUBA 0x0000ffff /* buffered UNIBUS address */
184: #define UBA_PURGE780(uba, bdp) \
185: ((uba)->uba_dpr[bdp] |= UBADPR_BNE)
186: #else
187: #define UBA_PURGE780(uba, bdp)
188: #endif
189: #ifdef DW750
190: #define UBADPR_ERROR 0x80000000 /* error occurred */
191: #define UBADPR_NXM 0x40000000 /* nxm from memory */
192: #define UBADPR_UCE 0x20000000 /* uncorrectable error */
193: #define UBADPR_PURGE 0x00000001 /* purge bdp */
194: /* the DELAY is for a hardware problem */
195: #define UBA_PURGE750(uba, bdp) { \
196: ((uba)->uba_dpr[bdp] |= (UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE)); \
197: DELAY(8); \
198: }
199: #else
200: #define UBA_PURGE750(uba, bdp)
201: #endif
202:
203: /*
204: * Macros for fast buffered data path purging in time-critical routines.
205: *
206: * Too bad C pre-processor doesn't have the power of LISP in macro
207: * expansion...
208: */
209:
210: /* THIS IS WRONG, should use pointer to uba_hd */
211: #if DWBUA || DW780 || DW750
212: #define UBAPURGE(uba, bdp) { \
213: switch (cpu) { \
214: case VAX_8200: UBA_PURGEBUA(uba, bdp); break; \
215: case VAX_8600: case VAX_780: UBA_PURGE780((uba), (bdp)); break; \
216: case VAX_750: UBA_PURGE750((uba), (bdp)); break; \
217: } \
218: }
219: #else
220: #define UBAPURGE(uba, bdp)
221: #endif
222:
223:
224:
225: /* uba_mr[] */
226: #define UBAMR_MRV 0x80000000 /* map register valid */
227: #define UBAMR_BO 0x02000000 /* byte offset bit */
228: #define UBAMR_DPDB 0x01e00000 /* data path designator field */
229: #define UBAMR_SBIPFN 0x001fffff /* SBI page address field */
230:
231: #define UBAMR_DPSHIFT 21 /* shift to data path designator */
232:
233: /*
234: * Number of unibus buffered data paths and possible uba's per cpu type.
235: */
236: #define NBDP8600 15
237: #define NBDP780 15
238: #define NBDPBUA 5
239: #define NBDP750 3
240: #define NBDP730 0
241: #define MAXNBDP 15
242:
243: /*
244: * Symbolic BUS addresses for UBAs.
245: */
246:
247: #if VAX630 || VAX650
248: #define QBAMAP630 ((struct pte *)0x20088000)
249: #define QMEM630 0x30000000
250: #define QIOPAGE630 0x20000000
251: /*
252: * Q-bus control registers
253: */
254: #define QIPCR 0x1f40 /* from start of iopage */
255: /* bits in QIPCR */
256: #define Q_DBIRQ 0x0001 /* doorbell interrupt request */
257: #define Q_LMEAE 0x0020 /* local mem external access enable */
258: #define Q_DBIIE 0x0040 /* doorbell interrupt enable */
259: #define Q_AUXHLT 0x0100 /* auxiliary processor halt */
260: #define Q_DMAQPE 0x8000 /* Q22 bus address space parity error */
261: #endif
262:
263: #if VAX730
264: #define UMEM730 0xfc0000
265: #endif
266:
267: #if VAX750
268: #define UMEM750(i) (0xfc0000-(i)*0x40000)
269: #endif
270:
271: #if VAX780
272: #define UMEM780(i) (0x20100000+(i)*0x40000)
273: #endif
274:
275: #if VAX8200 /* BEWARE, argument is node, not ubanum */
276: #define UMEM8200(i) (0x20400000+(i)*0x40000)
277: #endif
278:
279: #if VAX8600
280: #define UMEMA8600(i) (0x20100000+(i)*0x40000)
281: #define UMEMB8600(i) (0x22100000+(i)*0x40000)
282: #endif
283:
284: /*
285: * Macro to offset a UNIBUS device address, often expressed as
286: * something like 0172520, by forcing it into the last 8K
287: * of UNIBUS memory space.
288: */
289: #define ubdevreg(addr) ((addr) & 017777)
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