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1.1 root 1: /* $Header: apa8.h,v 10.1 86/11/19 10:45:09 jg Exp $ */
2: /* apa8.h - Definition and macros required to access APA8
3: *
4: * Defines required to support APA8
5: *
6: * Author:
7: * Scott Bates
8: * Brown University
9: * IRIS, Box 1946
10: * Providence, RI 02912
11: *
12: *
13: * Copyright (c) 1986 Brown University
14: *
15: * Permission to use, copy, modify and distribute this software and its
16: * documentation for any purpose and without fee is hereby granted, provided
17: * that the above copyright notice appear in all copies, and that both
18: * that copyright notice and this permission notice appear in supporting
19: * documentation, and that the name of Brown University not be used in
20: * advertising or publicity pertaining to distribution of the software
21: * without specific, written prior permission. Brown University makes no
22: * representations about the suitability of this software for any purpose.
23: * It is provided "as-is" without express or implied warranty.
24: */
25:
26: #define SCREEN_BASE (0xF4D00000) /* base address for screen bitmap */
27: #define XDEV_ID XDEV_IBMAPA8 /* device id for info structure */
28:
29: #define REAL_SCREEN_WIDTH 1024 /* number of bits/line for apa8 */
30: #define REAL_SCREEN_HEIGHT 512 /* Number of lines on apa8 */
31:
32: #define X_SCREEN_WIDTH 720 /* visible bits/line for apa8 */
33: #define X_SCREEN_HEIGHT 512 /* visible lines on the screen */
34:
35: #define SCREEN_DEVICE "/dev/apa8" /* device name */
36: #define MOUSE_DEVICE "/dev/msapa8" /* device name of mouse for display */
37:
38: #define CURSOR_TYPE SOFT_CURSOR /* apa8 uses software cursor */
39:
40: #define DISPLAY_INIT() apa8_init() /* display initialization routine */
41:
42: /*
43: * Control register (short)
44: */
45:
46: #define FC 0xF0000160
47:
48: /*
49: * Data mask registers (2 each 8 bits)
50: */
51:
52: #define DM 0xF0000162
53:
54: /*
55: * Display memory for the APA8
56: */
57:
58: #define FB SCREEN_BASE
59:
60: /*
61: * bits 0-2 rotate count
62: */
63:
64: #define DCR_ROTMASK 0x0007
65:
66: /*
67: * bits 3-5 logic unit function control
68: */
69:
70: #define DCR_FCMASK 0x0038
71: #define DCR_FCOR 0x0028
72: #define DCR_FCNOR 0x0038
73: #define DCR_FCPA 0x0010
74: #define DCR_FCPB 0x0000
75: #define DCR_FCPNA 0x0030
76: #define DCR_FCPNB 0x0020
77:
78: #define DEFAULT_FUNC DCR_FCPNB
79: #define HIDDEN_FUNC DCR_FCPA
80: #define RDWR_FUNC DCR_FCPA
81:
82: /*
83: * 8-9 memory mode
84: */
85:
86: #define DCR_MEMMODE 0x0300
87: #define DCR_SWR 0x0000
88: #define DCR_ISWR 0x0100
89: #define DCR_ADWR 0x0200
90: #define DCR_AURW 0x0300
91:
92: /*
93: * 10 inc/dec of the address counter
94: */
95:
96: #define DCR_DEC 0x0400
97: #define DCR_INC ~0x0400
98:
99: /*
100: * 11 x/y stepping
101: */
102:
103: #define DCR_X 0x0800
104: #define DCR_Y ~0x0800
105:
106: /*
107: * 12 1 means block transfer
108: */
109:
110: #define DCR_BT 0x1000
111:
112: /*
113: * 13 1 means interrupt enable
114: */
115:
116: #define DCR_IEN 0x2000
117:
118: /*
119: * 14 1 means Sync enable
120: */
121:
122: #define DCR_SEN 0x4000
123:
124: /*
125: * 15 1 means Video enable
126: */
127:
128: #define DCR_VEN 0x8000
129:
130: /*
131: * Data Mask Register masks (typically are the inverse of each other)
132: */
133:
134: #define DM_A 0xFF00
135: #define DM_B 0x00FF
136:
137: #define CLEAR_DM 0x0000
138: #define DEFAULT_DM DM_B
139: #define HIDDEN_DM DM_A
140: #define RDWR_DM DM_A
141:
142: /*
143: * values for the writemask.
144: */
145:
146: #define NOMASK 0x0000
147: #define MASKBYTE2 0x00FF
148: #define MASKBYTE1 0xFF00
149:
150: /*
151: * Bitmap to BUS address offsets. All address offsets in the bitmap area
152: * must be multiplied by 2 before being used as BUS offsets.
153: */
154:
155: #define BM_TO_BUS(n) ((n) << 1)
156:
157: /*
158: * The physical bitmap addresses on the apa8 adaptor card go
159: * from 0x0000 to 0xFFFF. (the size of a short or word, 16 bits
160: * addresses these spots.
161: */
162:
163: #define MAXOFFSET 0xFFFF
164:
165: /*
166: * This is defined to be the last scan line in the hidden area.
167: * It is needed because the side affect of setting the writemask
168: * registers is the mask is also written to the bitmap.
169: */
170:
171: #define WRMASK_SCREEN_BASE \
172: (*(u_short *)(SCREEN_BASE + BM_TO_BUS(MAXOFFSET - 1)))
173:
174: #define SET_FC(control_info) { \
175: *(u_short *) FC = (u_short)(control_info); \
176: }
177:
178: #define SET_WRITEMASK(mask) { \
179: SET_FC(DCR_SEN | DCR_VEN | DCR_ISWR | DCR_X | DCR_FCOR); \
180: WRMASK_SCREEN_BASE = (u_short) mask; \
181: }
182:
183: #define SET_DATAMASK(mask) { \
184: *(u_short *)DM = (u_short) mask; \
185: }
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