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1.1 root 1: /* $Header: apa8c.h,v 10.1 86/11/19 10:45:18 jg Exp $ */
2: /* apa8c.h - Definitions and macros required to access APA8C
3: *
4: * Defines required to support APA8C
5: *
6: * Author:
7: * Scott Bates
8: * Brown University
9: * IRIS, Box 1946
10: * Providence, RI 02912
11: *
12: *
13: * Copyright (c) 1986 Brown University
14: *
15: * Permission to use, copy, modify and distribute this software and its
16: * documentation for any purpose and without fee is hereby granted, provided
17: * that the above copyright notice appear in all copies, and that both
18: * that copyright notice and this permission notice appear in supporting
19: * documentation, and that the name of Brown University not be used in
20: * advertising or publicity pertaining to distribution of the software
21: * without specific, written prior permission. Brown University makes no
22: * representations about the suitability of this software for any purpose.
23: * It is provided "as-is" without express or implied warranty.
24: */
25:
26: #define SCREEN_BASE (0xF4D20000) /* base address for screen bitmap */
27: #define XDEV_ID XDEV_IBMAPA8C /* device id for info structure */
28:
29: #define REAL_SCREEN_WIDTH 1024 /* number of bits/line for apa8c */
30: #define REAL_SCREEN_HEIGHT 512 /* Number of lines on apa8c */
31:
32: #define X_SCREEN_WIDTH 720 /* number of bits/line for apa8c display */
33: #define X_SCREEN_HEIGHT 512 /* visible lines on the screen */
34:
35: #define SCREEN_DEVICE "/dev/apa8c" /* device name */
36: #define MOUSE_DEVICE "/dev/msapa8c" /* device name of mouse for display */
37:
38: #define CURSOR_TYPE SOFT_CURSOR /* apa8c uses software cursor */
39:
40: #define DISPLAY_INIT() apa8c_init() /* display initialization routine */
41:
42: /*
43: * Control register (short)
44: */
45:
46: #define APA8C_FC 0xF0000150
47:
48: /*
49: * Data mask registers (2 each 8 bits)
50: */
51:
52: #define APA8C_DM 0xF0000152
53:
54: /*
55: * Color Plane Select register.
56: */
57:
58: #define CPS_REG 0xF0000154
59:
60: /*
61: * Foreground/ Background register.
62: */
63:
64: #define FGBG_REG 0xF0000156
65:
66: /*
67: * Video Look-up Table register.
68: */
69:
70: #define VLT_REG 0xF0000158
71:
72: /*
73: * bits 0-2 rotate count
74: */
75:
76: #define DCR_ROTMASK 0x0007
77:
78: /*
79: * bits 3-5 logic unit function control
80: */
81:
82: #define DCR_FCMASK 0x0038
83: #define DCR_FCOR 0x0028
84: #define DCR_FCNOR 0x0038
85: #define DCR_FCPA 0x0010
86: #define DCR_FCPB 0x0000
87: #define DCR_FCPNA 0x0030
88: #define DCR_FCPNB 0x0020
89:
90: #define DEFAULT_FUNC DCR_FCPNB
91: #define HIDDEN_FUNC DCR_FCPA
92: #define RDWR_FUNC DCR_FCPA
93:
94: /*
95: * 6-7 reserved
96: */
97:
98: /*
99: * 8-9 memory mode
100: */
101:
102: #define DCR_MEMMODE 0x0300
103: #define DCR_SWR 0x0000
104: #define DCR_ISWR 0x0100
105: #define DCR_ADWR 0x0200
106: #define DCR_AURW 0x0300
107:
108: /*
109: * 10 inc/dec of the address counter
110: */
111:
112: #define DCR_DEC 0x0400
113: #define DCR_INC ~0x0400
114:
115: /*
116: * 11 x/y stepping
117: */
118:
119: #define DCR_X 0x0800
120: #define DCR_Y ~0x0800
121:
122: /*
123: * 12 1 means block transfer
124: */
125:
126: #define DCR_BT 0x1000
127:
128: /*
129: * 13 1 means interrupt enable
130: */
131:
132: #define DCR_IEN 0x2000
133:
134: /*
135: * 14 1 means Sync enable
136: */
137:
138: #define DCR_SEN 0x4000
139:
140: /*
141: * 15 1 means Video enable
142: */
143:
144: #define DCR_VEN 0x8000
145:
146: /*
147: * Data Mask Register masks (typically are the
148: * inverse of each other)
149: */
150:
151: #define DM_A 0xFF00
152: #define DM_B 0x00FF
153:
154: #define CLEAR_DM 0x0000
155: #define DEFAULT_DM DM_B
156: #define HIDDEN_DM DM_A
157: #define RDWR_DM DM_A
158:
159: /*
160: * Values for the writemask.
161: */
162:
163: #define NOMASK 0x0000
164: #define MASKBYTE2 0x00FF
165: #define MASKBYTE1 0xFF00
166:
167: /*
168: * Values for the color plane select register.
169: */
170:
171: #define DEFAULT_CPS 0x001F;
172:
173: /*
174: * Values for the foreground/background register.
175: */
176:
177: #define DEFAULT_FGBG 0x00F0;
178:
179: /*
180: * Color definitions (not all colors are defined)
181: */
182:
183: #define DARK_RED 0x0100
184: #define DARK_GREEN 0x0400
185: #define DARK_BLUE 0x1000
186: #define RED 0x0200
187: #define GREEN 0x0800
188: #define BLUE 0x2000
189: #define LIGHT_RED 0x0300
190: #define LIGHT_GREEN 0x0C00
191: #define LIGHT_BLUE 0x3000
192: #define BLACK 0x0000
193: #define WHITE 0x3F00
194:
195: /*
196: * Defines to work with the Video Look-up table.
197: * foreground = 1 bits background = 0 bits
198: * (Note: In "X" zero bits are black and one bits are white)
199: */
200:
201: #define VLT_SIZE 16
202: #define FG_COLOR WHITE
203: #define BG_COLOR DARK_GREEN
204:
205: /*
206: * Bitmap to BUS address offsets. All address offsets in the bitmap area
207: * must be multiplied by 2 before being used as BUS offsets.
208: */
209:
210: #define BM_TO_BUS(n) ((n) << 1)
211:
212: /*
213: * The physical bitmap addresses on the apa8C adaptor card
214: * go from 0000 to 0xFFFF. (the size of a short or word, 16 bits addresses
215: * these spots.
216: */
217:
218: #define MAXOFFSET 0xFFFF
219:
220: /*
221: * This is defined to be the last scan line in the hidden area.
222: * It is needed because the side affect of setting the writemask registers
223: * is the mask is also written to the bitmap.
224: */
225:
226: #define WRMASK_SCREEN_BASE \
227: (*(u_short *)(SCREEN_BASE + BM_TO_BUS(MAXOFFSET - 1)))
228:
229: #define SET_APA8C_FC(control_info) { \
230: *(u_short *) APA8C_FC = (u_short)(control_info); \
231: }
232:
233: #define SET_APA8C_WRITEMASK(mask) { \
234: SET_APA8C_FC(DCR_SEN | DCR_VEN | DCR_ISWR | DCR_X | DCR_FCOR); \
235: WRMASK_SCREEN_BASE = (u_short) mask; \
236: }
237:
238: #define SET_APA8C_DATAMASK(mask) { \
239: *(u_short *)APA8C_DM = (u_short) mask; \
240: }
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