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Annotation of 43BSDTahoe/sys/tahoevba/ikreg.h, revision 1.1

1.1     ! root        1: /*
        !             2:  *     @(#)ikreg.h     7.1 (Berkeley) 5/21/88
        !             3:  */
        !             4: 
        !             5: /*
        !             6:  * IKON DR-11W register definitions.
        !             7:  */
        !             8: struct ikdevice {
        !             9:        u_short ik_csr;         /* control status register */
        !            10:        u_short ik_data;        /* data in/out register */
        !            11:        u_char  ik_mod;         /* address modifier */
        !            12:        u_char  ik_vec;         /* interrupt vector */
        !            13:        u_short ik_pulse;       /* pulse commands (w) */
        !            14:        u_short ik_fill[5];
        !            15:        u_short ik_balo;        /* low word of dma beginning address (w) */
        !            16:        u_short ik_wc;          /* dma word count */
        !            17:        u_short ik_calo;        /* low word of dma current address (r) */
        !            18:        u_short ik_fill1;
        !            19:        u_short ik_bahi;        /* high word of dma beginning address (w) */
        !            20:        u_short ik_fill2;
        !            21:        u_short ik_cahi;        /* high word of dma current address (r) */
        !            22: };
        !            23: 
        !            24: /*
        !            25:  * CSR control definitions (write-only).
        !            26:  */
        !            27: #define IKCSR_GO       0x0001          /* start dma */
        !            28: #define IKCSR_FNC1     0x0002          /* function bit 1 */
        !            29: #define IKCSR_FNC2     0x0004          /* function bit 2 */
        !            30: #define IKCSR_FNC3     0x0008          /* function bit 3 */
        !            31: /* bits 4-5 are unused */
        !            32: #define IKCSR_IENA     0x0040          /* enable/disable interrupts */
        !            33: /* bit 7 is unused */
        !            34: #define IKCSR_CYCLE    0x0100          /* force dma to cycle */
        !            35: /* bits 9-11 are unused */
        !            36: #define IKCSR_MCLR     0x1000          /* master clear board */
        !            37: #define IKCSR_RPERR    0x2000          /* reset parity error */
        !            38: #define IKCSR_RATTF    0x4000          /* reset attention */
        !            39: #define IKCSR_RDMAF    0x8000          /* reset dma completion */
        !            40: 
        !            41: /*
        !            42:  * CSR status definitions (read-only).
        !            43:  */
        !            44: #define IKCSR_DEV      0x0001          /* device flag (0 = 10083, 1 = 10077) */
        !            45: /* bits 1-3 reflect the function latch state */
        !            46: #define IKCSR_TIMO     0x0010          /* bus timeout during dma */
        !            47: #define IKCSR_BERR     0x0020          /* bus error during dma */
        !            48: /* bit 6 reflects interrupt enable state */
        !            49: #define IKCSR_READY    0x0080          /* device ready for next command */
        !            50: /* bit 8 should be 0 */
        !            51: #define IKCSR_STATC    0x0200          /* status bit C */
        !            52: #define IKCSR_STATB    0x0400          /* status bit B */
        !            53: #define IKCSR_STATA    0x0800          /* status bit A */
        !            54: #define IKCSR_PERR     0x1000          /* parity error during pi/o or dma */
        !            55: #define IKCSR_ATTN     0x2000          /* current state of attention bit */
        !            56: #define IKCSR_ATTF     0x4000          /* latched attention t-f transition */
        !            57: #define IKCSR_DMAF     0x8000          /* dma completed or terminated */
        !            58: 
        !            59: #define IKCSR_BITS \
        !            60: "\020\1DEV\2FNC1\3FNC2\4FNC3\5TIMO\6BERR\7IENA\10READY\12STATC\13STATB\14STATA\
        !            61: \15PERR\16ATTN\17ATTF\20DMAF"
        !            62: 
        !            63: /*
        !            64:  * Pulse command register definitions (write-only).
        !            65:  */
        !            66: #define IKPULSE_GO     0x0001          /* enable dma */
        !            67: #define IKPULSE_FNC2   0x0004          /* pulse function bit 1 */
        !            68: #define IKPULSE_RIENA  0x0020          /* reset IKCSR_IENA */
        !            69: #define IKPULSE_SIENA  0x0040          /* set IKCSR_IENA */
        !            70: #define IKPULSE_CYCL   0x0100          /* force dma to cycle */
        !            71: #define IKPULSE_MCLR   0x1000          /* initialize interface */
        !            72: #define IKPULSE_RPERR  0x2000          /* reset IKCSR_PERR */
        !            73: #define IKPULSE_RATTF  0x4000          /* reset IKCSR_ATTF */
        !            74: #define IKPULSE_RDMAF  0x8000          /* reset IKCSR_DMAF */

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