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1.1 root 1: /*
2: * Copyright (c) 1988 Regents of the University of California.
3: * All rights reserved.
4: *
5: * This code is derived from software contributed to Berkeley by
6: * Chris Torek.
7: *
8: * Redistribution and use in source and binary forms are permitted
9: * provided that the above copyright notice and this paragraph are
10: * duplicated in all such forms and that any documentation,
11: * advertising materials, and other materials related to such
12: * distribution and use acknowledge that the software was developed
13: * by the University of California, Berkeley. The name of the
14: * University may not be used to endorse or promote products derived
15: * from this software without specific prior written permission.
16: * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
17: * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
18: * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
19: *
20: * @(#)ka820.h 7.2 (Berkeley) 7/9/88
21: */
22:
23: /*
24: * Definitions specific to the ka820 cpu.
25: */
26:
27: #if VAX8200
28:
29: /*
30: * Device addresses.
31: */
32: #define KA820_PORTADDR 0x20088000 /* port controller */
33: #define KA820_BRAMADDR 0x20090000 /* boot ram */
34: #define KA820_EEPROMADDR 0x20098000 /* eeprom */
35: #define KA820_RX50ADDR 0x200b0000 /* rcx50 */
36: #define KA820_CLOCKADDR 0x200b8000 /* watch chip */
37:
38: /*
39: * Sizes. The port controller, RCX50, and watch chip are all one page.
40: */
41: #define KA820_BRPAGES 16 /* 8K */
42: #define KA820_EEPAGES 64 /* 32K */
43:
44: /* port controller CSR bit values */
45: #define KA820PORT_RSTHALT 0x80000000 /* restart halt */
46: #define KA820PORT_LCONS 0x40000000 /* logical console */
47: #define KA820PORT_LCONSEN 0x20000000 /* logical console enable */
48: #define KA820PORT_BIRESET 0x10000000 /* BI reset */
49: #define KA820PORT_BISTF 0x08000000 /* ??? */
50: #define KA820PORT_ENBAPT 0x04000000 /* ??? */
51: #define KA820PORT_STPASS 0x02000000 /* self test pass */
52: #define KA820PORT_RUN 0x01000000 /* run */
53: #define KA820PORT_WWPE 0x00800000 /* ??? parity even? */
54: #define KA820PORT_EVLCK 0x00400000 /* event lock */
55: #define KA820PORT_WMEM 0x00200000 /* write mem */
56: #define KA820PORT_EV4 0x00100000 /* event 4 */
57: #define KA820PORT_EV3 0x00080000 /* event 3 */
58: #define KA820PORT_EV2 0x00040000 /* event 2 */
59: #define KA820PORT_EV1 0x00020000 /* event 1 */
60: #define KA820PORT_EV0 0x00010000 /* event 0 */
61: #define KA820PORT_WWPO 0x00008000 /* ??? parity odd? */
62: #define KA820PORT_PERH 0x00004000 /* parity error H */
63: #define KA820PORT_ENBPIPE 0x00002000 /* enable? pipe */
64: #define KA820PORT_TIMEOUT 0x00001000 /* timeout */
65: #define KA820PORT_RSVD 0x00000800 /* reserved */
66: #define KA820PORT_CONSEN 0x00000400 /* console interrupt enable */
67: #define KA820PORT_CONSCLR 0x00000200 /* clear console interrupt */
68: #define KA820PORT_CONSINTR 0x00000100 /* console interrupt req */
69: #define KA820PORT_RXIE 0x00000080 /* RX50 interrupt enable */
70: #define KA820PORT_RXCLR 0x00000040 /* clear RX50 interrupt */
71: #define KA820PORT_RXIRQ 0x00000020 /* RX50 interrupt request */
72: #define KA820PORT_IPCLR 0x00000010 /* clear IP interrupt */
73: #define KA820PORT_IPINTR 0x00000008 /* IP interrupt request */
74: #define KA820PORT_CRDEN 0x00000004 /* enable CRD interrupts */
75: #define KA820PORT_CRDCLR 0x00000002 /* clear CRD interrupt */
76: #define KA820PORT_CRDINTR 0x00000001 /* CRD interrupt request */
77:
78: /* what the heck */
79: #define KA820PORT_BITS \
80: "\20\40RSTHALT\37LCONS\36LCONSEN\35BIRESET\34BISTF\33ENBAPT\32STPASS\31RUN\
81: \30WWPE\27EVLCK\26WMEM\25EV4\24EV3\23EV2\22EV1\21EV\20WWPO\17PERH\16ENBPIPE\
82: \15TIMEOUT\13CONSEN\12CONSCLR\11CONSINTR\10RXIE\7RXCLR\6RXIRQ\5IPCLR\4IPINTR\
83: \3CRDEN\2CLRCLR\1CRDINTR"
84:
85: /* clock CSR bit values, per csr */
86: #define KA820CLK_0_BUSY 0x01 /* busy (time changing) */
87: #define KA820CLK_1_GO 0x0c /* run */
88: #define KA820CLK_1_SET 0x0d /* set the time */
89: #define KA820CLK_3_VALID 0x01 /* clock is valid */
90:
91: #ifndef LOCORE
92: struct ka820port {
93: u_long csr;
94: /* that seems to be all.... */
95: };
96:
97: struct ka820clock {
98: u_char sec;
99: u_char pad0;
100: u_char secalrm;
101: u_char pad1;
102: u_char min;
103: u_char pad2;
104: u_char minalrm;
105: u_char pad3;
106: u_char hr;
107: u_char pad4;
108: u_char hralrm;
109: u_char pad5;
110: u_char dayofwk;
111: u_char pad6;
112: u_char day;
113: u_char pad7;
114: u_char mon;
115: u_char pad8;
116: u_char yr;
117: u_char pad9;
118: u_short csr0;
119: u_short csr1;
120: u_short csr2;
121: u_short csr3;
122: };
123: #endif
124: #endif
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