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Annotation of 43BSDTahoe/sys/vax/mtpr.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * Copyright (c) 1982, 1986, 1988 Regents of the University of California.
        !             3:  * All rights reserved.  The Berkeley software License Agreement
        !             4:  * specifies the terms and conditions for redistribution.
        !             5:  *
        !             6:  *     @(#)mtpr.h      7.3 (Berkeley) 5/7/88
        !             7:  */
        !             8: 
        !             9: /*
        !            10:  * VAX processor register numbers
        !            11:  */
        !            12: 
        !            13: #define        KSP     0x0             /* kernel stack pointer */
        !            14: #define        ESP     0x1             /* exec stack pointer */
        !            15: #define        SSP     0x2             /* supervisor stack pointer */
        !            16: #define        USP     0x3             /* user stack pointer */
        !            17: #define        ISP     0x4             /* interrupt stack pointer */
        !            18: #define        P0BR    0x8             /* p0 base register */
        !            19: #define        P0LR    0x9             /* p0 length register */
        !            20: #define        P1BR    0xa             /* p1 base register */
        !            21: #define        P1LR    0xb             /* p1 length register */
        !            22: #define        SBR     0xc             /* system segment base register */
        !            23: #define        SLR     0xd             /* system segment length register */
        !            24: #define        PCBB    0x10            /* process control block base */
        !            25: #define        SCBB    0x11            /* system control block base */
        !            26: #define        IPL     0x12            /* interrupt priority level */
        !            27: #define        ASTLVL  0x13            /* async. system trap level */
        !            28: #define        SIRR    0x14            /* software interrupt request */
        !            29: #define        SISR    0x15            /* software interrupt summary */
        !            30: #if VAX8200
        !            31: #define        IPIR    0x16            /* interprocessor interrupt register */
        !            32: #endif
        !            33: #if VAX750 || VAX730
        !            34: #define        MCSR    0x17            /* machine check status register */
        !            35: #endif
        !            36: #define        ICCS    0x18            /* interval clock control */
        !            37: #define        NICR    0x19            /* next interval count */
        !            38: #define        ICR     0x1a            /* interval count */
        !            39: #if VAX8600 || VAX8200 || VAX780 || VAX750 || VAX730
        !            40: #define        TODR    0x1b            /* time of year (day) */
        !            41: #endif
        !            42: #if VAX750 || VAX730
        !            43: #define        CSRS    0x1c            /* console storage receive status register */
        !            44: #define        CSRD    0x1d            /* console storage receive data register */
        !            45: #define        CSTS    0x1e            /* console storage transmit status register */
        !            46: #define        CSTD    0x1f            /* console storage transmit data register */
        !            47: #endif
        !            48: #define        RXCS    0x20            /* console receiver control and status */
        !            49: #define        RXDB    0x21            /* console receiver data buffer */
        !            50: #define        TXCS    0x22            /* console transmitter control and status */
        !            51: #define        TXDB    0x23            /* console transmitter data buffer */
        !            52: #if VAX8200 || VAX750 || VAX730
        !            53: #define        TBDR    0x24            /* translation buffer disable register */
        !            54: #define        CADR    0x25            /* cache disable register */
        !            55: #define        MCESR   0x26            /* machine check error summary register */
        !            56: #endif
        !            57: #if VAX750 || VAX730
        !            58: #define        CAER    0x27            /* cache error */
        !            59: #endif
        !            60: #define        ACCS    0x28            /* accelerator control and status */
        !            61: #if VAX780
        !            62: #define        ACCR    0x29            /* accelerator maintenance */
        !            63: #endif
        !            64: #if VAX8200 || VAX780
        !            65: #define        WCSA    0x2c            /* WCS address */
        !            66: #define        WCSD    0x2d            /* WCS data */
        !            67: #endif
        !            68: #if VAX8200
        !            69: #define        WCSL    0x2e            /* WCS load */
        !            70: #endif
        !            71: #if VAX8600 || VAX780
        !            72: #define        SBIFS   0x30            /* SBI fault and status */
        !            73: #define        SBIS    0x31            /* SBI silo */
        !            74: #define        SBISC   0x32            /* SBI silo comparator */
        !            75: #define        SBIMT   0x33            /* SBI maintenance */
        !            76: #define        SBIER   0x34            /* SBI error register */
        !            77: #define        SBITA   0x35            /* SBI timeout address */
        !            78: #define        SBIQC   0x36            /* SBI quadword clear */
        !            79: #endif
        !            80: #if VAX750 || VAX730 || VAX630
        !            81: #define        IUR     0x37            /* init unibus (Qbus on 630) register */
        !            82: #endif
        !            83: #define        MAPEN   0x38            /* memory management enable */
        !            84: #define        TBIA    0x39            /* translation buffer invalidate all */
        !            85: #define        TBIS    0x3a            /* translation buffer invalidate single */
        !            86: #if VAX750 || VAX730
        !            87: #define        TB      0x3b            /* translation buffer */
        !            88: #endif
        !            89: #if VAX780
        !            90: #define        MBRK    0x3c            /* micro-program breakpoint */
        !            91: #endif
        !            92: #define        PMR     0x3d            /* performance monitor enable */
        !            93: #define        SID     0x3e            /* system identification */
        !            94: #if VAX8600 || VAX8200
        !            95: #define TBCHK  0x3f            /* Translation Buffer Check */
        !            96: #endif
        !            97: #if VAX8600
        !            98: #define PAMACC 0x40            /* PAMM access */
        !            99: #define PAMLOC 0x41            /* PAMM location */
        !           100: #define CSWP   0x42            /* Cache sweep */
        !           101: #define MDECC  0x43            /* MBOX data ecc register */
        !           102: #define MENA   0x44            /* MBOX error enable register */
        !           103: #define MDCTL  0x45            /* MBOX data control register */
        !           104: #define MCCTL  0x46            /* MBOX mcc control register */
        !           105: #define MERG   0x47            /* MBOX error generator register */
        !           106: #define CRBT   0x48            /* Console reboot */
        !           107: #define DFI    0x49            /* Diag fault insertion register */
        !           108: #define EHSR   0x4a            /* Error handling status register */
        !           109: #define STXCS  0x4c            /* Console block storage C/S */
        !           110: #define STXDB  0x4d            /* Console block storage D/B */
        !           111: #define ESPA   0x4e            /* EBOX scratchpad address */
        !           112: #define ESPD   0x4f            /* EBOX sratchpad data */
        !           113: #endif
        !           114: #if VAX8200
        !           115: #define        RXCS1   0x50            /* receive csr, console line 1 */
        !           116: #define        RXDB1   0x51            /* receive data buffer, console line 1 */
        !           117: #define        TXCS1   0x52            /* transmit csr, console line 1 */
        !           118: #define        TXDB1   0x53            /* transmit data buffer, console line 1 */
        !           119: #define        RXCS2   0x54            /* etc */
        !           120: #define        RXDB2   0x55
        !           121: #define        TXCS2   0x56
        !           122: #define        TXDB2   0x57
        !           123: #define        RXCS3   0x58
        !           124: #define        RXDB3   0x59
        !           125: #define        TXCS3   0x5a
        !           126: #define        TXDB3   0x5b
        !           127: #define        RXCD    0x5c            /* receive console data register */
        !           128: #define        CACHEX  0x5d            /* cache invalidate register */
        !           129: #define        BINID   0x5e            /* VAXBI node ID register */
        !           130: #define        BISTOP  0x5f            /* VAXBI stop register */
        !           131: #endif

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