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1.1 root 1: /*
2: * Copyright (c) 1982, 1986 Regents of the University of California.
3: * All rights reserved. The Berkeley software License Agreement
4: * specifies the terms and conditions for redistribution.
5: *
6: * @(#)ubareg.h 7.4 (Berkeley) 5/14/88
7: */
8:
9: /*
10: * VAX UNIBUS adapter registers
11: */
12:
13: /*
14: * "UNIBUS" adaptor types.
15: * This code is used for both UNIBUSes and Q-buses
16: * with different types of adaptors.
17: * Definition of a type includes support code for that type.
18: */
19: #if VAX780 || VAX8600
20: #define DW780 1 /* has adaptor regs, sr: 780/785/8600 */
21: #endif
22:
23: #if VAX750
24: #define DW750 2 /* has adaptor regs, no sr: 750, 730 */
25: #endif
26:
27: #if VAX730
28: #define DW730 3 /* has adaptor regs, no sr: 750, 730 */
29: #endif
30:
31: #if VAX630
32: #define QBA 4 /* 22-bit Q-bus, no adaptor regs: uVAX II */
33: #endif
34:
35: #if VAX8200 || VAX8500 || VAX8800
36: #define DWBUA 5 /* BI UNIBUS adaptor: 8200/8500/8800 */
37: #endif
38:
39: /*
40: * Size of unibus memory address space in pages
41: * (also number of map registers).
42: * QBAPAGES should be 8192, but umem needs to be expanded.
43: */
44: #define UBAPAGES 496
45: #define NUBMREG 496
46: #define QBAPAGES UBAPAGES /* for now; should be 8192 */
47: #define UBAIOADDR 0760000 /* start of I/O page */
48: #define UBAIOPAGES 16
49:
50: #ifndef LOCORE
51: /*
52: * DWBUA hardware registers.
53: */
54: struct dwbua_regs {
55: int pad1[456]; /* actually bii regs + pad */
56: int bua_csr; /* control and status register */
57: int bua_offset; /* vector offset register */
58: int bua_fubar; /* failed UNIBUS address register */
59: int bua_bifar; /* BI failed address register */
60: int bua_udiag[5]; /* micro diagnostics (R/O) */
61: int pad2[3];
62: /* dpr[0] is for DDP; dpr's 1 through 5 are for BPD's 1 through 5 */
63: int bua_dpr[6]; /* data path registers */
64: int pad3[10];
65: int bua_bdps[20]; /* buffered data path space *//*???*/
66: int pad4[8];
67: struct pte bua_map[UBAPAGES]; /* unibus map registers */
68: int pad5[UBAIOPAGES]; /* no maps for device address space */
69: };
70:
71: #ifdef DWBUA
72: /* bua_csr */
73: #define BUACSR_ERR 0x80000000 /* composite error */
74: #define BUACSR_BIF 0x10000000 /* BI failure */
75: #define BUACSR_SSYNTO 0x08000000 /* slave sync timeout */
76: #define BUACSR_UIE 0x04000000 /* unibus interlock error */
77: #define BUACSR_IVMR 0x02000000 /* invalid map register */
78: #define BUACSR_BADBDP 0x01000000 /* bad BDP select */
79: #define BUACSR_BUAEIE 0x00100000 /* bua error interrupt enable (?) */
80: #define BUACSR_UPI 0x00020000 /* unibus power init */
81: #define BUACSR_UREGDUMP 0x00010000 /* microdiag register dump */
82: #define BUACSR_IERRNO 0x000000ff /* mask for internal errror number */
83:
84: /* bua_offset */
85: #define BUAOFFSET_MASK 0x00003e00 /* hence max offset = 15872 */
86:
87: /* bua_dpr */
88: #define BUADPR_DPSEL 0x00e00000 /* data path select (?) */
89: #define BUADPR_PURGE 0x00000001 /* purge bdp */
90:
91: /* bua_map -- in particular, those bits that are not in DW780s & DW750s */
92: #define BUAMR_IOADR 0x40000000 /* I/O address space */
93: #define BUAMR_LAE 0x04000000 /* longword access enable */
94: /* I see no reason to use either one, though ... act 6 Aug 1987 */
95:
96: #define UBA_PURGEBUA(uba, bdp) \
97: (((struct dwbua_regs *)(uba))->bua_dpr[bdp] |= BUADPR_PURGE)
98: #else
99: #define UBA_PURGEBUA(uba, bdp)
100: #endif
101:
102: /*
103: * DW780/DW750 hardware registers
104: */
105: struct uba_regs {
106: int uba_cnfgr; /* configuration register */
107: int uba_cr; /* control register */
108: int uba_sr; /* status register */
109: int uba_dcr; /* diagnostic control register */
110: int uba_fmer; /* failed map entry register */
111: int uba_fubar; /* failed UNIBUS address register */
112: int pad1[2];
113: int uba_brsvr[4];
114: int uba_brrvr[4]; /* receive vector registers */
115: int uba_dpr[16]; /* buffered data path register */
116: int pad2[480];
117: struct pte uba_map[UBAPAGES]; /* unibus map register */
118: int pad3[UBAIOPAGES]; /* no maps for device address space */
119: };
120: #endif
121:
122: #ifdef DW780
123: /* uba_cnfgr */
124: #define UBACNFGR_UBINIT 0x00040000 /* unibus init asserted */
125: #define UBACNFGR_UBPDN 0x00020000 /* unibus power down */
126: #define UBACNFGR_UBIC 0x00010000 /* unibus init complete */
127:
128: #define UBACNFGR_BITS \
129: "\40\40PARFLT\37WSQFLT\36URDFLT\35ISQFLT\34MXTFLT\33XMTFLT\30ADPDN\27ADPUP\23UBINIT\22UBPDN\21UBIC"
130:
131: /* uba_cr */
132: #define UBACR_MRD16 0x40000000 /* map reg disable bit 4 */
133: #define UBACR_MRD8 0x20000000 /* map reg disable bit 3 */
134: #define UBACR_MRD4 0x10000000 /* map reg disable bit 2 */
135: #define UBACR_MRD2 0x08000000 /* map reg disable bit 1 */
136: #define UBACR_MRD1 0x04000000 /* map reg disable bit 0 */
137: #define UBACR_IFS 0x00000040 /* interrupt field switch */
138: #define UBACR_BRIE 0x00000020 /* BR interrupt enable */
139: #define UBACR_USEFIE 0x00000010 /* UNIBUS to SBI error field IE */
140: #define UBACR_SUEFIE 0x00000008 /* SBI to UNIBUS error field IE */
141: #define UBACR_CNFIE 0x00000004 /* configuration IE */
142: #define UBACR_UPF 0x00000002 /* UNIBUS power fail */
143: #define UBACR_ADINIT 0x00000001 /* adapter init */
144:
145: /* uba_sr */
146: #define UBASR_BR7FULL 0x08000000 /* BR7 receive vector reg full */
147: #define UBASR_BR6FULL 0x04000000 /* BR6 receive vector reg full */
148: #define UBASR_BR5FULL 0x02000000 /* BR5 receive vector reg full */
149: #define UBASR_BR4FULL 0x01000000 /* BR4 receive vector reg full */
150: #define UBASR_RDTO 0x00000400 /* UNIBUS to SBI read data timeout */
151: #define UBASR_RDS 0x00000200 /* read data substitute */
152: #define UBASR_CRD 0x00000100 /* corrected read data */
153: #define UBASR_CXTER 0x00000080 /* command transmit error */
154: #define UBASR_CXTMO 0x00000040 /* command transmit timeout */
155: #define UBASR_DPPE 0x00000020 /* data path parity error */
156: #define UBASR_IVMR 0x00000010 /* invalid map register */
157: #define UBASR_MRPF 0x00000008 /* map register parity failure */
158: #define UBASR_LEB 0x00000004 /* lost error */
159: #define UBASR_UBSTO 0x00000002 /* UNIBUS select timeout */
160: #define UBASR_UBSSYNTO 0x00000001 /* UNIBUS slave sync timeout */
161:
162: #define UBASR_BITS \
163: "\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO"
164:
165: /* uba_brrvr[] */
166: #define UBABRRVR_AIRI 0x80000000 /* adapter interrupt request */
167: #define UBABRRVR_DIV 0x0000ffff /* device interrupt vector field */
168: #endif
169:
170: /* uba_dpr */
171: #ifdef DW780
172: #define UBADPR_BNE 0x80000000 /* buffer not empty - purge */
173: #define UBADPR_BTE 0x40000000 /* buffer transfer error */
174: #define UBADPR_DPF 0x20000000 /* DP function (RO) */
175: #define UBADPR_BS 0x007f0000 /* buffer state field */
176: #define UBADPR_BUBA 0x0000ffff /* buffered UNIBUS address */
177: #define UBA_PURGE780(uba, bdp) \
178: ((uba)->uba_dpr[bdp] |= UBADPR_BNE)
179: #else
180: #define UBA_PURGE780(uba, bdp)
181: #endif
182: #ifdef DW750
183: #define UBADPR_ERROR 0x80000000 /* error occurred */
184: #define UBADPR_NXM 0x40000000 /* nxm from memory */
185: #define UBADPR_UCE 0x20000000 /* uncorrectable error */
186: #define UBADPR_PURGE 0x00000001 /* purge bdp */
187: /* the DELAY is for a hardware problem */
188: #define UBA_PURGE750(uba, bdp) { \
189: ((uba)->uba_dpr[bdp] |= (UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE)); \
190: DELAY(8); \
191: }
192: #else
193: #define UBA_PURGE750(uba, bdp)
194: #endif
195:
196: /*
197: * Macros for fast buffered data path purging in time-critical routines.
198: *
199: * Too bad C pre-processor doesn't have the power of LISP in macro
200: * expansion...
201: */
202:
203: /* THIS IS WRONG, should use pointer to uba_hd */
204: #if DWBUA || DW780 || DW750
205: #define UBAPURGE(uba, bdp) { \
206: switch (cpu) { \
207: case VAX_8200: UBA_PURGEBUA(uba, bdp); break; \
208: case VAX_8600: case VAX_780: UBA_PURGE780((uba), (bdp)); break; \
209: case VAX_750: UBA_PURGE750((uba), (bdp)); break; \
210: } \
211: }
212: #else
213: #define UBAPURGE(uba, bdp)
214: #endif
215:
216:
217:
218: /* uba_mr[] */
219: #define UBAMR_MRV 0x80000000 /* map register valid */
220: #define UBAMR_BO 0x02000000 /* byte offset bit */
221: #define UBAMR_DPDB 0x01e00000 /* data path designator field */
222: #define UBAMR_SBIPFN 0x001fffff /* SBI page address field */
223:
224: #define UBAMR_DPSHIFT 21 /* shift to data path designator */
225:
226: /*
227: * Number of unibus buffered data paths and possible uba's per cpu type.
228: */
229: #define NBDP8600 15
230: #define NBDP780 15
231: #define NBDPBUA 5
232: #define NBDP750 3
233: #define NBDP730 0
234: #define MAXNBDP 15
235:
236: /*
237: * Symbolic BUS addresses for UBAs.
238: */
239:
240: #if VAX630
241: #define QBAMAP630 ((struct pte *)0x20088000)
242: #define QMEM630 0x30000000
243: #define QIOPAGE630 0x20000000
244: /*
245: * Q-bus control registers
246: */
247: #define QIPCR 0x1f40 /* from start of iopage */
248: /* bits in QIPCR */
249: #define Q_DBIRQ 0x0001 /* doorbell interrupt request */
250: #define Q_LMEAE 0x0020 /* local mem external access enable */
251: #define Q_DBIIE 0x0040 /* doorbell interrupt enable */
252: #define Q_AUXHLT 0x0100 /* auxiliary processor halt */
253: #define Q_DMAQPE 0x8000 /* Q22 bus address space parity error */
254: #endif
255:
256: #if VAX730
257: #define UMEM730 0xfc0000
258: #endif
259:
260: #if VAX750
261: #define UMEM750(i) (0xfc0000-(i)*0x40000)
262: #endif
263:
264: #if VAX780
265: #define UMEM780(i) (0x20100000+(i)*0x40000)
266: #endif
267:
268: #if VAX8200 /* BEWARE, argument is node, not ubanum */
269: #define UMEM8200(i) (0x20400000+(i)*0x40000)
270: #endif
271:
272: #if VAX8600
273: #define UMEMA8600(i) (0x20100000+(i)*0x40000)
274: #define UMEMB8600(i) (0x22100000+(i)*0x40000)
275: #endif
276:
277: /*
278: * Macro to offset a UNIBUS device address, often expressed as
279: * something like 0172520, by forcing it into the last 8K
280: * of UNIBUS memory space.
281: */
282: #define ubdevreg(addr) ((addr) & 017777)
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