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1.1 root 1: /*
2: * PCI config typedefs.
3: */
4:
5: #define PCI_NUM_BASE_ADDRESS 6
6:
7: /*
8: * Status word as bitfields.
9: */
10: typedef struct {
11: unsigned short rsvd1:6,
12: fastBtb:1, // fast back-to-back
13: dataParity:1,
14: devSelTiming:2,
15: sigTargetAbort:1,
16: rcvTargetAbort:1,
17: rcvMasterAbort:1,
18: sigSystemError:1,
19: detParityError:1;
20: } pciStatusBits;
21:
22: /*
23: * For looking at status as either bitfields or a word.
24: */
25: typedef union {
26: pciStatusBits bits;
27: unsigned short word;
28: } pciConfStatus;
29:
30: /*
31: * PCI configuration header struct, "software" view.
32: */
33: typedef struct {
34: unsigned short deviceId;
35: unsigned short vendorId;
36: pciConfStatus status;
37: unsigned short command;
38: unsigned revId:8,
39: classApi:8,
40: subclass:8,
41: classCode:8;
42: unsigned char bist;
43: unsigned char headerType;
44: unsigned char latencyTimer;
45: unsigned char cacheLineSize;
46: unsigned baseAddress[PCI_NUM_BASE_ADDRESS];
47: unsigned baseAddressExp0;
48: unsigned baseAddressExp1;
49: unsigned expansionRomBase;
50: unsigned rsvd1;
51: unsigned rsvd2;
52: unsigned char maxLat;
53: unsigned char minGnt;
54: unsigned char intrPin;
55: unsigned char intrLine;
56: } pciConfHeader;
57:
58: /*
59: * Individual registers indices, the "hardware" view.
60: */
61: #define PCI_DEV_AND_VENDOR_ID 0
62: #define PCI_DEV_ID(reg) ((reg & 0xffff0000) >> 16)
63: #define PCI_VENDOR_ID(reg) (reg & 0x0000ffff)
64:
65: #define PCI_STATUS_AND_COMMAND 1
66: #define PCI_STATUS(reg) ((reg & 0xffff0000) >> 16)
67: #define PCI_COMMAND(reg) (reg & 0x0000ffff)
68:
69: #define PCI_CLASS_AND_REV 2
70: #define PCI_CLASS_CODE(reg) ((reg & 0xff000000) >> 24)
71: #define PCI_SUBCLASS(reg) ((reg & 0x00ff0000) >> 16)
72: #define PCI_CLASS_API(reg) ((reg & 0x0000ff00) >> 8)
73: #define PCI_REV_ID(reg) (reg & 0x000000ff)
74:
75: #define PCI_BIST_HDR_LAT_LS 3
76: #define PCI_BIST(reg) ((reg & 0xff000000) >> 24)
77: #define PCI_HDR_TYPE(reg) ((reg & 0x00ff0000) >> 16)
78: #define PCI_LATENCY(reg) ((reg & 0x0000ff00) >> 8)
79: #define PCI_CACHE_LINE_SIZE(reg) (reg & 0x000000ff)
80:
81: #define PCI_BASE_ADDRESS_0 4
82: #define PCI_BASE_ADDRESS_1 5
83: #define PCI_BASE_ADDRESS_2 6
84: #define PCI_BASE_ADDRESS_3 7
85: #define PCI_BASE_ADDRESS_4 8
86: #define PCI_BASE_ADDRESS_5 9
87: #define PCI_BASE_ADDRESS_EXP0 0xa
88: #define PCI_BASE_ADDRESS_EXP1 0xb
89: #define PCI_ROM_BASE_ADDRESS 0xc
90: #define PCI_RSVD1 0xd
91: #define PCI_RSVD2 0xe
92:
93: #define PCI_BUS_AND_INTR 0xf
94: #define PCI_MAX_LAT(reg) ((reg & 0xff000000) >> 24)
95: #define PCI_MAX_GNT(reg) ((reg & 0x00ff0000) >> 16)
96: #define PCI_INTR_PIN(reg) ((reg & 0x0000ff00) >> 8)
97: #define PCI_INTR_LINE(reg) (reg & 0x000000ff)
98:
99: #define PCI_BUS_AND_INTR_REG(lat, gnt, pin, line) \
100: ((lat << 24) | (gnt << 16) | (pin << 8) | line)
101:
102: /*
103: * Command register bits.
104: */
105: #define PCI_COMMAND_IO_ENABLE 0x0001
106: #define PCI_COMMAND_MEM_ENABLE 0x0002
107: #define PCI_COMMAND_MASTER_ENABLE 0x0004
108: #define PCI_COMMAND_SPECIAL 0x0008
109: #define PCI_COMMAND_MWI 0x0010
110: #define PCI_COMMAND_PALETTE_SNOOP 0x0020
111: #define PCI_COMMAND_PARITY_ERROR 0x0040
112: #define PCI_COMMAND_WAIT_ENABLE 0x0080
113: #define PCI_COMMAND_SYSTEM_ERR 0x0100
114: #define PCI_COMMAND_FAST_BTB 0x0200
115:
116: /*
117: * headerType bits.
118: */
119: #define HEADER_TYPE_MULTI_FCN 0x80 /* 1 --> multifunction */
120:
121: /*
122: * bist (built in self test) bits.
123: */
124: #define PCI_BIST_CAPABLE 0x80
125: #define PCI_BIST_START 0x40
126: #define PCI_BIST_CODE_MASK 0x0f
127: /*
128: * Limits.
129: */
130: /* #define PCI_NUM_BUSSES 256 */
131: #define PCI_NUM_BUSSES 1 /* for now... */
132: #define PCI_NUM_DEVICES_1 32 /* per bus, method 1 */
133: #define PCI_NUM_DEVICES_2 16 /* per bus, method 2 */
134: #define PCI_NUM_FUNCTIONS 8 /* per target */
135:
136: /*
137: * Vendor ID meaning "no device here".
138: */
139: #define VENDOR_ID_NONE 0xffff
140:
141: /*
142: * Class codes.
143: */
144: #define PCI_CLASS_OLD 0
145: #define PCI_CLASS_MASS_STORAGE 1
146: #define PCI_CLASS_NETWORK 2
147: #define PCI_CLASS_DISPLAY 3
148: #define PCI_CLASS_MULTIMEDIA 4
149: #define PCI_CLASS_MEMORY 5
150: #define PCI_CLASS_BRIDGE 6
151: #define PCI_CLASS_OTHER 0xff
152:
153: /*
154: * Subclass codes.
155: */
156:
157: #define PCI_SUBCLASS0_NON_VGA 0x00
158: #define PCI_SUBCLASS0_VGA 0x01
159:
160: #define PCI_SUBCLASS1_SCSI 0x00
161: #define PCI_SUBCLASS1_IDE 0x01
162: #define PCI_SUBCLASS1_FLOPPY 0x02
163: #define PCI_SUBCLASS1_IPI 0x03
164: #define PCI_SUBCLASS1_OTHER 0x80
165:
166: #define PCI_SUBCLASS2_ENET 0x00
167: #define PCI_SUBCLASS2_TR 0x01
168: #define PCI_SUBCLASS2_FDDI 0x02
169: #define PCI_SUBCLASS2_OTHER 0x80
170:
171: #define PCI_SUBCLASS3_VGA 0x00
172: #define PCI_SUBCLASS3_XGA 0x01
173: #define PCI_SUBCLASS3_OTHER 0x80
174:
175: #define PCI_SUBCLASS4_VIDEO 0x00
176: #define PCI_SUBCLASS4_AUDIO 0x01
177: #define PCI_SUBCLASS4_OTHER 0x02
178:
179: #define PCI_SUBCLASS5_RAM 0x00
180: #define PCI_SUBCLASS5_FLASH 0x01
181: #define PCI_SUBCLASS5_OTHER 0x80
182:
183: #define PCI_SUBCLASS6_HOST_PCI 0x00
184: #define PCI_SUBCLASS6_PCI_ISA 0x01
185: #define PCI_SUBCLASS6_PCI_EISA 0x02
186: #define PCI_SUBCLASS6_PCI_MICRO 0x03
187: #define PCI_SUBCLASS6_PCI_PCI 0x04
188: #define PCI_SUBCLASS6_PCI_MCIA 0x05
189: #define PCI_SUBCLASS6_OTHER 0x80
190:
191: /*
192: * Constants for parsing base address registers.
193: */
194: #define PCI_BASE_IO_BIT 0x01
195: #define PCI_BASE_PREFETCHABLE 0x08
196: #define PCI_BASE_MEM_TYPE 0x06
197: #define PCI_BASE_IO(value) (value & 0xfffffffc)
198: #define PCI_BASE_MEMORY(value) (value & 0xfffffff0)
199: #define PCI_MEM_TYPE_ANY_32 0x00
200: #define PCI_MEM_TYPE_LOW_1MEG 0x02
201: #define PCI_MEM_TYPE_ANY_64 0x04
202:
203: /*
204: * The actual ports we read and write to get all of the above using
205: * Configuration mechanism 1.
206: */
207: #define PCI_CONF_ADDRS_PORT 0xcf8
208: #define PCI_CONF_DATA_PORT 0xcfc
209:
210: /*
211: * Ports and constants used for Configuration mechanism 2.
212: *
213: * FIXME - what is the width of PCI_FORWARD_PORT?
214: */
215: #define PCI_CSE_PORT 0xcf8 /* Configuration Space Enable */
216: /* (8-bit) */
217: #define PCI_FORWARD_PORT 0xcfa /* basically, the bus number */
218: #define PCI_CONFIG_BASE 0xc000 /* base of mapped device register */
219: /* space */
220:
221: /*
222: * Fields in PCI_CSE_PORT
223: */
224: #define PCI_CSE_SPECIAL 0x01
225: #define PCI_CSE_KEY_MAP 0xf0
226: #define PCI_CSE_KEY_NORMAL 0x00
227:
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