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1.1 root 1: /* CONFIDENTIAL
2: * Copyright (c) 1993 by NeXT Computer, Inc as an unpublished work.
3: * All rights reserved.
4: *
5: * QVisionModes.c -- support for QVision driver modes.
6: *
7: * Author: Derek B Clegg 21 May 1993
8: * Based on work by Joe Pasqua, 30 September 1992.
9: */
10: #include "QVisionModes.h"
11:
12: /* Tables of register values for the supported modes. */
13:
14: /* QVision 1024 x 768 x 8 (QVision mode 0x38) @ 60Hz.
15: */
16: static const struct QVisionMode Mode_38_60Hz = {
17: "QVision[1024 x 768 x 8] @ 60Hz", QVisionAdapter, NO,
18:
19: /* Control register 1 value (63CA). */
20: 0x03,
21:
22: /* DAC command register 1 value (13C8). */
23: 0x40,
24:
25: /* Overflow register 1 value (3CF.42). */
26: 0x00,
27:
28: /* Overflow register 2 value (3CF.51). */
29: 0x00,
30:
31: /* Standard VGA data. */
32: {
33: 0xe3, /* Miscellaneous output register value (3C2). */
34: 0x00, /* Feature control register value (3DA). */
35:
36: /* Sequencer register values. */
37: { 0x01, 0x01, 0xff, 0x00, 0x0e },
38:
39: /* CRTC register values (3D5.00 - 3D5.18). */
40: {
41: 0x9b, 0x7f, 0x7f, 0x9e, 0x87, 0x17, 0x31, 0xf5, 0x00, 0x60, 0x00,
42: 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x94, 0xff, 0x80, 0x00, 0xff,
43: 0x31, 0xe3, 0xff,
44: },
45:
46: /* Attribute controller register values (3C0.00 - 3C0.13). */
47: {
48: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09,
49: 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00,
50: },
51:
52: /* Graphics controller register values (3CF.00 - 3CF.08). */
53: { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
54: }
55: };
56:
57: /* QVision 1024 x 768 x 8 (QVision mode 0x38) @ 66Hz.
58: */
59: static const struct QVisionMode Mode_38_66Hz = {
60: "QVision[1024 x 768 x 8] @ 66Hz", QVisionAdapter, NO,
61:
62: /* Control register 1 value (63CA). */
63: 0x03,
64:
65: /* DAC command register 1 value (13C8). */
66: 0x40,
67:
68: /* Overflow register 1 value (3CF.42). */
69: 0x00,
70:
71: /* Overflow register 2 value (3CF.51). */
72: 0x00,
73:
74: /* Standard VGA data. */
75: {
76: 0x27, /* Miscellaneous output register value (3C2). */
77: 0x00, /* Feature control register value (3DA). */
78:
79: /* Sequencer register values. */
80: { 0x01, 0x01, 0xff, 0x00, 0x0e },
81:
82: /* CRTC register values (3D5.00 - 3D5.18). */
83: {
84: 0xa1, 0x7f, 0x7f, 0x84, 0x85, 0x9b, 0x2e, 0xf5, 0x00, 0x60, 0x00,
85: 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x8b, 0xff, 0x80, 0x00, 0xff,
86: 0x2e, 0xe3, 0xff,
87: },
88:
89: /* Attribute controller register values (3C0.00 - 3C0.13). */
90: {
91: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09,
92: 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00,
93: },
94:
95: /* Graphics controller register values (3CF.00 - 3CF.08). */
96: { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
97: }
98: };
99:
100: /* QVision 1024 x 768 x 8 (QVision mode 0x38) @ 72Hz.
101: */
102: static const struct QVisionMode Mode_38_72Hz = {
103: "QVision[1024 x 768 x 8] @ 72Hz", QVisionAdapter, NO,
104:
105: /* Control register 1 value (63CA). */
106: 0x03,
107:
108: /* DAC command register 1 value (13C8). */
109: 0x40,
110:
111: /* Overflow register 1 value (3CF.42). */
112: 0x00,
113:
114: /* Overflow register 2 value (3CF.51). */
115: 0x00,
116:
117: /* Standard VGA data. */
118: {
119: 0x2b, /* Miscellaneous output register value (3C2). */
120: 0x00, /* Feature control register value (3DA). */
121:
122: /* Sequencer register values. */
123: { 0x01, 0x01, 0xff, 0x00, 0x0e },
124:
125: /* CRTC register values (3D5.00 - 3D5.18). */
126: {
127: 0x9e, 0x7f, 0x7f, 0x81, 0x83, 0x93, 0x1e, 0xf1, 0x00, 0x60, 0x00,
128: 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x83, 0xff, 0x80, 0x00, 0xff,
129: 0x1e, 0xe3, 0xff,
130: },
131:
132: /* Attribute controller register values (3C0.00 - 3C0.13). */
133: {
134: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09,
135: 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00,
136: },
137:
138: /* Graphics controller register values (3CF.00 - 3CF.08). */
139: { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
140: }
141: };
142:
143: /* Orion12 1024 x 768 x 8 (QVision mode 0x38) @ 76Hz.
144: */
145: static const struct QVisionMode Mode_38_76Hz = {
146: "Orion12[1024 x 768 x 8] @ 76Hz", Orion12Adapter, YES,
147:
148: /* Control register 1 value (63CA). */
149: 0x03,
150:
151: /* DAC command register 1 value (13C8). */
152: 0x40,
153:
154: /* Overflow register 1 value (3CF.42). */
155: 0x00,
156:
157: /* Overflow register 2 value (3CF.51). */
158: 0x00,
159:
160: /* Standard VGA data. */
161: {
162: 0x33, /* Miscellaneous output register value (3C2). */
163: 0x00, /* Feature control register value (3DA). */
164:
165: /* Sequencer register values. */
166: { 0x01, 0x01, 0xff, 0x00, 0x0e },
167:
168: /* CRTC register values (3D5.00 - 3D5.18). */
169: {
170: 0x9c, 0x7f, 0x7f, 0x1f, 0x85, 0x10, 0x26, 0xf5, 0x00, 0x60, 0x00,
171: 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x8b, 0xff, 0x80, 0x00, 0xff,
172: 0x26, 0xe3, 0xff,
173: },
174:
175: /* Attribute controller register values (3C0.00 - 3C0.13). */
176: {
177: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09,
178: 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00,
179: },
180:
181: /* Graphics controller register values (3CF.00 - 3CF.08). */
182: { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
183: }
184: };
185:
186: /* QVision 640 x 400 x 24 (QVision mode 0x4E) @ 60Hz.
187: */
188: static const struct QVisionMode Mode_4E_60Hz = {
189: "QVision[640 x 400 x 24] @ 60Hz", QVisionAdapter, NO,
190:
191: /* Control register 1 value (63CA). */
192: 0x07,
193:
194: /* DAC command register 1 value (13C8). */
195: 0x00,
196:
197: /* Overflow register 1 value (3CF.42). */
198: 0x01,
199:
200: /* Overflow register 2 value (3CF.51). */
201: 0x08,
202:
203: /* Standard VGA data. */
204: {
205: 0x6f, /* Miscellaneous output register value (3C2). */
206: 0x00, /* Feature control register value (3DA). */
207:
208: /* Sequencer register values. */
209: { 0x01, 0x01, 0xff, 0x00, 0x0e },
210:
211: /* CRTC register values (3D5.00 - 3D5.18). */
212: {
213: 0x5f, 0x4f, 0x50, 0x81, 0x53, 0x9f, 0x0b, 0x3e, 0x00, 0x40, 0x00,
214: 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x84, 0x8f, 0x40, 0x00, 0x95,
215: 0x03, 0xe3, 0xff,
216: },
217:
218: /* Attribute controller register values (3C0.00 - 3C0.13). */
219: {
220: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09,
221: 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00,
222: },
223:
224: /* Graphics controller register values (3CF.00 - 3CF.08). */
225: { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
226: }
227: };
228:
229: /* QVision 640 x 400 x 24 (QVision mode 0x4E) @ 70Hz.
230: */
231: static const struct QVisionMode Mode_4E_70Hz = {
232: "QVision[640 x 400 x 24] @ 70Hz", QVisionAdapter, NO,
233:
234: /* Control register 1 value (63CA). */
235: 0x07,
236:
237: /* DAC command register 1 value (13C8). */
238: 0x00,
239:
240: /* Overflow register 1 value (3CF.42). */
241: 0x01,
242:
243: /* Overflow register 2 value (3CF.51). */
244: 0x28,
245:
246: /* Standard VGA data. */
247: {
248: 0x6f, /* Miscellaneous output register value (3C2). */
249: 0x00, /* Feature control register value (3DA). */
250:
251: /* Sequencer register values. */
252: { 0x01, 0x01, 0xff, 0x00, 0x0e },
253:
254: /* CRTC register values (3D5.00 - 3D5.18). */
255: {
256: 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f, 0x00, 0x40, 0x00,
257: 0x00, 0x00, 0x00, 0x00, 0x00, 0x9c, 0x8e, 0x8f, 0x40, 0x00, 0x96,
258: 0xb9, 0xe3, 0xff,
259: },
260:
261: /* Attribute controller register values (3C0.00 - 3C0.13). */
262: {
263: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09,
264: 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00,
265: },
266:
267: /* Graphics controller register values (3CF.00 - 3CF.08). */
268: { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
269: }
270: };
271:
272: /* QVision 800 x 600 x 15 (QVision mode 0x3F) @ 60Hz.
273: */
274: static const struct QVisionMode Mode_3F_60Hz = {
275: "QVision[800 x 600 x 15] @ 60Hz", QVisionAdapter, NO,
276:
277: /* Control register 1 value (63CA). */
278: 0x05,
279:
280: /* DAC command register 1 value (13C8). */
281: 0x20,
282:
283: /* Overflow register 1 value (3CF.42). */
284: 0x00,
285:
286: /* Overflow register 2 value (3CF.51). */
287: 0x20,
288:
289: /* Standard VGA data. */
290: {
291: 0xf3, /* Miscellaneous output register value (3C2). */
292: 0x00, /* Feature control register value (3DA). */
293:
294: /* Sequencer register values. */
295: { 0x01, 0x01, 0xff, 0x00, 0x0e },
296:
297: /* CRTC register values (3D5.00 - 3D5.18). */
298: {
299: 0x7f, 0x63, 0x64, 0x80, 0x68, 0x19, 0x73, 0xf0, 0x00, 0x60, 0x00,
300: 0x00, 0x00, 0x00, 0x00, 0x00, 0x58, 0x8c, 0x57, 0xc8, 0x00, 0x58,
301: 0x72, 0xe3, 0xff,
302: },
303:
304: /* Attribute controller register values (3C0.00 - 3C0.13). */
305: {
306: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09,
307: 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00,
308: },
309:
310: /* Graphics controller register values (3CF.00 - 3CF.08). */
311: { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
312: }
313: };
314:
315: /* QVision 800 x 600 x 15 (QVision mode 0x3F) @ 72Hz.
316: */
317: static const struct QVisionMode Mode_3F_72Hz = {
318: "QVision[800 x 600 x 15] @ 72Hz", QVisionAdapter, NO,
319:
320: /* Control register 1 value (63CA). */
321: 0x05,
322:
323: /* DAC command register 1 value (13C8). */
324: 0x20,
325:
326: /* Overflow register 1 value (3CF.42). */
327: 0x00,
328:
329: /* Overflow register 2 value (3CF.51). */
330: 0x20,
331:
332: /* Standard VGA data. */
333: {
334: 0x23, /* Miscellaneous output register value (3C2). */
335: 0x00, /* Feature control register value (3DA). */
336:
337: /* Sequencer register values. */
338: { 0x01, 0x01, 0xff, 0x00, 0x0e },
339:
340: /* CRTC register values (3D5.00 - 3D5.18). */
341: {
342: 0x84, 0x63, 0x64, 0x83, 0x6b, 0x1c, 0x73, 0xf0, 0x00, 0x60, 0x00,
343: 0x00, 0x00, 0x00, 0x00, 0x00, 0x58, 0x5c, 0x57, 0xc8, 0x00, 0x58,
344: 0x72, 0xe3, 0xff,
345: },
346:
347: /* Attribute controller register values (3C0.00 - 3C0.13). */
348: {
349: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09,
350: 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00,
351: },
352:
353: /* Graphics controller register values (3CF.00 - 3CF.08). */
354: { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
355: }
356: };
357:
358: /* Orion12 1280 x 1024 x 8 (QVision mode 0x3A) @ 68Hz.
359: */
360: static const struct QVisionMode Mode_3A_68Hz = {
361: "Orion12[1280 x 1024 x 8] @ 68Hz", Orion12Adapter, YES,
362:
363: /* Control register 1 value (63CA). */
364: 0x03,
365:
366: /* DAC command register 1 value (13C8). */
367: 0x40,
368:
369: /* Overflow register 1 value (3CF.42). */
370: 0x81,
371:
372: /* Overflow Register 2 values (3CF.51h). */
373: 0xe8,
374:
375: /* Standard VGA data. */
376: {
377: 0x23, /* Miscellaneous output register values (3C2). */
378: 0x00, /* Feature control register value (3DA). */
379:
380: /* Sequencer register values. */
381: { 0x01, 0x01, 0xff, 0x00, 0x0e },
382:
383: /* CRTC register values (3D5.00 - 3D5.18h) */
384: {
385: 0xcf, 0x9f, 0x9f, 0x12, 0xa4, 0x19, 0x2e, 0x5a, 0x00, 0x60, 0x00,
386: 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x8b, 0xff, 0x00, 0x00, 0xff,
387: 0x2e, 0xe3, 0xff,
388: },
389:
390: /* Attribute controller register values (3C0.00 - 3C0.13). */
391: {
392: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09,
393: 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00,
394: },
395:
396: /* Graphics controller register values (3CF.00 - 3CF.08). */
397: { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
398: }
399: };
400:
401: /* Orion 1024 x 768 x 15 (QVision mode 0x40) @ 60Hz.
402: */
403: static const struct QVisionMode Mode_40_60Hz = {
404: "Orion[1024 x 768 x 15] @ 60Hz", OrionAdapter, NO,
405:
406: /* Control register 1 value (63CA). */
407: 0x05,
408:
409: /* DAC command register 1 value (13C8). */
410: 0x20,
411:
412: /* Overflow register 1 value (3CF.42). */
413: 0x01,
414:
415: /* Overflow register 2 value (3CF.51). */
416: 0x00,
417:
418: /* Standard VGA data. */
419: {
420: 0xe3, /* Miscellaneous output register values (3C2). */
421: 0x00, /* Feature control register value (3DA). */
422:
423: /* Sequencer register values. */
424: { 0x01, 0x01, 0xff, 0x00, 0x0e },
425:
426: /* CRTC register values (3D5.00 - 3D5.18). */
427: {
428: 0x9b, 0x7f, 0x7f, 0x9e, 0x87, 0x17, 0x31, 0xf5, 0x00, 0x60, 0x00,
429: 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x94, 0xff, 0x00, 0x00, 0xff,
430: 0x31, 0xe3, 0xff,
431: },
432:
433: /* Attribute controller register values (3C0.00 - 3C0.13). */
434: {
435: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09,
436: 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00,
437: },
438:
439: /* Graphics controller register values (3CF.00 - 3CF.08). */
440: { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
441: }
442: };
443:
444: /* Orion 1024 x 768 x 15 (QVision mode 0x40) @ 72Hz.
445: */
446: static const struct QVisionMode Mode_40_72Hz = {
447: "Orion[1024 x 768 x 15] @ 72Hz", OrionAdapter, NO,
448:
449: /* Control register 1 value (63CA). */
450: 0x05,
451:
452: /* DAC command register 1 value (13C8). */
453: 0x20,
454:
455: /* Overflow register 1 value (3CF.42). */
456: 0x01,
457:
458: /* Overflow register 2 value (3CF.51). */
459: 0x00,
460:
461: /* Standard VGA data. */
462: {
463: 0x2b, /* Miscellaneous output register value (3C2). */
464: 0x00, /* Feature control register value (3DA). */
465:
466: /* Sequencer register values. */
467: { 0x01, 0x01, 0xff, 0x00, 0x0e },
468:
469: /* CRTC register values (3D5.00 - 3D5.18). */
470: {
471: 0x9e, 0x7f, 0x7f, 0x81, 0x83, 0x93, 0x1e, 0xf1, 0x00, 0x60, 0x00,
472: 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x83, 0xff, 0x00, 0x00, 0xff,
473: 0x1e, 0xe3, 0xff,
474: },
475:
476: /* Attribute controller register values (3C0.00 - 3C0.13). */
477: {
478: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09,
479: 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00,
480: },
481:
482: /* Graphics controller register values (3CF.00 - 3CF.08). */
483: { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
484: }
485: };
486:
487: /* Orion 640 x 480 x 24 (QVision mode 0x4F) @ 60Hz.
488: */
489: static const struct QVisionMode Mode_4F_60Hz = {
490: "Orion[640 x 480 x 24] @ 60Hz", OrionAdapter, NO,
491:
492: /* Control register 1 values (63CA). */
493: 0x07,
494:
495: /* DAC command register 1 value (13C8). */
496: 0x00,
497:
498: /* Overflow register 1 value (3CF.42). */
499: 0x02,
500:
501: /* Overflow register 2 value (3CF.51). */
502: 0x08,
503:
504: /* Standard VGA data. */
505: {
506: 0xef, /* Miscellaneous output register value (3C2). */
507: 0x00, /* Feature control register value (3DA). */
508:
509: /* Sequencer register values. */
510: { 0x01, 0x01, 0xff, 0x00, 0x0e },
511:
512: /* CRTC register values (3D5.00 - 3D5.18). */
513: {
514: 0x5f, 0x4f, 0x50, 0x81, 0x53, 0x9f, 0x0b, 0x3e, 0x00, 0x40, 0x00,
515: 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0x8c, 0xdf, 0x00, 0x00, 0xe5,
516: 0x03, 0xe3, 0xff,
517: },
518:
519: /* Attribute controller register values (3C0.00 - 3C0.13). */
520: {
521: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09,
522: 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00,
523: },
524:
525: /* Graphics controller register values (3CF.00 - 3CF.08). */
526: { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
527: }
528: };
529:
530: const IODisplayInfo QVisionModeTable[] = {
531: /* 0: QVision 1024 x 768 x 8 (Mode 0x38) @ 60Hz. */
532: {
533: 1024, 768, 1024, 1024, 60, 0,
534: IO_8BitsPerPixel, IO_OneIsWhiteColorSpace, "WWWWWWWW",
535: 0, (void *)&Mode_38_60Hz,
536: },
537:
538: /* 1: QVision 1024 x 768 x 8 (Mode 0x38) @ 66Hz. */
539: {
540: 1024, 768, 1024, 1024, 66, 0,
541: IO_8BitsPerPixel, IO_OneIsWhiteColorSpace, "WWWWWWWW",
542: 0, (void *)&Mode_38_66Hz,
543: },
544:
545: /* 2: QVision 1024 x 768 x 8 (Mode 0x38) @ 72Hz. */
546: {
547: 1024, 768, 1024, 1024, 72, 0,
548: IO_8BitsPerPixel, IO_OneIsWhiteColorSpace, "WWWWWWWW",
549: 0, (void *)&Mode_38_72Hz,
550: },
551:
552: /* 3: Orion12 1024 x 768 x 8 (Mode 0x38) @ 76Hz. */
553: {
554: 1024, 768, 1024, 1024, 76, 0,
555: IO_8BitsPerPixel, IO_OneIsWhiteColorSpace, "WWWWWWWW",
556: 0, (void *)&Mode_38_76Hz,
557: },
558:
559: /* 4: QVision 640 x 400 x 24 (Mode 0x4E) @ 60Hz. */
560: {
561: 640, 400, 640, 2560, 60, 0,
562: IO_24BitsPerPixel, IO_RGBColorSpace,"--------RRRRRRRRGGGGGGGGBBBBBBBB",
563: 0, (void *)&Mode_4E_60Hz,
564: },
565:
566: /* 5: QVision 640 x 400 x 24 (Mode 0x4E) @ 70Hz. */
567: {
568: 640, 400, 640, 2560, 70, 0,
569: IO_24BitsPerPixel, IO_RGBColorSpace,"--------RRRRRRRRGGGGGGGGBBBBBBBB",
570: 0, (void *)&Mode_4E_70Hz,
571: },
572:
573: /* 6: QVision 800 x 600 x 15 (QVision mode 0x3F) @ 60Hz. */
574: {
575: 800, 600, 800, 1600, 60, 0,
576: IO_15BitsPerPixel, IO_RGBColorSpace, "-RRRRRGGGGGBBBBB",
577: 0, (void *)&Mode_3F_60Hz,
578: },
579:
580: /* 7: QVision 800 x 600 x 15 (Mode 0x3F) @ 72Hz. */
581: {
582: 800, 600, 800, 1600, 72, 0,
583: IO_15BitsPerPixel, IO_RGBColorSpace, "-RRRRRGGGGGBBBBB",
584: 0, (void *)&Mode_3F_72Hz,
585: },
586:
587: /* 8: Orion12 1280 x 1024 x 8 (Mode 0x3A) @ 68Hz. */
588: {
589: 1280, 1024, 2048, 2048, 68, 0,
590: IO_8BitsPerPixel, IO_OneIsWhiteColorSpace, "WWWWWWWW",
591: 0, (void *)&Mode_3A_68Hz,
592: },
593:
594: /* 9: Orion 1024 x 768 x 15 (Mode 0x40) @ 60Hz. */
595: {
596: 1024, 768, 1024, 2048, 60, 0,
597: IO_15BitsPerPixel, IO_RGBColorSpace, "-RRRRRGGGGGBBBBB",
598: 0, (void *)&Mode_40_60Hz,
599: },
600:
601: /* 10: Orion 1024 x 768 x 15 (Mode 0x40) @ 72Hz. */
602: {
603: 1024, 768, 1024, 2048, 72, 0,
604: IO_15BitsPerPixel, IO_RGBColorSpace, "-RRRRRGGGGGBBBBB",
605: 0, (void *)&Mode_40_72Hz,
606: },
607:
608: /* 11: Orion 640 x 480 x 24 (Mode 0x4F) @ 60Hz. */
609: {
610: 640, 480, 1024, 4096, 60, 0,
611: IO_24BitsPerPixel, IO_RGBColorSpace,"--------RRRRRRRRGGGGGGGGBBBBBBBB",
612: 0, (void *)&Mode_4F_60Hz,
613: },
614:
615: /* 8-bit color modes */
616: /* 12: QVision 1024 x 768 x 8 (Mode 0x38) @ 60Hz. */
617: {
618: 1024, 768, 1024, 1024, 60, 0,
619: IO_8BitsPerPixel, IO_RGBColorSpace, "PPPPPPPP",
620: 0, (void *)&Mode_38_60Hz,
621: },
622:
623: /* 13: QVision 1024 x 768 x 8 (Mode 0x38) @ 66Hz. */
624: {
625: 1024, 768, 1024, 1024, 66, 0,
626: IO_8BitsPerPixel, IO_RGBColorSpace, "PPPPPPPP",
627: 0, (void *)&Mode_38_66Hz,
628: },
629:
630: /* 14: QVision 1024 x 768 x 8 (Mode 0x38) @ 72Hz. */
631: {
632: 1024, 768, 1024, 1024, 72, 0,
633: IO_8BitsPerPixel, IO_RGBColorSpace, "PPPPPPPP",
634: 0, (void *)&Mode_38_72Hz,
635: },
636:
637: /* 15: Orion12 1024 x 768 x 8 (Mode 0x38) @ 76Hz. */
638: {
639: 1024, 768, 1024, 1024, 76, 0,
640: IO_8BitsPerPixel, IO_RGBColorSpace, "PPPPPPPP",
641: 0, (void *)&Mode_38_76Hz,
642: },
643:
644: /* 16: Orion12 1280 x 1024 x 8 (Mode 0x3A) @ 68Hz. */
645: {
646: 1280, 1024, 2048, 2048, 68, 0,
647: IO_8BitsPerPixel, IO_RGBColorSpace, "PPPPPPPP",
648: 0, (void *)&Mode_3A_68Hz,
649: },
650: };
651:
652: const int QVisionModeTableCount =
653: sizeof(QVisionModeTable)/sizeof(QVisionModeTable[0]);
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