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1.1 root 1: /* CONFIDENTIAL
2: * Copyright (c) 1993 by NeXT Computer, Inc as an unpublished work.
3: * All rights reserved.
4: *
5: * S3Modes.h -- internal definitions for S3 driver.
6: *
7: * History
8: * Thu Sep 15 15:16:43 PDT 1994, James C. Lee
9: * Added AT&T 20C505 DAC support
10: * Author: Derek B Clegg 21 May 1993
11: * Based on work by Peter Graffagnino, 31 January 1993.
12: */
13:
14: #ifndef S3MODES_H__
15: #define S3MODES_H__
16:
17: #import <objc/objc.h>
18: #import <mach/mach.h>
19: #import <driverkit/displayDefs.h>
20: #import <driverkit/i386/ioPorts.h>
21: #import "vgaModes.h"
22:
23: enum S3AdapterType {
24: UnknownAdapter, S3_805, S3_928,
25: };
26: typedef enum S3AdapterType S3AdapterType;
27:
28: enum DACtype {
29: UnknownDAC,
30: ATT20C491, /* AT&T 20C491 or Sierra SC15025. */
31: Bt484, /* BrookTree 484. */
32: Bt485, /* BrookTree 485. */
33: Bt485A, /* BrookTree 485A. */
34: ATT20C505 /* AT&T 20C505 */
35: };
36: typedef enum DACtype DACtype;
37:
38: #define ONE_MEGABYTE (1 << 20)
39: #define TWO_MEGABYTES (2 << 20)
40: #define THREE_MEGABYTES (3 << 20)
41: #define FOUR_MEGABYTES (4 << 20)
42:
43: #define S3_XCRTC_COUNT 48
44: #define S3_MODE_COUNT 10 /* Maximum refresh rate/mode control pairs. */
45:
46: struct S3ModeControl {
47: unsigned char refreshRate;
48: unsigned char modeControl; /* 0x3D4:42 */
49: };
50:
51: struct S3Mode {
52: const char *name; /* The name of this mode. */
53: S3AdapterType adapter; /* The adapter required for this mode. */
54: unsigned long memSize; /* The memory necessary for this mode. */
55:
56: struct S3ModeControl modeControl[S3_MODE_COUNT];
57: unsigned char advFuncCntl; /* 0x4AE8 */
58: unsigned char xcrtc[S3_XCRTC_COUNT];
59: VGAMode vgaData;
60: };
61: typedef struct S3Mode S3Mode;
62:
63: extern const IODisplayInfo S3_805_ModeTable[];
64: extern const int S3_805_ModeTableCount;
65: extern const int S3_805_defaultMode;
66: extern const IODisplayInfo S3_928_ModeTable[];
67: extern const int S3_928_ModeTableCount;
68: extern const int S3_928_defaultMode;
69:
70: /* Definitions for the S3 registers that we use. */
71:
72: #define S3_EXTENDED_REGISTER_MAX 0x7F
73:
74: /* Indexes for S3 registers. */
75:
76: #define S3_CHIP_ID_INDEX 0x30 /* Chip ID/REV register. */
77: #define S3_CHIP_ID_MASK 0xF0
78: #define S3_CHIP_ID_805 0xA0
79: #define S3_CHIP_ID_928 0x90
80: #define S3_REVISION_MASK 0x0F
81:
82: #define S3_MEM_CNFG_INDEX 0x31 /* Memory configuration register. */
83:
84: #define S3_BKWD_2 0x33 /* Backward compatibility register. */
85:
86: #define S3_CRTR_LOCK_INDEX 0x35 /* CRT register lock register. */
87:
88: #define S3_CONFG_REG1_INDEX 0x36 /* Configuration 1 register. */
89: #define S3_CONFG_REG2_INDEX 0x37 /* Configuration 2 register. */
90: #define S3_BUS_SELECT_MASK 0x03
91: #define S3_EISA_BUS 0x00
92: #define S3_LOCAL_BUS 0x01
93: #define S3_ISA_BUS 0x03
94: #define S3_MEM_SIZE_MASK 0xC0
95: #define S3_4_MEG 0
96: #define S3_3_MEG (2 << 5)
97: #define S3_2_MEG (4 << 5)
98: #define S3_1_MEG (6 << 5)
99: #define S3_HALF_MEG (7 << 5)
100:
101: /* Lock registers */
102:
103: #define S3_REG_LOCK1 0x38 /* Register lock 1 register. */
104: #define S3_LOCK1_KEY 0x48
105: #define S3_REG_LOCK2 0x39 /* Register lock 2 register. */
106: #define S3_LOCK2_KEY 0xA0
107:
108: #define S3_DT_EX_POS 0x3B /* Data transfer execute position
109: register. */
110: #define S3_IL_RTSTART 0x3C /* Interlace retrace start register. */
111:
112: /* System Control Registers */
113:
114: #define S3_SYS_CNFG 0x40 /* System configuration register. */
115: #define S3_8514_ACCESS_MASK 0x01
116: #define S3_8514_ENABLE_ACCESS 0x01
117: #define S3_8514_DISABLE_ACCESS 0x00
118: #define S3_WRITE_POST_MASK 0x08
119: #define S3_WRITE_POST_ENABLE 0x08
120: #define S3_WRITE_POST_DISABLE 0x00
121:
122: #define S3_MODE_CTL 0x42 /* Mode control register. */
123: #define S3_EXT_MODE 0x43 /* Extended mode register. */
124: #define S3_HGC_MODE 0x45 /* Hardware graphics cursor mode
125: register. */
126: #define S3_ENB_485 (1 << 5)/* Cursor control enable for Brooktree
127: Bt485 DAC. */
128:
129: /* System Extension Registers. */
130:
131: #define S3_EX_SCTL_1 0x50 /* Extended system control 1
132: register. */
133:
134: #define S3_EX_MCTL_1 0x53 /* Extended memory control 1
135: register. */
136: #define S3_MMIO_ACCESS_MASK 0x10
137: #define S3_ENABLE_MMIO_ACCESS 0x10
138: #define S3_DISABLE_MMIO_ACCESS 0x00
139:
140: #define S3_EX_MCTL_2 0x54 /* Extended memory control 2
141: register. */
142: #define S3_PREFETCH_CTRL_MASK 0x07
143: #define S3_PREFETCH_MAX 0x07
144:
145: #define S3_EX_DAC_CT 0x55 /* Extended video DAC control
146: register. */
147: #define S3_DAC_R_SEL_MASK 0x03 /* Mask for extension bits of the
148: RS[1:0] signals for video DAC
149: addressing. */
150: #define S3_ENB_SID 0x80 /* Enable external SID operation. */
151: #define S3_HWGC_EXOP 0x20 /* Hardware cursor external operation
152: mode. */
153:
154: #define S3_LAW_CTL 0x58 /* Linear address window control
155: register. */
156: #define S3_LAW_SIZE_MASK 0x03
157: #define S3_LAW_SIZE_64K 0x00
158: #define S3_LAW_SIZE_1M 0x01
159: #define S3_LAW_SIZE_2M 0x02
160: #define S3_LAW_SIZE_4M 0x03
161: #define S3_PREFETCH_MASK 0x04
162: #define S3_ENABLE_PREFETCH 0x04
163: #define S3_DISABLE_PREFETCH 0x00
164: #define S3_LAW_ENABLE_MASK 0x10
165: #define S3_ENABLE_LAW 0x10
166: #define S3_DISABLE_LAW 0x00
167:
168: #define S3_LAW_POS_HI 0x59 /* Linear address window position
169: registers. */
170: #define S3_LAW_POS_LO 0x5A
171:
172: #define S3_GOUT_PORT 0x5C /* General output port register. */
173:
174: #define S3_EXT_H_OVF 0x5D /* Extended horizontal overflow
175: register. */
176: #define S3_EXT_V_OVF 0x5E /* Extended vertical overflow
177: register. */
178:
179: /* Enhanced Command Registers */
180:
181: #define S3_ADVFUNC_CNTL 0x4AE8 /* Advanced function control
182: register. */
183: #define S3_GP_STAT 0x9AE8 /* Graphics processor status
184: register. */
185: #define S3_GP_BUSY_MASK (1 << 9)
186:
187: /* DAC registers. */
188:
189: #define RS_00 0x3C8
190: #define RS_01 0x3C9
191: #define RS_02 0x3C6
192: #define RS_03 0x3C7
193:
194: /* Register read/write helpers. */
195:
196: /* Set an index on `port' to `index', and return the byte read from `port + 1'.
197: */
198: static inline int rread(int port, int index)
199: {
200: outb(port, index);
201: return (inb(port + 1));
202: }
203:
204: /* Use outw to send index and data together.
205: */
206: static inline void rwrite(int port, int index, int value)
207: {
208: outw(port, index | (value << 8));
209: }
210:
211: /* Read-modify-write.
212: */
213: static inline void rrmw(int port, int index, int protect, int value)
214: {
215: unsigned int u = rread(port, index);
216: rwrite(port,index, (u & protect) | value);
217: }
218:
219: static inline void
220: S3_unlockRegisters(void)
221: {
222: rwrite(VGA_CRTC_INDEX, S3_REG_LOCK1, S3_LOCK1_KEY);
223: rwrite(VGA_CRTC_INDEX, S3_REG_LOCK2, S3_LOCK2_KEY);
224: }
225:
226: static inline void
227: S3_lockRegisters(void)
228: {
229: rwrite(VGA_CRTC_INDEX, S3_REG_LOCK1, 0);
230: rwrite(VGA_CRTC_INDEX, S3_REG_LOCK2, 0);
231: }
232:
233: #endif /* S3MODES_H__ */
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