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1.1 root 1: /* CONFIDENTIAL
2: * Copyright (c) 1993 by NeXT Computer, Inc as an unpublished work.
3: * All rights reserved.
4: *
5: * S3_805_Modes.c -- Modes for the S3 805.
6: *
7: * Author: Derek B Clegg 21 May 1993
8: */
9: #import "S3Modes.h"
10:
11: /* Tables of register values for the supported modes. */
12:
13: /* S3 805 800 x 600 x 15 (S3 mode 0x114).
14: */
15: static const S3Mode S3_805_800x600x15 = {
16: "S3_805[800 x 600 x 15]", S3_805, ONE_MEGABYTE,
17:
18: /* Mode control. */
19: { 60, 0x0A },
20:
21: /* Advanced function control register (0x4AE8). */
22: 0x03,
23:
24: /* Extra CRTC registers. */
25: {
26: 0x31, 0x8D, 0x32, 0x10, 0x33, 0x00, 0x34, 0x00, 0x35, 0x00,
27: 0x3A, 0x95, 0x3B, 0xF8, 0x3C, 0x00, 0x40, 0x50, 0x43, 0x00,
28: 0x50, 0x90, 0x51, 0x00, 0x53, 0x00, 0x54, 0x18, 0x56, 0x00,
29: 0x57, 0x00, 0x5C, 0x35, 0x5D, 0x00, 0x5E, 0x00, 0x5F, 0x00,
30: 0x60, 0x2F, 0x61, 0x81, 0x62, 0x92, 0x63, 0x92,
31: },
32:
33: /* Standard VGA registers. */
34: {
35: 0xEF,
36: 0x00,
37: { 0x01, 0x01, 0x0F, 0x00, 0x0E },
38: {
39: 0xFC, 0xC7, 0xC7, 0x9F, 0xD3, 0x8D, 0x70, 0xF0, 0x00, 0x60,
40: 0x00, 0x00, 0x00, 0x00, 0x00, 0xC8, 0x58, 0x8C, 0x57, 0xC8,
41: 0x00, 0x58, 0x6F, 0xA3, 0xFF,
42: },
43: {
44: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, 0x38, 0x39,
45: 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x01, 0x00, 0x0F, 0x00,
46: },
47: {
48: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF,
49: },
50: }
51: };
52:
53: /* S3 805 1024 x 768 x 8 (S3 mode 0x205).
54: */
55: static const S3Mode S3_805_1024x768x8 = {
56: "S3_805[1024 x 768 x 8]", S3_805, ONE_MEGABYTE,
57:
58: /* Mode control. */
59: { 60, 0x0D, 70, 0x0E, 72, 0x05 },
60:
61: /* Advanced function control register (0x4AE8). */
62: 0x07, /* 0x4AE8 */
63:
64: /* Extra CRTC registers. */
65: {
66: 0x31, 0x8D, 0x32, 0x10, 0x33, 0x00, 0x34, 0x00, 0x35, 0x00,
67: 0x3A, 0x95, 0x3B, 0x9D, 0x3C, 0x9F, 0x40, 0x51, 0x43, 0x00,
68: 0x50, 0x00, 0x51, 0x00, 0x53, 0x00, 0x54, 0x48, 0x56, 0x00,
69: 0x57, 0x00, 0x5C, 0x3D, 0x5D, 0x00, 0x5E, 0x00, 0x5F, 0x00,
70: 0x60, 0x2F, 0x61, 0x81, 0x62, 0x00, 0x63, 0x00,
71: },
72:
73: /* Standard VGA registers. */
74: {
75: 0x2F,
76: 0x00,
77: { 0x01, 0x01, 0x0F, 0x00, 0x0E },
78: {
79: 0xA3, 0x7F, 0x80, 0x86, 0x84, 0x95, 0x25, 0xF5, 0x00, 0x60,
80: 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x87, 0xFF, 0x80,
81: 0x60, 0xFF, 0x21, 0xEB, 0xFF,
82: },
83: {
84: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, 0x38, 0x39,
85: 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x01, 0x00, 0x0F, 0x00,
86: },
87: {
88: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF,
89: },
90: }
91: };
92:
93: const IODisplayInfo S3_805_ModeTable[] = {
94: {
95: /* S3 805; 800 x 600 x 15 @ 60Hz. */
96: 800, 600, 800, 1600, 60, 0, IO_15BitsPerPixel,
97: IO_RGBColorSpace, "-RRRRRGGGGGBBBBB", 0, (void *)&S3_805_800x600x15,
98: },
99: {
100: /* S3 805; 1024 x 768 x 8 @ 60Hz. */
101: 1024, 768, 1024, 1024, 60, 0, IO_8BitsPerPixel,
102: IO_RGBColorSpace, "PPPPPPPP", 0, (void *)&S3_805_1024x768x8,
103: },
104: {
105: /* S3 805; 1024 x 768 x 8 @ 70Hz. */
106: 1024, 768, 1024, 1024, 70, 0, IO_8BitsPerPixel,
107: IO_RGBColorSpace, "PPPPPPPP", 0, (void *)&S3_805_1024x768x8,
108: },
109: {
110: /* S3 805; 1024 x 768 x 8 @ 72Hz. */
111: 1024, 768, 1024, 1024, 72, 0, IO_8BitsPerPixel,
112: IO_RGBColorSpace, "PPPPPPPP", 0, (void *)&S3_805_1024x768x8,
113: },
114: {
115: /* S3 805; 1024 x 768 x 8 @ 60Hz. */
116: 1024, 768, 1024, 1024, 60, 0, IO_8BitsPerPixel,
117: IO_OneIsWhiteColorSpace, "WWWWWWWW", 0, (void *)&S3_805_1024x768x8,
118: },
119: {
120: /* S3 805; 1024 x 768 x 8 @ 70Hz. */
121: 1024, 768, 1024, 1024, 70, 0, IO_8BitsPerPixel,
122: IO_OneIsWhiteColorSpace, "WWWWWWWW", 0, (void *)&S3_805_1024x768x8,
123: },
124: {
125: /* S3 805; 1024 x 768 x 8 @ 72Hz. */
126: 1024, 768, 1024, 1024, 72, 0, IO_8BitsPerPixel,
127: IO_OneIsWhiteColorSpace, "WWWWWWWW", 0, (void *)&S3_805_1024x768x8,
128: },
129: };
130:
131: const int S3_805_ModeTableCount =
132: (sizeof(S3_805_ModeTable) / sizeof(S3_805_ModeTable[0]));
133:
134: const int S3_805_defaultMode = 0;
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