![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to S3_928_Modes.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [NeXTSTEP 3.3 examples] / Examples / DriverKit / S3 / S3_reloc.tproj|
Return to S3_928_Modes.c CVS log | Up to [NeXTSTEP 3.3 examples] / Examples / DriverKit / S3 / S3_reloc.tproj |
1.1 root 1: /* CONFIDENTIAL
2: * Copyright (c) 1993 by NeXT Computer, Inc as an unpublished work.
3: * All rights reserved.
4: *
5: * S3_928_Modes.c -- Modes for the S3 928.
6: *
7: * Author: Derek B Clegg 21 May 1993
8: */
9: #import "S3Modes.h"
10:
11: /* Tables of register values for the supported modes. */
12:
13: /* S3 928 800 x 600 x 15 (S3 mode 0x114 or 0x214).
14: */
15: static const S3Mode S3_928_800x600x15 = {
16: "S3_928[800 x 600 x 15]", S3_928, TWO_MEGABYTES,
17:
18: /* Mode control. */
19: { 60, 0x02 },
20:
21: /* Advanced function control register (0x4AE8). */
22: 0x07,
23:
24: /* Extra CRTC registers. */
25: {
26: 0x31, 0x8D, 0x32, 0x10, 0x33, 0x20, 0x34, 0x00, 0x35, 0x00,
27: 0x3A, 0x95, 0x3B, 0xF8, 0x3C, 0x19, 0x40, 0x50, 0x43, 0x00,
28: 0x50, 0x10, 0x51, 0x50, 0x53, 0x00, 0x54, 0x00, 0x56, 0x00,
29: 0x57, 0x00, 0x5C, 0x32, 0x5D, 0x00, 0x5E, 0x00, 0x5F, 0x00,
30: 0x60, 0x2F, 0x61, 0x81, 0x62, 0x92, 0x63, 0x92,
31: },
32:
33: /* Standard VGA registers. */
34: {
35: 0xEF,
36: 0x00,
37: { 0x01, 0x01, 0x0F, 0x00, 0x0E },
38: {
39: 0x3D, 0x31, 0x32, 0x82, 0x35, 0x1D, 0x74, 0xF0, 0x00, 0x60,
40: 0x00, 0x00, 0x00, 0x00, 0x00, 0xC8, 0x58, 0x8C, 0x57, 0x00,
41: 0x00, 0x57, 0x73, 0xE3, 0xFF,
42: },
43: {
44: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, 0x38, 0x39,
45: 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x01, 0x00, 0x0F, 0x00,
46: },
47: {
48: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF,
49: },
50: }
51: };
52:
53: /* S3 928 800 x 600 x 24 (S3 mode 0x221).
54: */
55: static const S3Mode S3_928_800x600x24 = {
56: "S3_928[800 x 600 x 24]", S3_928, THREE_MEGABYTES,
57:
58: /* Mode control. */
59: { 60, 0x02 },
60:
61: /* Advanced function control register (0x4AE8). */
62: 0x07,
63:
64: /* Extra CRTC registers. */
65: {
66: 0x31, 0x8D, 0x32, 0x10, 0x33, 0x20, 0x34, 0x00, 0x35, 0x00,
67: 0x3A, 0x95, 0x3B, 0x7C, 0x3C, 0x32, 0x40, 0x50, 0x43, 0x00,
68: 0x50, 0x30, 0x51, 0x60, 0x53, 0x20, 0x54, 0x00, 0x56, 0x00,
69: 0x57, 0x00, 0x5C, 0x32, 0x5D, 0x00, 0x5E, 0x00, 0x5F, 0x00,
70: 0x60, 0x2F, 0x61, 0x81, 0x62, 0x92, 0x63, 0x92,
71: },
72:
73: /* Standard VGA registers. */
74: {
75: 0xEF,
76: 0x00,
77: { 0x01, 0x01, 0x0F, 0x00, 0x0E },
78: {
79: /* I had to add the `+1' to make this mode work. */
80: 0x7F, 0x63 + 1, 0x64 + 1, 0x82, 0x6A, 0x1A, 0x72, 0xF0, 0x00, 0x60,
81: 0x00, 0x00, 0x00, 0x00, 0x00, 0xC8, 0x59, 0x8D, 0x57, 0x00,
82: 0x00, 0x59, 0x72, 0xE3, 0xFF,
83: },
84: {
85: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, 0x38, 0x39,
86: 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x01, 0x00, 0x0F, 0x00,
87: },
88: {
89: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF,
90: },
91: }
92: };
93:
94: /* S3 928 1024 x 768 x 8 (S3 mode 0x205).
95: */
96: static const S3Mode S3_928_1024x768x8 = {
97: "S3_928[1024 x 768 x 8]", S3_928, ONE_MEGABYTE,
98:
99: /* Mode control. */
100: { 60, 0x0D, 70, 0x0E, 72, 0x05 },
101:
102: /* Advanced function control register (0x4AE8). */
103: 0x07,
104:
105: /* Extra CRTC registers. */
106: {
107: 0x31, 0x8D, 0x32, 0x10, 0x33, 0x00, 0x34, 0x00, 0x35, 0x00,
108: 0x3A, 0x95, 0x3B, 0x9D, 0x3C, 0x9F, 0x40, 0x51, 0x43, 0x00,
109: 0x50, 0x00, 0x51, 0x00, 0x53, 0x00, 0x54, 0x08, 0x56, 0x00,
110: 0x57, 0x00, 0x5C, 0x0D, 0x5D, 0x00, 0x5E, 0x00, 0x5F, 0x00,
111: 0x60, 0x1F, 0x61, 0x81, 0x62, 0x00, 0x63, 0x00,
112: },
113:
114: /* Standard VGA registers. */
115: {
116: 0x2F,
117: 0x00,
118: { 0x01, 0x01, 0x0F, 0x00, 0x0E },
119: {
120: 0xA3, 0x7F, 0x80, 0x86, 0x84, 0x95, 0x25, 0xF5, 0x00, 0x60,
121: 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x87, 0xFF, 0x80,
122: 0x60, 0xFF, 0x21, 0xEB, 0xFF,
123: },
124: {
125: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, 0x38, 0x39,
126: 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x01, 0x00, 0x0F, 0x00,
127: },
128: {
129: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF,
130: },
131: }
132: };
133:
134: /* S3 928 1024 x 768 x 15 (S3 mode 0x117).
135: */
136: static const S3Mode S3_928_1024x768x15 = {
137: "S3_928[1024 x 768 x 15]", S3_928, TWO_MEGABYTES,
138:
139: /* Mode control. */
140: { 60, 0x0D, 72, 0x05 },
141:
142: /* Advanced function control register (0x4AE8). */
143: 0x07,
144:
145: /* Extra CRTC registers. */
146: {
147: 0x31, 0x8D, 0x32, 0x10, 0x33, 0x20, 0x34, 0x00, 0x35, 0x00,
148: 0x3A, 0x95, 0x3B, 0x4B, 0x3C, 0x20, 0x40, 0x50, 0x43, 0x00,
149: 0x50, 0x10, 0x51, 0x50, 0x53, 0x00, 0x54, 0x00, 0x56, 0x00,
150: 0x57, 0x00, 0x5C, 0x3D, 0x5D, 0x00, 0x5E, 0x00, 0x5F, 0x00,
151: 0x60, 0x2F, 0x61, 0x82, 0x62, 0x00, 0x63, 0x00,
152: },
153:
154: /* Standard VGA registers. */
155: {
156: 0xEF,
157: 0x00,
158: { 0x01, 0x01, 0x0F, 0x00, 0x0E },
159: {
160: 0x4F, 0x3F, 0x40, 0x12, 0x42, 0x0A, 0x24, 0xF5, 0x00, 0x60,
161: 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x88, 0xFF, 0x00,
162: 0x00, 0xFF, 0x21, 0xE3, 0xFF,
163: },
164: {
165: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, 0x38, 0x39,
166: 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x01, 0x00, 0x0F, 0x00,
167: },
168: {
169: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF,
170: },
171: }
172: };
173:
174: /* S3 928 1024 x 768 x 24 (S3 mode 222).
175: * This mode doesn't quite work yet.
176: */
177: static const S3Mode S3_928_1024x768x24 = {
178: "S3_928[1024 x 768 x 24]", S3_928, THREE_MEGABYTES,
179:
180: /* Mode control. */
181: { 60, 0x0D, 72, 0x05 },
182:
183: /* Advanced function control register (0x4AE8). */
184: 0x07,
185:
186: /* Extra CRTC registers. */
187: {
188: 0x31, 0x8D, 0x32, 0x10, 0x33, 0x20, 0x34, 0x00, 0x35, 0x00,
189: 0x3A, 0x95, 0x3B, 0x9D, 0x3C, 0x40, 0x40, 0x50, 0x43, 0x00,
190: 0x50, 0x30, 0x51, 0x60, 0x53, 0x20, 0x54, 0x08, 0x56, 0x00,
191: 0x57, 0x00, 0x5C, 0x3D, 0x5D, 0x00, 0x5E, 0x00, 0x5F, 0x00,
192: 0x60, 0x1F, 0x61, 0x81, 0x62, 0x00, 0x63, 0x00,
193: },
194:
195: /* Standard VGA registers. */
196: {
197: 0x2F,
198: 0x00,
199: { 0x01, 0x01, 0x0F, 0x00, 0x0E },
200: {
201: 0xA3, 0x7F, 0x80, 0x86, 0x84, 0x95, 0x25, 0xF5, 0x00, 0x60,
202: 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x87, 0xFF, 0x00,
203: 0x60, 0xFF, 0x21, 0xEB, 0xFF,
204: },
205: {
206: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, 0x38, 0x39,
207: 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x01, 0x00, 0x0F, 0x00,
208: },
209: {
210: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF,
211: },
212: }
213: };
214:
215: /* S3 928 1280 x 1024 x 8 (S3 mode 0x107).
216: */
217: static const S3Mode S3_928_1280x1024x8 = {
218: "S3_928[1280 x 1024 x 8]", S3_928, TWO_MEGABYTES,
219:
220: /* Mode control. */
221: { 60, 0x0C },
222:
223: /* Advanced function control register (0x4AE8). */
224: 0x07,
225:
226: /* Extra CRTC registers. */
227: {
228: 0x31, 0x8D, 0x32, 0x10, 0x33, 0x20, 0x34, 0x00, 0x35, 0x00,
229: 0x3A, 0x95, 0x3B, 0xBB, 0x3C, 0x14, 0x40, 0x50, 0x43, 0x00,
230: 0x50, 0xC0, 0x51, 0x00, 0x53, 0x00, 0x54, 0x00, 0x56, 0x00,
231: 0x57, 0x00, 0x5C, 0x3C, 0x5D, 0x00, 0x5E, 0x55, 0x5F, 0x00,
232: 0x60, 0x2F, 0x61, 0x81, 0x62, 0x40, 0x63, 0x40,
233: },
234:
235: /* Standard VGA registers. */
236: {
237: 0x2F,
238: 0x00,
239: { 0x01, 0x01, 0x0F, 0x00, 0x0E },
240: {
241: /* I had to add the `-0xE' to make this work. */
242: 0x30, 0x27, 0x27, 0x94, 0x29, 0x8E - 0xE, 0x37, 0x52, 0x00, 0x60,
243: 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x05, 0x8C, 0xFF, 0xA0,
244: 0x00, 0x00, 0x31, 0xA3, 0xFF,
245: },
246: {
247: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, 0x38, 0x39,
248: 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x01, 0x00, 0x0F, 0x00,
249: },
250: {
251: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF,
252: },
253: }
254: };
255:
256: /* S3 928 1280 x 1024 x 15 (S3 mode 0x21A)
257: */
258: static const S3Mode S3_928_1280x1024x15 = {
259: "S3_928[1280 x 1024 x 15]", S3_928, FOUR_MEGABYTES,
260:
261: /* Mode control. */
262: { 60, 0x0C },
263:
264: /* Advanced function control register (0x4AE8). */
265: 0x07,
266:
267: /* Extra CRTC registers. */
268: {
269: 0x31, 0x8F, 0x32, 0x10, 0x33, 0x20, 0x34, 0x00, 0x35, 0x00,
270: 0x3A, 0x95, 0x3B, 0x5D, 0x3C, 0x28, 0x40, 0x50, 0x43, 0x00,
271: 0x50, 0x10, 0x51, 0x60, 0x53, 0x20, 0x54, 0x00, 0x56, 0x00,
272: 0x57, 0x00, 0x5C, 0x3C, 0x5D, 0x00, 0x5E, 0x55, 0x5F, 0x00,
273: 0x60, 0x2F, 0x61, 0x81, 0x62, 0x40, 0x63, 0x40,
274: },
275:
276: /* Standard VGA registers. */
277: {
278: 0x2F,
279: 0x00,
280: { 0x01, 0x01, 0x0F, 0x00, 0x0E },
281: {
282: /* I had to add the `+1' to get this to work. */
283: 0x65, 0x4F + 1, 0x50 + 1, 0x89, 0x52, 0x9C, 0x37, 0x52, 0x00, 0x40,
284: 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x05, 0x8C, 0xFF, 0x00,
285: 0x00, 0x00, 0x31, 0xE3, 0xFF,
286: },
287: {
288: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, 0x38, 0x39,
289: 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x01, 0x00, 0x0F, 0x00,
290: },
291: {
292: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF,
293: },
294: }
295: };
296:
297: const IODisplayInfo S3_928_ModeTable[] = {
298: {
299: /* S3 928; 800 x 600 x 15 @ 60Hz. */
300: 800, 600, 1024, 2048, 60, 0, IO_15BitsPerPixel,
301: IO_RGBColorSpace, "-RRRRRGGGGGBBBBB", 0, (void *)&S3_928_800x600x15,
302: },
303: {
304: /* S3 928; 800 x 600 x 24 @ 60Hz. */
305: 800, 600, 1024, 4096, 60, 0, IO_24BitsPerPixel,
306: IO_RGBColorSpace, "--------RRRRRRRRGGGGGGGGBBBBBBBB",
307: 0, (void *)&S3_928_800x600x24,
308: },
309: {
310: /* S3 928; 1024 x 768 x 8 @ 60Hz. RGB */
311: 1024, 768, 1024, 1024, 60, 0, IO_8BitsPerPixel,
312: IO_RGBColorSpace, "PPPPPPPP", 0, (void *)&S3_928_1024x768x8,
313: },
314: {
315: /* S3 928; 1024 x 768 x 8 @ 70Hz. RGB */
316: 1024, 768, 1024, 1024, 70, 0, IO_8BitsPerPixel,
317: IO_RGBColorSpace, "PPPPPPPP", 0, (void *)&S3_928_1024x768x8,
318: },
319: {
320: /* S3 928; 1024 x 768 x 8 @ 72Hz. RGB */
321: 1024, 768, 1024, 1024, 72, 0, IO_8BitsPerPixel,
322: IO_RGBColorSpace, "PPPPPPPP", 0, (void *)&S3_928_1024x768x8,
323: },
324: {
325: /* S3 928; 1024 x 768 x 8 @ 60Hz. */
326: 1024, 768, 1024, 1024, 60, 0, IO_8BitsPerPixel,
327: IO_OneIsWhiteColorSpace, "WWWWWWWW", 0, (void *)&S3_928_1024x768x8,
328: },
329: {
330: /* S3 928; 1024 x 768 x 8 @ 70Hz. */
331: 1024, 768, 1024, 1024, 70, 0, IO_8BitsPerPixel,
332: IO_OneIsWhiteColorSpace, "WWWWWWWW", 0, (void *)&S3_928_1024x768x8,
333: },
334: {
335: /* S3 928; 1024 x 768 x 8 @ 72Hz. */
336: 1024, 768, 1024, 1024, 72, 0, IO_8BitsPerPixel,
337: IO_OneIsWhiteColorSpace, "WWWWWWWW", 0, (void *)&S3_928_1024x768x8,
338: },
339: {
340: /* S3 928; 1024 x 768 x 15 @ 60Hz. */
341: 1024, 768, 1024, 2048, 60, 0, IO_15BitsPerPixel,
342: IO_RGBColorSpace, "-RRRRRGGGGGBBBBB", 0, (void *)&S3_928_1024x768x15,
343: },
344: {
345: /* S3 928; 1024 x 768 x 15 @ 72Hz. */
346: 1024, 768, 1024, 2048, 72, 0, IO_15BitsPerPixel,
347: IO_RGBColorSpace, "-RRRRRGGGGGBBBBB", 0, (void *)&S3_928_1024x768x15,
348: },
349: {
350: /* S3 928; 1024 x 768 x 24 @ 60Hz. */
351: 1024, 768, 1024, 4096, 60, 0, IO_24BitsPerPixel,
352: IO_RGBColorSpace, "--------RRRRRRRRGGGGGGGGBBBBBBBB",
353: 0, (void *)&S3_928_1024x768x24,
354: },
355: {
356: /* S3 928; 1024 x 768 x 24 @ 72Hz. */
357: 1024, 768, 1024, 4096, 72, 0, IO_24BitsPerPixel,
358: IO_RGBColorSpace, "--------RRRRRRRRGGGGGGGGBBBBBBBB",
359: 0, (void *)&S3_928_1024x768x24,
360: },
361: {
362: /* S3 928; 1280 x 1024 x 8 @ 60Hz. */
363: 1280, 1024, 1280, 1280, 60, 0, IO_8BitsPerPixel,
364: IO_OneIsWhiteColorSpace, "WWWWWWWW", 0, (void *)&S3_928_1280x1024x8,
365: },
366: {
367: /* S3 928; 1280 x 1024 x 8 @ 60Hz. RGB */
368: 1280, 1024, 1280, 1280, 60, 0, IO_8BitsPerPixel,
369: IO_RGBColorSpace, "PPPPPPPP", 0, (void *)&S3_928_1280x1024x8,
370: },
371: {
372: /* S3 928; 1280 x 1024 x 15 @ 60Hz. */
373: 1280, 1024, 2048, 4096, 60, 0, IO_15BitsPerPixel,
374: IO_RGBColorSpace, "-RRRRRGGGGGBBBBB", 0, (void *)&S3_928_1280x1024x15,
375: },
376: };
377:
378: const int S3_928_ModeTableCount =
379: (sizeof(S3_928_ModeTable) / sizeof(S3_928_ModeTable[0]));
380:
381: const int S3_928_defaultMode = 2;
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.