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1.1 root 1: /* Copyright (c) 1992 NeXT Computer, Inc. All rights reserved.
2: *
3: * SVGACommonDefines.h
4: *
5: */
6:
7: /*
8: ** Color palette constants
9: */
10: #define WHITE_INDEX 3
11: #define LIGHT_GRAY_INDEX 2
12: #define DARK_GRAY_INDEX 1
13: #define BLACK_INDEX 0
14:
15: /*
16: ** Color palette constants (gamma 2.2, for typical CRT displays)
17: */
18: #define WHITE_PALETTE_VALUE 0x3F
19: #define LIGHT_GRAY_PALETTE_VALUE 0x34
20: #define DARK_GRAY_PALETTE_VALUE 0x26
21: #define BLACK_PALETTE_VALUE 0
22:
23:
24: /*
25: **************************************************************************
26: ** VGA :- General registers **
27: **************************************************************************
28: */
29: #define WRIT_MONO_GEN_MISC_OP 0x03C2
30: #define WRIT_COLR_GEN_MISC_OP 0x03C2
31: #define WRIT_EIDR_GEN_MISC_OP 0x03C2
32:
33: #define READ_MONO_GEN_MISC_OP 0x03CC
34: #define READ_COLR_GEN_MISC_OP 0x03CC
35: #define READ_EIDR_GEN_MISC_OP 0x03CC
36:
37: #define READ_MONO_GEN_IN_ST_0 0x03C2
38: #define READ_COLR_GEN_IN_ST_0 0x03C2
39: #define READ_EIDR_GEN_IN_ST_0 0x03C2
40:
41: #define READ_MONO_GEN_IN_ST_1 0x03BA
42: #define READ_COLR_GEN_IN_ST_1 0x03DA
43:
44: #define WRIT_MONO_GEN_FEAT_CT 0x03BA
45: #define WRIT_COLR_GEN_FEAT_CT 0x03DA
46:
47: #define READ_MONO_GEN_FEAT_CT 0x03CA
48: #define READ_COLR_GEN_FEAT_CT 0x03CA
49:
50: /*
51: ** Index mask - not necessary here
52: */
53: #define MONO_GEN_MSK 0x00
54: #define COLR_GEN_MSK 0x00
55: #define EIDR_GEN_MSK 0x00
56:
57: /*
58: ** List of index registers
59: */
60:
61: /*
62: ** Bitfields for misc op reg.
63: */
64: #define GEN_AT_VSP 0x80
65: #define GEN_AT_HSP 0x40
66: #define GEN_AT__PB 0x00
67: #define GEN_AT_DVD 0x10
68: #define GEN_AT__CS 0x0C
69: #define GEN_AT__ER 0x02
70: #define GEN_AT_IOA 0x01
71:
72: /*
73: ** Bitfields for feature control reg.
74: */
75: #define GEN_AT_VSS 0x08
76:
77: /*
78: ** Bitfields for Input Status #0 register
79: */
80: #define GEN_AT__SS 0x10
81:
82: /*
83: ** Bitfields for Input Status #1 register
84: */
85: #define GEN_AT__VR 0x08
86: #define GEN_AT__DE 0x01
87:
88: /*
89: **************************************************************************
90: ** VGA :- Sequencer registers **
91: **************************************************************************
92: */
93: #define MONO_SEQ_ADDR 0x03C4
94: #define COLR_SEQ_ADDR 0x03C4
95: #define EIDR_SEQ_ADDR 0x03C4
96:
97: #define MONO_SEQ_DATA 0x03C5
98: #define COLR_SEQ_DATA 0x03C5
99: #define EIDR_SEQ_DATA 0x03C5
100:
101: /*
102: ** List of index registers
103: */
104: #define SEQ_AT_RST 0x00
105: #define SEQ_AT_CLO 0x01
106: #define SEQ_AT_MPK 0x02
107: #define SEQ_AT_CRS 0x03
108: #define SEQ_AT_MMD 0x04
109:
110: /*
111: ** Bitfield - Sequencer registers - Reset
112: */
113: #define SEQ_AT__SR 0x02
114: #define SEQ_AT__AR 0x00
115:
116: /*
117: ** Bitfields - Sequencer registers - Clocking Mode Register
118: */
119: #define SEQ_AT__SO 0x20
120: #define SEQ_AT__S4 0x10
121: #define SEQ_AT__DC 0x08
122: #define SEQ_AT__SL 0x04
123: #define SEQ_AT__89 0x01
124:
125: /*
126: ** Bitfields - Sequencer registers - Map Mask Register
127: */
128: #define SEQ_AT_EM3 0x08
129: #define SEQ_AT_EM2 0x04
130: #define SEQ_AT_EM1 0x02
131: #define SEQ_AT_EM0 0x01
132:
133: /*
134: ** Bitfields - Sequencer registers - Character Map Select Registers
135: */
136: #define SEQ_AT_SAH 0x20
137: #define SEQ_AT_SBH 0x10
138: #define SEQ_AT__SA 0x0C
139: #define SEQ_AT__SB 0x03
140:
141: /*
142: ** Bitfields - Sequencer registers - Memory Mode Register
143: */
144: #define SEQ_AT__C4 0x08
145: #define SEQ_AT__OE 0x04
146: #define SEQ_AT__EM 0x02
147:
148: /*
149: **************************************************************************
150: ** VGA :- CRT Controller Registers **
151: **************************************************************************
152: */
153: #define MONO_CRT_ADDR 0x03B4
154: #define MONO_CRT_DATA 0x03B5
155:
156: #define COLR_CRT_ADDR 0x03D4
157: #define COLR_CRT_DATA 0x03D5
158:
159:
160: /*
161: ** List of index registers
162: */
163: #define CRT_AT_HORZ_TOT 0x00
164: #define CRT_AT_HORZ_DND 0x01
165: #define CRT_AT_HORZ_BST 0x02
166: #define CRT_AT_HORZ_BND 0x03
167: #define CRT_AT_HORZ_RST 0x04
168: #define CRT_AT_HORZ_RND 0x05
169: #define CRT_AT_VERT_TOT 0x06
170: #define CRT_AT_OVERFLOW 0x07
171: #define CRT_AT_PRE_ROWS 0x08
172: #define CRT_AT_MAX_SCAN 0x09
173: #define CRT_AT_CURSR_ST 0x0A
174: #define CRT_AT_CURSR_ND 0x0B
175: #define CRT_AT_ST_ADRHI 0x0C
176: #define CRT_AT_ST_ADRLO 0x0D
177: #define CRT_AT_CR_LOCHI 0x0E
178: #define CRT_AT_CR_LOCLO 0x0F
179: #define CRT_AT_VRT_RTST 0x10
180: #define CRT_AT_VRT_RTLO 0x11
181: #define CRT_AT_VRT_DSND 0x12
182: #define CRT_AT___OFFSET 0x13
183: #define CRT_AT_UNDR_LOC 0x14
184: #define CRT_AT_VBLNK_ST 0x15
185: #define CRT_AT_VBLNK_ND 0x16
186: #define CRT_AT_MOD_CTRL 0x17
187: #define CRT_AT_LINE_CMP 0x18
188:
189: /*
190: ** Bitfields - CRT Controller registers - Horizontal total Register
191: */
192: #define CRT_AT__HT 0xFF
193:
194: /*
195: ** Bitfields - CRT Controller registers - Horizontal Display End Register
196: */
197: #define CRT_AT_HDE 0xFF
198:
199: /*
200: ** Bitfields - CRT Controller registers - Start Horizontal Blanking register
201: */
202: #define CRT_AT_SHB 0xFF
203:
204: /*
205: ** Bitfields - CRT Controller registers - End Horizontal Blanking Register
206: */
207: #define CRT_AT__CR 0x80
208: #define CRT_AT_DES 0x60
209: #define CRT_AT_EHB 0x1F
210:
211: /*
212: ** Bitfields - CRT Controller registers - Start Horizontal Retrace Register
213: */
214: #define CRT_AT_SHR 0xFF
215:
216: /*
217: ** Bitfields - CRT Controller registers - End Horizontal Retrace Register
218: */
219: #define CRT_AT_EHB_6 0x80
220: #define EGA_AT_CRT 0x80
221: #define CRT_AT_HRD 0x60
222: #define CRT_AT_EHR 0x1F
223:
224: /*
225: ** Bitfields - CRT Controller registers - Vertical Total Register
226: */
227: #define CRT_AT_VT 0xFF
228:
229: /*
230: ** Bitfields - CRT Controller registers - Overflow Register
231: */
232: #define CRT_AT_VRS_9 0x80
233: #define CRT_AT_VDE_9 0x40
234: #define EGA_AT_CRT_8 0x20
235: #define CRT_AT_VT1_8 0x20
236: #define CRT_AT__LC_8 0x10
237: #define CRT_AT_VBS_8 0x08
238: #define CRT_AT_VRS_8 0x04
239: #define CRT_AT_VDE_8 0x02
240: #define CRT_AT__VT_8 0x01
241:
242: /*
243: ** Bitfields - CRT Controller registers - Preset Row Scan Register
244: */
245: #define CRT_AT__BP 0x60
246: #define CRT_AT_PRS 0x1F
247:
248: /*
249: ** Bitfields - CRT Controller registers - Maximum Scan Line Register
250: */
251: #define CRT_AT_2T4 0x80
252: #define CRT_AT__LC 0x40
253: #define CRT_AT_VBS_9 0x20
254: #define CRT_AT_MSL 0x1F
255:
256: /*
257: ** Bitfields - CRT Controller registers - Cursor Start Register
258: */
259: #define CRT_AT_COO 0x20
260: #define CRT_AT__CS 0x1F
261:
262: /*
263: ** Bitfields - CRT Controller registers - Cursor End Register
264: */
265: #define CRT_AT_CSK 0x60
266: #define CRT_AT__CE 0x1F
267:
268: /*
269: ** Bitfields - CRT Controller registers - Start Address High Register
270: */
271: #define CRT_AT_SAH 0xFF
272:
273: /*
274: ** Bitfields - CRT Controller registers - Start Address Low Register
275: */
276: #define CRT_AT_SAL 0xFF
277:
278: /*
279: ** Bitfields - CRT Controller registers - Cursor Location High Register
280: */
281: #define CRT_AT_CLH 0xFF
282:
283: /*
284: ** Bitfields - CRT Controller registers - Cursor Location Low Register
285: */
286: #define CRT_AT_CLL 0xFF
287:
288: /*
289: ** Bitfields - CRT Controller registers - Vertical Retrace Start Register
290: */
291: #define CRT_AT_VRS 0xFF
292:
293: /*
294: ** Bitfields - CRT Controller registers - Vertical Retrace End Register
295: */
296: #define CRT_AT__PR 0x80
297: #define CRT_AT__BW 0x40
298: #define CRT_AT_DVI 0x20
299: #define CRT_AT_CVI 0x10
300: #define CRT_AT_EVR 0x0F
301:
302: /*
303: ** Bitfields - CRT Controller registers - Light Pen High Register
304: */
305: #define CRT_AT_LPH 0xFF
306:
307: /*
308: ** Bitfields - CRT Controller registers - Light Pen Low Register
309: */
310: #define CRT_AT_LPL 0xFF
311:
312: /*
313: ** Bitfields - CRT Controller registers - Vertical Display End Register
314: */
315: #define CRT_AT_VDE 0xFF
316:
317: /*
318: ** Bitfields - CRT Controller registers - Offset Register
319: */
320: #define CRT_AT_OFF 0xFF
321:
322: /*
323: ** Bitfields - CRT Controller registers - Underline Location Register
324: */
325: #define CRT_AT__DW 0x40
326: #define CRT_AT_CB4 0x20
327: #define CRT_AT__UL 0x1F
328:
329: /*
330: ** Bitfields - CRT Controller registers - Start vertical Blank register
331: */
332: #define CRT_AT_VBS 0xFF
333:
334: /*
335: ** Bitfields - CRT Controller registers - End Vertical Blank register
336: */
337: #define CRT_AT_VBE_H 0x60
338: #define CRT_AT_VBE_L 0x1F
339:
340: /*
341: ** Bitfields - CRT Controller registers - Mode Control Register
342: */
343: #define CRT_AT__HR 0x80
344: #define CRT_AT__WB 0x40
345: #define CRT_AT__AW 0x20
346: #define CRT_AT__OC 0x10
347: #define CRT_AT_CBT 0x08
348: #define CRT_AT_HRS 0x04
349: #define CRT_AT_SRS 0x02
350: #define CRT_AT_CMS 0x01
351:
352: /*
353: ** Bitfields - CRT Controller registers - Line Compare Register
354: */
355: #define CRT_AT_LNC 0xFF
356:
357: /*
358: **************************************************************************
359: ** VGA :- GCR Controller Registers **
360: **************************************************************************
361: */
362: #define MONO_GCR_ADDR 0x03CE
363: #define COLR_GCR_ADDR 0x03CE
364: #define EIDR_GCR_ADDR 0x03CE
365:
366: #define MONO_GCR_DATA 0x03CF
367: #define COLR_GCR_DATA 0x03CF
368: #define EIDR_GCR_DATA 0x03CF
369:
370: /*
371: ** List of index registers
372: */
373: #define GCR_AT_SET_RESET 0x00
374: #define GCR_AT_ENA_S_RST 0x01
375: #define GCR_AT_COLR_COMP 0x02
376: #define GCR_AT_DATA_ROTR 0x03
377: #define GCR_AT_READ_MAPS 0x04
378: #define GCR_AT_GCR__MODE 0x05
379: #define GCR_AT_GCR__MISC 0x06
380: #define GCR_AT_CLR_NOCAR 0x07
381: #define GCR_AT_BIT__MASK 0x08
382:
383: /*
384: ** Bitfields - Graphics Controller Registers - Graphics#1 Position Register
385: */
386: #define GCR_AT_GP1 0x03
387:
388: /*
389: ** Bitfields - Graphics Controller Registers - Graphics#2 Position Register
390: */
391: #define GCR_AT_GP2 0x03
392:
393: /*
394: ** Bitfields - Graphics Controller Registers - Set/Reset Register
395: */
396: #define GCR_AT_S_R 0x0F
397:
398: /*
399: ** Bitfields - Graphics Controller Registers - Enable Set/Reset Register
400: */
401: #define GCR_AT_ESR 0x0F
402:
403: /*
404: ** Bitfields - Graphics Controller Registers - Color Compare Register
405: */
406: #define GCR_AT__CC 0x0F
407:
408: /*
409: ** Bitfields - Graphics Controller Registers - Data Rotate register
410: */
411: #define GCR_AT__FS 0x30
412: #define GCR_AT__RC 0x0F
413:
414: /*
415: ** Bitfields - Graphics Controller Registers - Read Map Select Register
416: */
417: #define GCR_AT_RMS 0x03
418:
419: /*
420: ** Bitfields - Graphics Controller Registers - Mode Register
421: */
422: #define GCR_AT__SR 0x60
423: #define GCR_AT__OE 0x10
424: #define GCR_AT__RM 0x08
425: #define GCR_AT__TC 0x04
426: #define GCR_AT__WM 0x03
427:
428: /*
429: ** Bitfields - Graphics Controller Registers - Miscellaneous register
430: */
431: #define GCR_AT__MM 0x0C
432: #define GCR_AT_COE 0x02
433: #define GCR_AT__GA 0x01
434:
435: /*
436: ** Bitfields - Graphics Controller Registers - Color Dont Care register
437: */
438: #define GCR_AT_CDC 0x0F
439:
440: /*
441: ** Bitfields - Graphics Controller Registers - Bit Mask
442: */
443: #define GCR_AT__BM 0xFF
444:
445: /*
446: **************************************************************************
447: ** VGA :- ACR Controller Registers **
448: **************************************************************************
449: */
450: #define WRIT_TOGL_ACR_ADDR 0x03C0
451: #define READ_TOGL_ACR_ADDR 0x03C0
452:
453: #define WRIT_TOGL_ACR_DATA 0x03C0
454: #define READ_TOGL_ACR_DATA 0x03C1
455:
456: /*
457: ** Index mask
458: */
459: #define ACR_MSK 0x1F
460:
461: /*
462: ** List of index registers
463: */
464: #define ACR_AT_PALETTE_0 0x00
465: #define ACR_AT_PALETTE_1 0x01
466: #define ACR_AT_PALETTE_2 0x02
467: #define ACR_AT_PALETTE_3 0x03
468: #define ACR_AT_PALETTE_4 0x04
469: #define ACR_AT_PALETTE_5 0x05
470: #define ACR_AT_PALETTE_6 0x06
471: #define ACR_AT_PALETTE_7 0x07
472: #define ACR_AT_PALETTE_8 0x08
473: #define ACR_AT_PALETTE_9 0x09
474: #define ACR_AT_PALETTE_A 0x0A
475: #define ACR_AT_PALETTE_B 0x0B
476: #define ACR_AT_PALETTE_C 0x0C
477: #define ACR_AT_PALETTE_D 0x0D
478: #define ACR_AT_PALETTE_E 0x0E
479: #define ACR_AT_PALETTE_F 0x0F
480: #define ACR_AT_MODE_CNTL 0x10
481: #define ACR_AT_OVERSCN_C 0x11
482: #define ACR_AT_CLR_PL_EN 0x12
483: #define ACR_AT_HORZ_PXPN 0x13
484: #define ACR_AT_COLOR_SEL 0x14
485:
486: /*
487: ** Bitfields - Attribute Controller registers - pallette registers
488: */
489: #define ACR_AT__SR 0x20
490: #define ACR_AT__SG 0x10
491: #define ACR_AT__SB 0x08
492: #define ACR_AT_REG 0x04
493: #define ACR_AT_GRN 0x02
494: #define ACR_AT_BLU 0x01
495:
496: /*
497: ** Bitfields - Attribute Controller registers - Mode Control register
498: */
499: #define ACR_AT_IPS 0x80
500: #define ACR_AT_PCS 0x40
501: #define ACR_AT_PPC 0x20
502: #define ACR_AT__BI 0x08
503: #define ACR_AT_ELG 0x04
504: #define ACR_AT__DT 0x02
505: #define ACR_AT__GA 0x01
506:
507: /*
508: ** Bitfields - Attribute Controller registers - Overscan Color Register
509: */
510:
511: #define ACR_AT_OSR 0x20
512: #define ACR_AT_OSG 0x10
513: #define ACR_AT_OSB 0x08
514: #define ACR_AT_ORD 0x04
515: #define ACR_AT_OGR 0x02
516: #define ACR_AT_OBL 0x01
517: /*
518: ** Bitfields - Attribute Controller registers - Color Plane Enable Register
519: */
520:
521: #define ACR_AT_VSM 0x30
522: #define ACR_AT_CPE 0x0F
523: /*
524: ** Bitfields - Attribute Controller registers - Horizontal Pixel Panning Reg
525: */
526: #define ACR_AT_HPP 0x0F
527:
528: /*
529: ** Bitfields - Attribute Controller registers - Color Select Register
530: */
531: #define ACR_AT_C67 0x0C
532: #define ACR_AT_C45 0x03
533:
534: /*
535: **************************************************************************
536: ** VGA :- PEL Controller Registers **
537: **************************************************************************
538: */
539: #define WRIT_MONO_PEL_AWMR 0x03C8
540: #define WRIT_COLR_PEL_AWMR 0x03C8
541: #define READ_MONO_PEL_AWMR 0x03C8
542: #define READ_COLR_PEL_AWMR 0x03C8
543:
544: #define WRIT_MONO_PEL_ARMR 0x03C7
545: #define WRIT_COLR_PEL_ARMR 0x03C7
546:
547: #define WRIT_MONO_PEL_DATA 0x03C9
548: #define WRIT_COLR_PEL_DATA 0x03C9
549: #define READ_MONO_PEL_DATA 0x03C9
550: #define READ_COLR_PEL_DATA 0x03C9
551:
552: #define READ_MONO_PEL_DACS 0x03C7
553: #define READ_COLR_PEL_DACS 0x03C7
554:
555: #define WRIT_MONO_PEL_MASK 0x03C6
556: #define WRIT_COLR_PEL_MASK 0x03C6
557: #define READ_MONO_PEL_MASK 0x03C6
558: #define READ_COLR_PEL_MASK 0x03C6
559:
560: /*
561: **************************************************************************
562: ** VGA :- External Palette RAM
563: **************************************************************************
564: */
565: #define MONO_PEL_MASK 0x03C6
566: #define COLR_PEL_MASK 0x03C6
567: #define EIDR_PEL_MASK 0x03C6
568:
569: #define MONO_PEL_WADR 0x03C8
570: #define COLR_PEL_WADR 0x03C8
571: #define EIDR_PEL_WADR 0x03C8
572:
573: #define MONO_PEL_DATA 0x03C9
574: #define COLR_PEL_DATA 0x03C9
575: #define EIDR_PEL_DATA 0x03C9
576:
577: #define MONO_PEL_RADR 0x03C7
578: #define COLR_PEL_RADR 0x03C7
579: #define EIDR_PEL_RADR 0x03C7
580:
581: #define MONO_PEL_DACS 0x03C7
582: #define COLR_PEL_DACS 0x03C7
583: #define EIDR_PEL_DACS 0x03C7
584:
585: /*
586: **************************************************************************
587: ** VGA :- MODES **
588: **************************************************************************
589: */
590: #define MAX_GEN_INDEX 0x01
591: #define MAX_SEQ_INDEX SEQ_AT_MMD
592: #define MAX_CRT_INDEX CRT_LINE_CMP
593: #define MAX_GCR_INDEX GCR_BIT__MASK
594: #define MAX_ACR_INDEX ACR_COLOUR_SEL
595:
596: /*
597: ** There now follows a symbolic list of modes, these will be used as indeces into tables of
598: ** initial values to be put into the various registers for a given mode.
599: */
600:
601: #define MODE_VGA_AT_00 0x00
602: #define MODE_VGA_AT_01 0x01
603: #define MODE_VGA_AT_02 0x02
604: #define MODE_VGA_AT_03 0x03
605: #define MODE_VGA_AT_04 0x04
606: #define MODE_VGA_AT_05 0x05
607: #define MODE_VGA_AT_06 0x06
608: #define MODE_VGA_AT_07 0x07
609: #define MODE_VGA_AT_00_X 0x08
610: #define MODE_VGA_AT_01_X 0x09
611: #define MODE_VGA_AT_02_X 0x0A
612: #define MODE_VGA_AT_03_X 0x0B
613: #define MODE_VGA_AT_07_X 0x0C
614: #define MODE_VGA_AT_0D 0x0D
615: #define MODE_VGA_AT_0E 0x0E
616: #define MODE_VGA_AT_0F 0x0F
617: #define MODE_VGA_AT_10 0x10
618: #define MODE_VGA_AT_11 0x11
619: #define MODE_VGA_AT_12 0x12
620: #define MODE_VGA_AT_13 0x13
621:
622: #define MIN_VGA_AT_MODE MODE_VGA_AT_00
623: #define MAX_VGA_AT_MODE MODE_VGA_AT_13
624: #define NUM_VGA_AT_MODE MAX_VGA_AT_MODE-MIN_VGA_AT_MODE
625:
626: #define IS_REG_MODE(a) ((a) <= MAX_VGA_AT_MODE)
627:
628: struct mode_params {
629: char *m_str;
630: int p_type;
631: int p_bpp;
632: int p_start;
633: int p_pages;
634: int p_alfa_w;
635: int p_alfa_h;
636: int p_char_w;
637: int p_char_h;
638: int p_disp_w;
639: int p_disp_h;
640: int p_font;
641: };
642:
643: /*
644: ** Defines for the type of a particular mode ie - is it alphanummeric(A) or graphical(G),
645: ** color(C) or mono(M),
646: */
647:
648: #define MODE_A_M 0x00
649: #define MODE_A_C 0x01
650: #define MODE_G_M 0x10
651: #define MODE_G_C 0x11
652:
653: /*
654: **************************************************************************
655: ** VGA :- FONTS **
656: **************************************************************************
657: */
658:
659: #define FONT_09_BY_16 0x00
660: #define FONT_09_BY_15 0x01
661: #define FONT_09_BY_14 0x02
662: #define FONT_09_BY_13 0x03
663: #define FONT_08_BY_16 0x04
664: #define FONT_08_BY_15 0x05
665: #define FONT_08_BY_14 0x06
666: #define FONT_08_BY_08 0x07
667:
668:
669: #define VGA_AT_MAX_PLANES 0x04
670:
671:
672: // Start of defines from prototype vga_ts_defs.h file.
673:
674: /*
675: **************************************************************************
676: ** VGA :- General registers **
677: **************************************************************************
678: */
679: #define WRIT_MONO_MODE_CT 0x03B8
680: #define WRIT_COLR_MODE_CT 0x03D8
681: #define WRIT_EIDR_MODE_CT 0x03D8
682:
683: #define WRIT_MONO_GEN_VID_EN 0x46E8
684: #define WRIT_COLR_GEN_VID_EN 0x46E8
685: #define WRIT_EIDR_GEN_VID_EN 0x46E8
686:
687: #define READ_MONO_GEN_VID_EN 0x03C3
688: #define READ_COLR_GEN_VID_EN 0x03C3
689: #define READ_EIDR_GEN_VID_EN 0x03C3
690:
691: #define WRIT_MONO_ALT_VID_EN 0x46E8
692: #define WRIT_COLR_ALT_VID_EN 0x46E8
693: #define WRIT_EIDR_ALT_VID_EN 0x46E8
694:
695: #define READ_MONO_ALT_VID_EN 0x46E8
696: #define READ_COLR_ALT_VID_EN 0x46E8
697: #define READ_EIDR_ALT_VID_EN 0x46E8
698:
699: /*
700: ** Bitfields for Hercules compatibility register
701: */
702: #define GEN_TS_HER 0xFD
703: #define GEN_TS_ESP 0x02
704:
705: /*
706: ** Bitfields for Video Subsystem Register
707: */
708: #define GEN_TS_WRI 0x01
709: #define GEN_TS_REA 0x08
710: #define GEN_TS_VSR 0xF6
711:
712: /*
713: **************************************************************************
714: ** VGA :- 6845 Compatibility registers **
715: **************************************************************************
716: */
717: #define MONO_6845_CTL_REG 0x03B4
718: #define COLR_6845_CTL_REG 0x03D4
719:
720: #define MONO_6845_DTA_REG 0x03B5
721: #define COLR_6845_DTA_REG 0x03D5
722:
723: #define MONO_6845_DMC_REG 0x03B8
724: #define COLR_6845_DMC_REG 0x03D8
725:
726: #define WRIT_6845_DCC_REG 0x03D9
727:
728: #define MONO_6845_DSC_REG 0x03BA
729: #define COLR_6845_DSC_REG 0x03DA
730:
731: #define WRIT_6845_ATT_REG 0x03DE
732: #define WRIT_HERCULES_REG 0x03BF
733:
734: /*
735: **************************************************************************
736: ** VGA :- Sequencer registers **
737: **************************************************************************
738: */
739:
740: /*
741: ** New Registers
742: */
743:
744: /*
745: ** List of index registers
746: */
747: #define SEQ_TS_TSS 0x06
748: #define SEQ_TS_TAM 0x07
749:
750: /*
751: ** Bitfields - Sequencer Registers - TS state control Tseng Labs
752: */
753: #define SEQ_TS_TSS 0x06
754:
755: /*
756: ** Bitfields - Sequencer Registers - TS Auxiliary mode Tseng Labs
757: */
758: #define SEQ_TS_VGM 0x80
759: #define SEQ_TS_MC2 0x40
760: #define SEQ_TS_RO2 0x20
761: #define SEQ_TS_RO1 0x08
762: #define SEQ_TS_SC2 0x02
763: #define SEQ_TS_MC4 0x01
764: #define SEQ_TS_MSK 0x14
765:
766: /*
767: **************************************************************************
768: ** VGA :- CRT Controller Registers **
769: **************************************************************************
770: */
771:
772: /*
773: ** New Registers
774: */
775:
776: /*
777: ** List of index registers
778: */
779: #define CRT_TS_RAS 0x32
780: #define CRT_TS_ESA 0x33
781: #define CRT_TS_CTL 0x34
782: #define CRT_TS_OVH 0x35
783: #define CRT_TS_VS1 0x36
784: #define CRT_TS_VS2 0x37
785:
786: /*
787: ** Bitfields - CRT Controller registers - RAS/CAS Configuration Reggister Tseng Labs
788: */
789: #define CRT_TS_SCM 0x80
790: #define CRT_TS_RAL 0x40
791: #define CRT_TS_RCD 0x20
792: #define CRT_TS_RSP 0x18
793: #define CRT_TS_CSP 0x04
794: #define CRT_TS_CSW 0x03
795:
796: /*
797: ** Bitfields - CRT Controller registers - Extended Start Register Tseng Labs
798: */
799: #define CRT_TS_CSA 0x0C
800: #define CRT_TS_LSA 0x03
801:
802: /*
803: ** Bitfields - CRT Controller registers - 6845 Compatibility Control Register Tseng Labs
804: */
805: #define CRT_TS_CMP 0x80
806: #define CRT_TS_EBA 0x40
807: #define CRT_TS_EXL 0x20
808: #define CRT_TS_EXR 0x10
809: #define CRT_TS_EVS 0x08
810: #define CRT_TS_TRI 0x04
811: #define CRT_TS_MCK 0x02
812: #define CRT_TS_EMK 0x01
813:
814: /*
815: ** Bitfields - CRT Controller registers - Overflow High Tseng Labs
816: */
817: #define CRT_TS_VIM 0x80
818: #define CRT_TS_ARW 0x40
819: #define CRT_TS_ESR 0x20
820: #define CRT_TS_LCA 0x10
821: #define CRT_TS_VSA 0x08
822: #define CRT_TS_VDA 0x04
823: #define CRT_TS_VTA 0x02
824: #define CRT_TS_VBA 0x01
825:
826: /*
827: ** Bitfields - CRT Controller registers - Video System Configuration 1 Tseng Labs
828: */
829: #define CRT_TS_RWF 0x80
830: #define CRT_TS_DMF 0x40
831: #define CRT_TS_AMD 0x20
832: #define CRT_TS_SGL 0x10
833: #define CRT_TS_FWF 0x08
834: #define CRT_TS_REF 0x07
835:
836: /*
837: ** Bitfields - CRT Controller registers - Video System Configuration 2 Tseng Labs
838: */
839: #define CRT_TS_DRM 0x80
840: #define CRT_TS_TST 0x40
841: #define CRT_TS_PTC 0x20
842: #define CRT_TS_RM8 0x10
843: #define CRT_TS_DMD 0x0C
844: #define CRT_TS_DBW 0x03
845:
846: /*
847: **************************************************************************
848: ** VGA :- GCR Controller Registers **
849: **************************************************************************
850: */
851:
852: /*
853: ** New Registers
854: */
855: #define MONO_GCR_SEGS 0x03CD
856: #define COLR_GCR_SEGS 0x03CD
857: #define EIDR_GCR_SEGS 0x03CD
858:
859: /*
860: ** List of index registers
861: */
862:
863: /*
864: ** Bitfields - GCR Controller registers - Segment Select Register Tseng Labs
865: */
866: #define GCR_TS_GRD 0xF0
867: #define GCR_TS_GWR 0x0F
868:
869: /*
870: **************************************************************************
871: ** VGA :- ACR Controller Registers **
872: **************************************************************************
873: */
874:
875: /*
876: ** New Registers
877: */
878:
879: /*
880: ** List of index registers
881: */
882: #define ACR_TS_MSC 0x16
883:
884: /*
885: ** Bitfields - Attribute Controller Registers - Miscellaneous Tseng Labs
886: */
887: #define ACR_TS_BYP 0x80
888: #define ACR_TS_2BC 0x40
889: #define ACR_TS_SHR 0x30
890: #define ACR_TS_RES 0x0F
891:
892: /*
893: **************************************************************************
894: ** VGA :- MODES **
895: **************************************************************************
896: */
897: #define MAX_TS_GEN_INDEX 0x01
898: #define MAX_TS_SEQ_INDEX SEQ_TS_TAM
899: #define MAX_TS_CRT_INDEX CRT_TS_VS2
900: #define MAX_TS_GCR_INDEX GCR_AT_BIT__MASK
901: #define MAX_TS_ACR_INDEX ACR_TS_MISC
902:
903:
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