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1.1 root 1: ;;- Machine description for AMD Am29000 for GNU C compiler
2: ;; Copyright (C) 1991, 1992 Free Software Foundation, Inc.
3: ;; Contributed by Richard Kenner ([email protected])
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 2, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
22:
23: ;; The insns in this file are presented in the same order as the AMD 29000
24: ;; User's Manual (i.e., alphabetical by machine op-code).
25: ;;
26: ;; DEFINE_EXPAND's are located near the first occurrence of the major insn
27: ;; that they generate.
28:
29: ;; The only attribute we have is the type. We only care about calls, branches,
30: ;; loads, stores, floating-point operations, and multi-word insns.
31: ;; Everything else is miscellaneous.
32:
33: (define_attr "type"
34: "call,branch,load,store,fadd,fmul,fam,fdiv,fsqrt,dmul,dam,ddiv,dsqrt,multi,misc"
35: (const_string "misc"))
36:
37: ;; ASM insns cannot go into a delay slot, so call them "multi".
38: (define_asm_attributes [(set_attr "type" "multi")])
39:
40: (define_attr "in_delay_slot" "yes,no"
41: (if_then_else (eq_attr "type" "call,branch,multi") (const_string "no")
42: (const_string "yes")))
43:
44: ;; Branch and call insns require a single delay slot. Annulling is not
45: ;; supported.
46: (define_delay (eq_attr "type" "call,branch")
47: [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
48:
49: ;; Define the function unit usages. We first define memory as a unit.
50: (define_function_unit "memory" 1 0 (eq_attr "type" "load") 6 5
51: [(eq_attr "type" "load")])
52: (define_function_unit "memory" 1 0 (eq_attr "type" "load") 6 6
53: [(eq_attr "type" "store")])
54: (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
55:
56: ;; Now define the function units for the floating-point support. Most
57: ;; units are pipelined and can accept an input every cycle.
58: ;;
59: ;; Note that we have an inaccuracy here. If a fmac insn is issued, followed
60: ;; 2 cycles later by a fadd, there will be a conflict for the floating
61: ;; adder that we can't represent. Also, all insns will conflict for the
62: ;; floating-point rounder. It isn't clear how to represent this.
63:
64: (define_function_unit "multiplier" 1 0 (eq_attr "type" "fmul") 3 0)
65: (define_function_unit "multiplier" 1 0 (eq_attr "type" "dmul") 6 4)
66: (define_function_unit "multiplier" 1 0 (eq_attr "type" "fam") 6 0)
67: (define_function_unit "multiplier" 1 0 (eq_attr "type" "dam") 9 4)
68:
69: (define_function_unit "adder" 1 0 (eq_attr "type" "fadd,fam,dam") 3 0)
70:
71: (define_function_unit "divider" 1 0 (eq_attr "type" "fdiv") 11 10)
72: (define_function_unit "divider" 1 0 (eq_attr "type" "fsqrt") 28 27)
73: (define_function_unit "divider" 1 0 (eq_attr "type" "ddiv") 18 17)
74: (define_function_unit "divider" 1 0 (eq_attr "type" "dsqrt") 57 56)
75:
76: ;; ADD
77: (define_insn "addsi3"
78: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
79: (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
80: (match_operand:SI 2 "add_operand" "rI,N")))]
81: ""
82: "@
83: add %0,%1,%2
84: sub %0,%1,%n2")
85:
86: (define_insn "adddi3"
87: [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
88: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
89: (match_operand:DI 2 "gpc_reg_operand" "r")))]
90: ""
91: "add %L0,%L1,%L2\;addc %0,%1,%2"
92: [(set_attr "type" "multi")])
93:
94: ;; AND/ANDN
95: (define_insn "andsi3"
96: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
97: (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
98: (match_operand:SI 2 "and_operand" "rI,K")))]
99: ""
100: "@
101: and %0,%1,%2
102: andn %0,%1,%C2")
103:
104: (define_insn ""
105: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
106: (and:SI (not:SI (match_operand:SI 1 "srcb_operand" "rI"))
107: (match_operand:SI 2 "gpc_reg_operand" "r")))]
108: ""
109: "andn %0,%2,%1")
110:
111:
112: ;; CALLI
113: ;;
114: ;; Start with a subroutine to write out CLOBBERs starting at lr2 up to,
115: ;; but not including, the next parameter register. If operand[0] is null,
116: ;; it means that all the argument registers have been used.
117: (define_expand "clobbers_to"
118: [(clobber (match_operand:SI 0 "" ""))]
119: ""
120: "
121: {
122: int i;
123: int high_regno;
124:
125: if (operands[0] == 0)
126: high_regno = R_LR (18);
127: else if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) < R_LR (0)
128: || REGNO (operands[0]) > R_LR (18))
129: abort ();
130: else
131: high_regno = REGNO (operands[0]);
132:
133: for (i = R_LR (2); i < high_regno; i++)
134: emit_insn (gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, i)));
135:
136: DONE;
137: }")
138:
139: ;; We indicate that LR0 is clobbered in the CALL_INSN itself. Otherwise,
140: ;; reorg will think it is just clobbered by the called function.
141:
142: (define_expand "call"
143: [(parallel [(call (match_operand:SI 0 "" "")
144: (match_operand 1 "" ""))
145: (clobber (scratch:SI))])
146: (match_operand 2 "" "")]
147: ""
148: "
149: {
150: if (GET_CODE (operands[0]) != MEM)
151: abort ();
152:
153: /* We tell here whether this is a recursive call, since this insn may
154: later be inlined into another function. */
155: if (! TARGET_SMALL_MEMORY
156: && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
157: operands[0] = gen_rtx (MEM, SImode,
158: force_reg (Pmode, XEXP (operands[0], 0)));
159:
160: operands[2] = gen_clobbers_to (operands[2]);
161: }")
162:
163: (define_expand "call_value"
164: [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
165: (call (match_operand:SI 1 "" "")
166: (match_operand 2 "" "")))
167: (clobber (scratch:SI))])
168: (match_operand 3 "" "")]
169: ""
170: "
171: {
172: if (GET_CODE (operands[1]) != MEM)
173: abort ();
174:
175: /* We tell here whether this is a recursive call, since this insn may
176: later be inlined into another function. */
177: if (! TARGET_SMALL_MEMORY
178: && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
179: operands[1] = gen_rtx (MEM, SImode,
180: force_reg (Pmode, XEXP (operands[1], 0)));
181:
182: operands[3] = gen_clobbers_to (operands[3]);
183: }")
184:
185: (define_insn ""
186: [(call (match_operand:SI 0 "memory_operand" "m")
187: (match_operand 1 "" ""))
188: (clobber (match_scratch:SI 2 "=&l"))]
189: "GET_CODE (XEXP (operands[0], 0)) != CONST_INT"
190: "calli lr0,%0%#"
191: [(set_attr "type" "call")])
192:
193: (define_insn ""
194: [(call (mem:SI (match_operand:SI 0 "call_operand" "i"))
195: (match_operand:SI 1 "general_operand" "g"))
196: (clobber (match_scratch:SI 2 "=&l"))]
197: ""
198: "call lr0,%F0"
199: [(set_attr "type" "call")])
200:
201: (define_insn ""
202: [(set (match_operand 0 "gpc_reg_operand" "=r")
203: (call (match_operand:SI 1 "memory_operand" "m")
204: (match_operand 2 "" "")))
205: (clobber (match_scratch:SI 3 "=&l"))]
206: "GET_CODE (XEXP (operands[1], 0)) != CONST_INT"
207: "calli lr0,%1%#"
208: [(set_attr "type" "call")])
209:
210: (define_insn ""
211: [(set (match_operand 0 "gpc_reg_operand" "=r")
212: (call (mem:SI (match_operand:SI 1 "call_operand" "i"))
213: (match_operand:SI 2 "general_operand" "g")))
214: (clobber (match_scratch:SI 3 "=&l"))]
215: ""
216: "call lr0,%F1"
217: [(set_attr "type" "call")])
218:
219: (define_expand "probe"
220: [(call (mem:SI (symbol_ref:SI "_msp_check"))
221: (const_int 1))]
222: "TARGET_STACK_CHECK"
223: "")
224:
225: ;; This is used for internal routine calls via TPC. Currently used only
226: ;; in probe, above.
227: (define_insn ""
228: [(call (mem:SI (match_operand:SI 0 "immediate_operand" "s"))
229: (const_int 1))]
230: ""
231: "call %*,%0"
232: [(set_attr "type" "call")])
233:
234: ;; CONST, CONSTH, CONSTN
235: ;;
236: ;; Many of these are generated from move insns.
237: (define_insn ""
238: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
239: (and:SI (match_operand:SI 1 "immediate_operand" "i")
240: (const_int 65535)))]
241: ""
242: "const %0,%1")
243:
244: (define_insn ""
245: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
246: (const_int 16)
247: (match_operand:SI 1 "const_0_operand" ""))
248: (ashiftrt:SI (match_operand:SI 2 "immediate_operand" "i")
249: (const_int 16)))]
250: ""
251: "consth %0,%2")
252:
253: (define_insn ""
254: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
255: (const_int 16)
256: (match_operand:SI 1 "const_0_operand" ""))
257: (match_operand:SI 2 "cint_16_operand" "J"))]
258: ""
259: "consth %0,%m2")
260:
261: (define_insn ""
262: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
263: (ior:SI (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0"))
264: (match_operand:SI 2 "const_int_operand" "n")))]
265: "(INTVAL (operands[2]) & 0xffff) == 0"
266: "consth %0,%2")
267:
268: (define_insn ""
269: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
270: (ior:SI (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0"))
271: (and:SI (match_operand:SI 2 "immediate_operand" "i")
272: (const_int -65536))))]
273: ""
274: "consth %0,%2")
275:
276: ;; CONVERT
277: (define_insn "fix_truncsfsi2"
278: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
279: (fix:SI (match_operand:SF 1 "register_operand" "r")))]
280: ""
281: "convert %0,%1,0,3,0,1")
282:
283: (define_insn "fix_truncdfsi2"
284: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
285: (fix:SI (match_operand:DF 1 "register_operand" "r")))]
286: ""
287: "convert %0,%1,0,3,0,2")
288:
289: (define_insn "fixuns_truncsfsi2"
290: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
291: (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
292: ""
293: "convert %0,%1,1,3,0,1")
294:
295: (define_insn "fixuns_truncdfsi2"
296: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
297: (unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))]
298: ""
299: "convert %0,%1,1,3,0,2")
300:
301: (define_insn "truncdfsf2"
302: [(set (match_operand:SF 0 "register_operand" "=r")
303: (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
304: ""
305: "convert %0,%1,0,4,1,2")
306:
307: (define_insn "extendsfdf2"
308: [(set (match_operand:DF 0 "register_operand" "=r")
309: (float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
310: ""
311: "convert %0,%1,0,4,2,1")
312:
313: (define_insn "floatsisf2"
314: [(set (match_operand:SF 0 "register_operand" "=r")
315: (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
316: ""
317: "convert %0,%1,0,4,1,0")
318:
319: (define_insn "floatsidf2"
320: [(set (match_operand:DF 0 "register_operand" "=r")
321: (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
322: ""
323: "convert %0,%1,0,4,2,0")
324:
325: (define_insn "floatunssisf2"
326: [(set (match_operand:SF 0 "register_operand" "=r")
327: (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
328: ""
329: "convert %0,%1,1,4,1,0")
330:
331: (define_insn "floatunssidf2"
332: [(set (match_operand:DF 0 "register_operand" "=r")
333: (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
334: ""
335: "convert %0,%1,1,4,2,0")
336:
337: ;; CPxxx, DEQ, DGT, DGE, FEQ, FGT, FGE
338: (define_insn ""
339: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
340: (match_operator 3 "comparison_operator"
341: [(match_operand:SI 1 "gpc_reg_operand" "r")
342: (match_operand:SI 2 "srcb_operand" "rI")]))]
343: ""
344: "cp%J3 %0,%1,%2")
345:
346: (define_insn ""
347: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
348: (match_operator 3 "fp_comparison_operator"
349: [(match_operand:SF 1 "register_operand" "r")
350: (match_operand:SF 2 "register_operand" "r")]))]
351: ""
352: "f%J3 %0,%1,%2"
353: [(set_attr "type" "fadd")])
354:
355: (define_insn ""
356: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
357: (match_operator 3 "fp_comparison_operator"
358: [(match_operand:DF 1 "register_operand" "r")
359: (match_operand:DF 2 "register_operand" "r")]))]
360: ""
361: "d%J3 %0,%1,%2"
362: [(set_attr "type" "fadd")])
363:
364: ;; DADD
365: (define_expand "adddf3"
366: [(set (match_operand:DF 0 "register_operand" "")
367: (plus:DF (match_operand:DF 1 "register_operand" "")
368: (match_operand:DF 2 "register_operand" "")))]
369: ""
370: "")
371:
372: (define_insn ""
373: [(set (match_operand:DF 0 "register_operand" "=r")
374: (plus:DF (match_operand:DF 1 "register_operand" "%r")
375: (match_operand:DF 2 "register_operand" "r")))]
376: "! TARGET_29050 "
377: "dadd %0,%1,%2"
378: [(set_attr "type" "fadd")])
379:
380: (define_insn ""
381: [(set (match_operand:DF 0 "register_operand" "=r,a")
382: (plus:DF (match_operand:DF 1 "register_operand" "%r,r")
383: (match_operand:DF 2 "register_operand" "r,0")))]
384: "TARGET_29050"
385: "@
386: dadd %0,%1,%2
387: dmac 8,%0,%1,%1"
388: [(set_attr "type" "fadd,dam")])
389:
390: ;; DDIV
391: (define_insn "divdf3"
392: [(set (match_operand:DF 0 "register_operand" "=r")
393: (div:DF (match_operand:DF 1 "register_operand" "=r")
394: (match_operand:DF 2 "register_operand" "r")))]
395: ""
396: "ddiv %0,%1,%2"
397: [(set_attr "type" "ddiv")])
398:
399: ;; DIVIDE
400: ;;
401: ;; We must set Q to the sign extension of the dividend first. For MOD, we
402: ;; must get the remainder from Q.
403: ;;
404: ;; For divmod: operand 1 is divided by operand 2; quotient goes to operand
405: ;; 0 and remainder to operand 3.
406: (define_expand "divmodsi4"
407: [(set (match_dup 4)
408: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
409: (const_int 31)))
410: (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
411: (div:SI (match_dup 1)
412: (match_operand:SI 2 "gpc_reg_operand" "")))
413: (set (match_operand:SI 3 "gpc_reg_operand" "")
414: (mod:SI (match_dup 1)
415: (match_dup 2)))
416: (use (match_dup 4))])]
417: ""
418: "
419: {
420: operands[4] = gen_reg_rtx (SImode);
421: }")
422:
423: (define_insn ""
424: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
425: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
426: (match_operand:SI 2 "gpc_reg_operand" "r")))
427: (set (match_operand:SI 3 "register_operand" "=q")
428: (mod:SI (match_dup 1)
429: (match_dup 2)))
430: (use (match_operand:SI 4 "register_operand" "3"))]
431: ""
432: "divide %0,%1,%2")
433:
434: ;; DIVIDU
435: ;;
436: ;; Similar to DIVIDE.
437: (define_expand "udivmodsi4"
438: [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
439: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
440: (match_operand:SI 2 "gpc_reg_operand" "")))
441: (set (match_operand:SI 3 "gpc_reg_operand" "")
442: (umod:SI (match_dup 1)
443: (match_dup 2)))
444: (use (const_int 0))])]
445: ""
446: "")
447:
448: (define_insn ""
449: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
450: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
451: (match_operand:SI 2 "gpc_reg_operand" "r")))
452: (set (match_operand:SI 3 "register_operand" "=q")
453: (umod:SI (match_dup 1)
454: (match_dup 2)))
455: (use (match_operand:SI 4 "const_int_operand" "3"))]
456: ""
457: "dividu %0,%1,%2")
458:
459: ;; DMAC/DMSM
460: (define_insn ""
461: [(set (match_operand:DF 0 "register_operand" "=a,*r")
462: (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r,A")
463: (match_operand:DF 2 "register_operand" "r,r"))
464: (match_operand:DF 3 "register_operand" "0,*r")))]
465: "TARGET_29050"
466: "@
467: dmac 0,%0,%1,%2
468: dmsm %0,%2,%3"
469: [(set_attr "type" "dam")])
470:
471: (define_insn ""
472: [(set (match_operand:DF 0 "register_operand" "=a")
473: (plus:DF (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r"))
474: (match_operand:DF 2 "register_operand" "r"))
475: (match_operand:DF 3 "register_operand" "0")))]
476: "TARGET_29050"
477: "dmac 1,%0,%2,%1"
478: [(set_attr "type" "dam")])
479:
480: (define_insn ""
481: [(set (match_operand:DF 0 "register_operand" "=a")
482: (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r")
483: (match_operand:DF 2 "register_operand" "r"))
484: (match_operand:DF 3 "register_operand" "0")))]
485: "TARGET_29050"
486: "dmac 2,%0,%1,%2"
487: [(set_attr "type" "dam")])
488:
489: (define_insn ""
490: [(set (match_operand:DF 0 "register_operand" "=a")
491: (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "r")
492: (neg:DF (match_operand:DF 2 "register_operand" "r")))
493: (match_operand:DF 3 "register_operand" "0")))]
494: "TARGET_29050"
495: "dmac 3,%0,%1,%2"
496: [(set_attr "type" "dam")])
497:
498: (define_insn ""
499: [(set (match_operand:DF 0 "register_operand" "=a")
500: (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r"))
501: (match_operand:DF 2 "register_operand" "r")))]
502: "TARGET_29050"
503: "dmac 5,%0,%2,%1"
504: [(set_attr "type" "dam")])
505:
506: (define_insn ""
507: [(set (match_operand:DF 0 "register_operand" "=a")
508: (minus:DF (neg:DF (match_operand:DF 1 "register_operand" "r"))
509: (match_operand:DF 2 "register_operand" "0")))]
510: "TARGET_29050"
511: "dmac 11,%0,%1,%1"
512: [(set_attr "type" "dam")])
513:
514: (define_insn ""
515: [(set (match_operand:DF 0 "register_operand" "=a")
516: (neg:DF (plus:DF (match_operand:DF 1 "register_operand" "%r")
517: (match_operand:DF 2 "register_operand" "0"))))]
518: "TARGET_29050"
519: "dmac 11,%0,%1,%1"
520: [(set_attr "type" "dam")])
521:
522: (define_insn ""
523: [(set (match_operand:DF 0 "register_operand" "=r,r,a")
524: (neg:DF (match_operand:DF 1 "register_operand" "0,r,r")))
525: (clobber (match_scratch:SI 2 "=&r,&r,X"))]
526: "TARGET_29050"
527: "@
528: cpeq %2,gr1,gr1\;xor %0,%1,%2
529: cpeq %2,gr1,gr1\;xor %0,%1,%2\;sll %L0,%L1,0
530: dmac 13,%0,%1,%1"
531: [(set_attr "type" "multi,multi,dam")])
532:
533: ;; DMUL
534: (define_expand "muldf3"
535: [(set (match_operand:DF 0 "register_operand" "")
536: (mult:DF (match_operand:DF 1 "register_operand" "")
537: (match_operand:DF 2 "register_operand" "")))]
538: ""
539: "")
540:
541: (define_insn ""
542: [(set (match_operand:DF 0 "register_operand" "=r")
543: (mult:DF (match_operand:DF 1 "register_operand" "%r")
544: (match_operand:DF 2 "register_operand" "r")))]
545: "! TARGET_29050"
546: "dmul %0,%1,%2"
547: [(set_attr "type" "dmul")])
548:
549: (define_insn ""
550: [(set (match_operand:DF 0 "register_operand" "=r,a")
551: (mult:DF (match_operand:DF 1 "register_operand" "%r,r")
552: (match_operand:DF 2 "register_operand" "r,r")))]
553: "TARGET_29050"
554: "@
555: dmul %0,%1,%2
556: dmac 4,%0,%1,%2"
557: [(set_attr "type" "dmul,dam")])
558:
559: ;; DSUB
560: (define_expand "subdf3"
561: [(set (match_operand:DF 0 "register_operand" "=r")
562: (minus:DF (match_operand:DF 1 "register_operand" "r")
563: (match_operand:DF 2 "register_operand" "r")))]
564: ""
565: "")
566:
567: (define_insn ""
568: [(set (match_operand:DF 0 "register_operand" "=r")
569: (minus:DF (match_operand:DF 1 "register_operand" "r")
570: (match_operand:DF 2 "register_operand" "r")))]
571: "! TARGET_29050"
572: "dsub %0,%1,%2"
573: [(set_attr "type" "fadd")])
574:
575: (define_insn ""
576: [(set (match_operand:DF 0 "register_operand" "=r,a,a")
577: (minus:DF (match_operand:DF 1 "register_operand" "r,0,r")
578: (match_operand:DF 2 "register_operand" "r,r,0")))]
579: "TARGET_29050"
580: "@
581: dsub %0,%1,%2
582: dmac 9,%0,%2,%2
583: dmac 10,%0,%1,%1"
584: [(set_attr "type" "fadd,dam,dam")])
585:
586: ;; EXBYTE
587: (define_insn ""
588: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
589: (ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI")
590: (const_int -256))
591: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
592: (const_int 8)
593: (ashift:PSI
594: (match_operand:PSI 3 "register_operand" "b")
595: (const_int 3)))))]
596: ""
597: "exbyte %0,%2,%1")
598:
599: (define_insn ""
600: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
601: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
602: (const_int 8)
603: (ashift:PSI
604: (match_operand:PSI 2 "register_operand" "b")
605: (const_int 3))))]
606: ""
607: "exbyte %0,%1,0")
608:
609: (define_insn ""
610: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
611: (const_int 8)
612: (match_operand:PSI 1 "const_24_operand" ""))
613: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
614: (const_int 8)
615: (ashift:PSI
616: (match_operand:PSI 3 "register_operand" "b")
617: (const_int 3))))]
618: ""
619: "exbyte %0,%2,%0")
620:
621: (define_expand "extzv"
622: [(set (match_operand:SI 0 "gpc_reg_operand" "")
623: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
624: (match_operand:SI 2 "general_operand" "")
625: (match_operand:SI 3 "general_operand" "")))]
626: ""
627: "
628: {
629: int size, pos;
630:
631: if (GET_CODE (operands[2]) != CONST_INT
632: || GET_CODE (operands[3]) != CONST_INT)
633: FAIL;
634:
635: size = INTVAL (operands[2]);
636: pos = INTVAL (operands[3]);
637:
638: /* Can't do this unless a byte extraction. If extracting the high
639: or low byte, don't do this because a shift or AND is shorter.
640: Don't do 16-bit extracts, since the only two are the high and low
641: ends, and it is faster to do them with CONSTH and SRL. */
642:
643: if (size != 8 || (pos != 8 && pos != 16))
644: FAIL;
645:
646: operands[3] = gen_rtx (ASHIFT, PSImode,
647: force_reg (PSImode, GEN_INT (pos / 8)),
648: GEN_INT (3));
649:
650: }")
651:
652: ;; EXHW
653: (define_insn ""
654: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
655: (ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI")
656: (const_int -65536))
657: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
658: (const_int 16)
659: (ashift:PSI
660: (match_operand:PSI 3 "register_operand" "b")
661: (const_int 3)))))]
662: ""
663: "exhw %0,%2,%1")
664:
665: (define_insn ""
666: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
667: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
668: (const_int 16)
669: (ashift:PSI
670: (match_operand:PSI 2 "register_operand" "b")
671: (const_int 3))))]
672: ""
673: "exhw %0,%1,0")
674:
675: (define_insn ""
676: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
677: (const_int 16)
678: (match_operand:PSI 1 "const_16_operand" ""))
679: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
680: (const_int 16)
681: (ashift:PSI
682: (match_operand:PSI 3 "register_operand" "b")
683: (const_int 3))))]
684: ""
685: "exhw %0,%2,%0")
686:
687: ;; EXHWS
688: ;;
689: ;; This is probably unused. The high-order 16-bits are obtained with an SRA
690: ;; insn. The low-order 16 bits are a sign-extend, which is a pair of
691: ;; shifts. Setting BP followed by the insn is equivalent, so we don't
692: ;; bother going to any trouble to generate this insn.
693:
694: (define_insn ""
695: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
696: (sign_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
697: (const_int 16)
698: (ashift:PSI
699: (match_operand:PSI 2 "register_operand" "b")
700: (const_int 3))))]
701: ""
702: "exhws %0,%1")
703:
704: ;; EXTRACT
705: (define_insn ""
706: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
707: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
708: (match_operand:PSI 2 "register_operand" "f")))]
709: ""
710: "extract %0,%1,%1")
711:
712: (define_expand "rotlsi3"
713: [(set (match_dup 3)
714: (match_operand:SI 2 "gpc_reg_or_immediate_operand" ""))
715: (set (match_operand:SI 0 "gpc_reg_operand" "")
716: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
717: (match_dup 3)))]
718: ""
719: "
720: { operands[2] = gen_lowpart (PSImode, operands[2]);
721: operands[3] = gen_reg_rtx (PSImode);
722: }")
723:
724: ;; It would be nice to be able to have a define_split corresponding to the
725: ;; above, but there is no way to tell combine we need a PSImode temporary.
726: ;; If we put a (clobber (scratch:PSI)) there, combine would merge the above
727: ;; two insns. This is bad because it then thinks only one insn is needed.
728:
729: ;; FADD
730: (define_expand "addsf3"
731: [(set (match_operand:SF 0 "register_operand" "")
732: (plus:SF (match_operand:SF 1 "register_operand" "")
733: (match_operand:SF 2 "register_operand" "")))]
734: ""
735: "")
736:
737: (define_insn ""
738: [(set (match_operand:SF 0 "register_operand" "=r")
739: (plus:SF (match_operand:SF 1 "register_operand" "%r")
740: (match_operand:SF 2 "register_operand" "r")))]
741: "! TARGET_29050"
742: "fadd %0,%1,%2"
743: [(set_attr "type" "fadd")])
744:
745: (define_insn ""
746: [(set (match_operand:SF 0 "register_operand" "=r,a")
747: (plus:SF (match_operand:SF 1 "register_operand" "%r,r")
748: (match_operand:SF 2 "register_operand" "r,0")))]
749: "TARGET_29050"
750: "@
751: fadd %0,%1,%2
752: fmac 8,%0,%1,%1"
753: [(set_attr "type" "fadd,fam")])
754:
755: ;; FDIV
756: (define_insn "divsf3"
757: [(set (match_operand:SF 0 "register_operand" "=r")
758: (div:SF (match_operand:SF 1 "register_operand" "=r")
759: (match_operand:SF 2 "register_operand" "r")))]
760: ""
761: "fdiv %0,%1,%2"
762: [(set_attr "type" "fdiv")])
763:
764: ;; FDMUL
765: (define_insn ""
766: [(set (match_operand:DF 0 "register_operand" "=r")
767: (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "%r"))
768: (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))]
769: ""
770: "fdmul %0,%1,%2")
771:
772: ;; FMAC/FMSM
773: (define_insn ""
774: [(set (match_operand:SF 0 "register_operand" "=a,*r")
775: (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r,A")
776: (match_operand:SF 2 "register_operand" "r,r"))
777: (match_operand:SF 3 "register_operand" "0,*r")))]
778: "TARGET_29050"
779: "@
780: fmac 0,%0,%1,%2
781: fmsm %0,%2,%3"
782: [(set_attr "type" "fam")])
783:
784: (define_insn ""
785: [(set (match_operand:SF 0 "register_operand" "=a")
786: (plus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
787: (match_operand:SF 2 "register_operand" "r"))
788: (match_operand:SF 3 "register_operand" "0")))]
789: "TARGET_29050"
790: "fmac 1,%0,%2,%1"
791: [(set_attr "type" "fam")])
792:
793: (define_insn ""
794: [(set (match_operand:SF 0 "register_operand" "=a")
795: (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r")
796: (match_operand:SF 2 "register_operand" "r"))
797: (match_operand:SF 3 "register_operand" "0")))]
798: "TARGET_29050"
799: "fmac 2,%0,%1,%2"
800: [(set_attr "type" "fam")])
801:
802: (define_insn ""
803: [(set (match_operand:SF 0 "register_operand" "=a")
804: (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
805: (match_operand:SF 2 "register_operand" "r"))
806: (match_operand:SF 3 "register_operand" "0")))]
807: "TARGET_29050"
808: "fmac 3,%0,%2,%1"
809: [(set_attr "type" "fam")])
810:
811: (define_insn ""
812: [(set (match_operand:SF 0 "register_operand" "=a")
813: (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
814: (match_operand:SF 2 "register_operand" "r")))]
815: "TARGET_29050"
816: "fmac 5,%0,%2,%1"
817: [(set_attr "type" "fam")])
818:
819: (define_insn ""
820: [(set (match_operand:SF 0 "register_operand" "=a")
821: (minus:SF (neg:SF (match_operand:SF 1 "register_operand" "%r"))
822: (match_operand:SF 2 "register_operand" "0")))]
823: "TARGET_29050"
824: "fmac 11,%0,%1,%1"
825: [(set_attr "type" "fam")])
826:
827: (define_insn ""
828: [(set (match_operand:SF 0 "register_operand" "=a")
829: (neg:SF (plus:SF (match_operand:SF 1 "register_operand" "%r")
830: (match_operand:SF 2 "register_operand" "0"))))]
831: "TARGET_29050"
832: "fmac 11,%0,%1,%1"
833: [(set_attr "type" "fam")])
834:
835: (define_insn ""
836: [(set (match_operand:SF 0 "register_operand" "=r,a")
837: (neg:SF (match_operand:SF 1 "register_operand" "r,r")))
838: (clobber (match_scratch:SI 2 "=&r,X"))]
839: "TARGET_29050"
840: "@
841: cpeq %2,gr1,gr1\;xor %0,%1,%2
842: fmac 13,%0,%1,%1"
843: [(set_attr "type" "multi,fam")])
844:
845: ;; FMUL
846: (define_expand "mulsf3"
847: [(set (match_operand:SF 0 "register_operand" "")
848: (mult:SF (match_operand:SF 1 "register_operand" "")
849: (match_operand:SF 2 "register_operand" "")))]
850: ""
851: "")
852:
853: (define_insn ""
854: [(set (match_operand:SF 0 "register_operand" "=r")
855: (mult:SF (match_operand:SF 1 "register_operand" "%r")
856: (match_operand:SF 2 "register_operand" "r")))]
857: "! TARGET_29050"
858: "fmul %0,%1,%2"
859: [(set_attr "type" "fmul")])
860:
861: (define_insn ""
862: [(set (match_operand:SF 0 "register_operand" "=r,a")
863: (mult:SF (match_operand:SF 1 "register_operand" "%r,r")
864: (match_operand:SF 2 "register_operand" "r,r")))]
865: "TARGET_29050"
866: "@
867: fmul %0,%1,%2
868: fmac 4,%0,%1,%2"
869: [(set_attr "type" "fmul,fam")])
870:
871: ;; FSUB
872: (define_expand "subsf3"
873: [(set (match_operand:SF 0 "register_operand" "")
874: (minus:SF (match_operand:SF 1 "register_operand" "")
875: (match_operand:SF 2 "register_operand" "")))]
876: ""
877: "")
878:
879: (define_insn ""
880: [(set (match_operand:SF 0 "register_operand" "=r")
881: (minus:SF (match_operand:SF 1 "register_operand" "r")
882: (match_operand:SF 2 "register_operand" "r")))]
883: "! TARGET_29050"
884: "fsub %0,%1,%2"
885: [(set_attr "type" "fadd")])
886:
887: (define_insn ""
888: [(set (match_operand:SF 0 "register_operand" "=r,a,a")
889: (minus:SF (match_operand:SF 1 "register_operand" "r,0,r")
890: (match_operand:SF 2 "register_operand" "r,r,0")))]
891: "TARGET_29050"
892: "@
893: fsub %0,%1,%2
894: fmac 9,%0,%2,%2
895: fmac 10,%0,%1,%1"
896: [(set_attr "type" "fadd,fam,fam")])
897:
898: ;; INBYTE
899: (define_insn ""
900: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
901: (const_int 8)
902: (ashift:PSI
903: (match_operand:PSI 2 "register_operand" "b")
904: (const_int 3)))
905: (match_operand:SI 1 "srcb_operand" "rI"))]
906: ""
907: "inbyte %0,%0,%1")
908:
909: (define_insn ""
910: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
911: (ior:SI (and:SI
912: (not:SI
913: (ashift:SI (const_int 255)
914: (ashift:PSI
915: (match_operand:PSI 3 "register_operand" "b")
916: (const_int 3))))
917: (match_operand:SI 1 "gpc_reg_operand" "r"))
918: (ashift:SI (zero_extend:SI
919: (match_operand:QI 2 "srcb_operand" "rI"))
920: (ashift:PSI (match_dup 3) (const_int 3)))))]
921: ""
922: "inbyte %0,%1,%2")
923:
924: ;; INHW
925: (define_insn ""
926: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
927: (const_int 16)
928: (ashift:PSI
929: (match_operand:PSI 2 "register_operand" "b")
930: (const_int 3)))
931: (match_operand:SI 1 "srcb_operand" "rI"))]
932: ""
933: "inhw %0,%0,%1")
934:
935: (define_insn ""
936: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
937: (ior:SI (and:SI
938: (not:SI
939: (ashift:SI (const_int 65535)
940: (ashift:PSI
941: (match_operand:PSI 3 "register_operand" "b")
942: (const_int 3))))
943: (match_operand:SI 1 "gpc_reg_operand" "r"))
944: (ashift:SI (zero_extend:SI
945: (match_operand:HI 2 "srcb_operand" "rI"))
946: (ashift:PSI (match_dup 3) (const_int 3)))))]
947: ""
948: "inhw %0,%1,%2")
949:
950: (define_expand "insv"
951: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "")
952: (match_operand:SI 1 "general_operand" "")
953: (match_operand:SI 2 "general_operand" ""))
954: (match_operand:SI 3 "srcb_operand" ""))]
955: ""
956: "
957: {
958: int size, pos;
959:
960: if (GET_CODE (operands[1]) != CONST_INT
961: || GET_CODE (operands[2]) != CONST_INT)
962: FAIL;
963:
964: size = INTVAL (operands[1]);
965: pos = INTVAL (operands[2]);
966: if ((size != 8 && size != 16) || pos % size != 0)
967: FAIL;
968:
969: operands[2] = gen_rtx (ASHIFT, PSImode,
970: force_reg (PSImode, GEN_INT (pos / 8)),
971: GEN_INT (3));
972: }")
973:
974: ;; LOAD (also used by move insn).
975: (define_insn ""
976: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
977: (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
978: (const_int -4))))
979: (set (match_operand:PSI 2 "register_operand" "=b")
980: (truncate:PSI (match_dup 1)))]
981: "! TARGET_DW_ENABLE"
982: "load 0,16,%0,%1"
983: [(set_attr "type" "load")])
984:
985: (define_insn ""
986: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
987: (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
988: "TARGET_DW_ENABLE"
989: "load 0,1,%0,%1"
990: [(set_attr "type" "load")])
991:
992: (define_insn ""
993: [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
994: (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
995: "TARGET_DW_ENABLE"
996: "load 0,1,%0,%1"
997: [(set_attr "type" "load")])
998:
999: (define_insn ""
1000: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1001: (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
1002: "TARGET_DW_ENABLE"
1003: "load 0,2,%0,%1"
1004: [(set_attr "type" "load")])
1005:
1006: (define_insn ""
1007: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1008: (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))
1009: (clobber (match_scratch:PSI 2 "=&b"))]
1010: "TARGET_DW_ENABLE"
1011: "load 0,17,%0,%1"
1012: [(set_attr "type" "load")])
1013:
1014: (define_insn ""
1015: [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
1016: (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))
1017: (clobber (match_scratch:PSI 2 "=&b"))]
1018: "TARGET_DW_ENABLE"
1019: "load 0,17,%0,%1"
1020: [(set_attr "type" "load")])
1021:
1022: (define_insn ""
1023: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1024: (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))
1025: (clobber (match_scratch:PSI 2 "=&b"))]
1026: "TARGET_DW_ENABLE"
1027: "load 0,18,%0,%1"
1028: [(set_attr "type" "load")])
1029:
1030: ;; LOADM
1031: (define_expand "load_multiple"
1032: [(set (match_dup 4)
1033: (match_operand:PSI 2 "const_int_operand" ""))
1034: (match_par_dup 3 [(set (match_operand:SI 0 "" "")
1035: (match_operand:SI 1 "" ""))])]
1036: ""
1037: "
1038: {
1039: int regno;
1040: int count;
1041: rtx from;
1042: int i;
1043:
1044: /* Support only loading a constant number of hard registers from memory. */
1045: if (GET_CODE (operands[2]) != CONST_INT
1046: || operands[2] == const1_rtx
1047: || GET_CODE (operands[1]) != MEM
1048: || GET_CODE (operands[0]) != REG
1049: || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
1050: FAIL;
1051:
1052: count = INTVAL (operands[2]);
1053: regno = REGNO (operands[0]);
1054:
1055: /* CR gets set to the number of registers minus one. */
1056: operands[2] = GEN_INT(count - 1);
1057:
1058: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 2));
1059: from = memory_address (SImode, XEXP (operands[1], 0));
1060: XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode,
1061: gen_rtx (REG, SImode, regno),
1062: gen_rtx (MEM, SImode, from));
1063: operands[4] = gen_reg_rtx (PSImode);
1064:
1065: XVECEXP (operands[3], 0, 1) = gen_rtx (USE, VOIDmode, operands[4]);
1066: XVECEXP (operands[3], 0, 2) = gen_rtx (CLOBBER, VOIDmode, operands[4]);
1067:
1068: for (i = 1; i < count; i++)
1069: XVECEXP (operands[3], 0, i + 2)
1070: = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
1071: gen_rtx (MEM, SImode, plus_constant (from, i * 4)));
1072: }")
1073:
1074: ;; Indicate that CR is used and is then clobbered.
1075: (define_insn ""
1076: [(set (match_operand 0 "gpc_reg_operand" "=r")
1077: (match_operand 1 "memory_operand" "m"))
1078: (use (match_operand:PSI 2 "register_operand" "+c"))
1079: (clobber (match_dup 2))]
1080: "GET_MODE (operands[0]) == GET_MODE (operands[1])
1081: && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD"
1082: "loadm 0,0,%0,%1"
1083: [(set_attr "type" "load")])
1084:
1085: (define_insn ""
1086: [(match_parallel 0 "load_multiple_operation"
1087: [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
1088: (match_operand:SI 2 "memory_operand" "m"))
1089: (use (match_operand:PSI 3 "register_operand" "+c"))
1090: (clobber (match_dup 3))])]
1091: ""
1092: "loadm 0,0,%1,%2"
1093: [(set_attr "type" "load")])
1094:
1095: ;; MTSR (used also by move insn)
1096: (define_insn ""
1097: [(set (match_operand:SI 0 "spec_reg_operand" "=*h,*h")
1098: (and:SI (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i")
1099: (match_operand:SI 2 "const_int_operand" "n,n")))]
1100: "masks_bits_for_special (operands[0], operands[2])"
1101: "@
1102: mtsr %0,%1
1103: mtsrim %0,%1")
1104:
1105: (define_insn ""
1106: [(set (match_operand:PSI 0 "register_operand" "=h,h")
1107: (truncate:PSI
1108: (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i")))]
1109: ""
1110: "@
1111: mtsr %0,%1
1112: mtsrim %0,%1")
1113:
1114: ;; MULTIPLY, MULTM, MULTMU
1115: (define_insn "mulsi3"
1116: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1117: (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1118: (match_operand:SI 2 "gpc_reg_operand" "r")))
1119: (clobber (match_scratch:SI 3 "=&q"))]
1120: ""
1121: "multiply %0,%1,%2")
1122:
1123: (define_insn ""
1124: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1125: (subreg:SI
1126: (mult:DI
1127: (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1128: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0))
1129: (clobber (match_scratch:SI 3 "=&q"))]
1130: ""
1131: "multm %0,%1,%2")
1132:
1133: (define_insn ""
1134: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1135: (subreg:SI
1136: (mult:DI
1137: (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1138: (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0))
1139: (clobber (match_scratch:SI 3 "=&q"))]
1140: ""
1141: "multmu %0,%1,%2")
1142:
1143: (define_insn "mulsidi3"
1144: [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1145: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1146: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
1147: (clobber (match_scratch:SI 3 "=&q"))]
1148: ""
1149: "multiply %L0,%1,%2\;multm %0,%1,%2"
1150: [(set_attr "type" "multi")])
1151:
1152: (define_split
1153: [(set (match_operand:DI 0 "gpc_reg_operand" "")
1154: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1155: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))
1156: (clobber (reg:SI 180))]
1157: "reload_completed"
1158: [(parallel [(set (match_dup 3)
1159: (mult:SI (match_dup 1) (match_dup 2)))
1160: (clobber (reg:SI 180))])
1161: (parallel [(set (match_dup 4)
1162: (subreg:SI (mult:DI
1163: (sign_extend:DI (match_dup 1))
1164: (sign_extend:DI (match_dup 2))) 0))
1165: (clobber (reg:SI 180))])]
1166: "
1167: { operands[3] = operand_subword (operands[0], 1, 1, DImode);
1168: operands[4] = operand_subword (operands[1], 0, 1, DImode); } ")
1169:
1170: (define_insn "umulsidi3"
1171: [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1172: (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1173: (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
1174: (clobber (match_scratch:SI 3 "=&q"))]
1175: ""
1176: "multiplu %L0,%1,%2\;multmu %0,%1,%2"
1177: [(set_attr "type" "multi")])
1178:
1179: (define_split
1180: [(set (match_operand:DI 0 "gpc_reg_operand" "")
1181: (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1182: (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))
1183: (clobber (reg:SI 180))]
1184: "reload_completed"
1185: [(parallel [(set (match_dup 3)
1186: (mult:SI (match_dup 1) (match_dup 2)))
1187: (clobber (reg:SI 180))])
1188: (parallel [(set (match_dup 4)
1189: (subreg:SI (mult:DI (zero_extend:DI (match_dup 1))
1190: (zero_extend:DI (match_dup 2))) 0))
1191: (clobber (reg:SI 180))])]
1192: "
1193: { operands[3] = operand_subword (operands[0], 1, 1, DImode);
1194: operands[4] = operand_subword (operands[1], 0, 1, DImode); } ")
1195:
1196: ;; NAND
1197: (define_insn ""
1198: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1199: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1200: (not:SI (match_operand:SI 2 "srcb_operand" "rI"))))]
1201: ""
1202: "nand %0,%1,%2")
1203:
1204: (define_insn ""
1205: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1206: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1207: (match_operand:SI 2 "const_int_operand" "K")))]
1208: "((unsigned) ~ INTVAL (operands[2])) < 256"
1209: "nand %0,%1,%C2")
1210:
1211: ;; NOR
1212: (define_insn ""
1213: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1214: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1215: (not:SI (match_operand:SI 2 "srcb_operand" "rI"))))]
1216: ""
1217: "nor %0,%1,%2")
1218:
1219: (define_insn ""
1220: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1221: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1222: (match_operand:SI 2 "const_int_operand" "K")))]
1223: "((unsigned) ~ INTVAL (operands[2])) < 256"
1224: "nor %0,%1,%C2")
1225:
1226: (define_insn "one_cmplsi2"
1227: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1228: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1229: ""
1230: "nor %0,%1,0")
1231:
1232: ;; OR/ORN
1233: (define_expand "iorsi3"
1234: [(set (match_operand:SI 0 "gpc_reg_operand" "")
1235: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1236: (match_operand:SI 2 "srcb_operand" "")))]
1237: ""
1238: "")
1239:
1240: (define_insn ""
1241: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1242: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1243: (match_operand:SI 2 "srcb_operand" "rI")))]
1244: "! TARGET_29050"
1245: "or %0,%1,%2")
1246:
1247: (define_insn ""
1248: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1249: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1250: (match_operand:SI 2 "srcb_operand" "rI,K")))]
1251: "TARGET_29050"
1252: "@
1253: or %0,%1,%2
1254: orn %0,%1,%C2")
1255:
1256:
1257: ;; SLL (also used by move insn)
1258: (define_insn "nop"
1259: [(const_int 0)]
1260: ""
1261: "aseq 0x40,gr1,gr1")
1262:
1263: (define_insn "ashlsi3"
1264: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1265: (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1266: (match_operand:QI 2 "srcb_operand" "rn")))]
1267: ""
1268: "sll %0,%1,%Q2")
1269:
1270: ;; SQRT
1271: (define_insn "sqrtsf2"
1272: [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
1273: (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
1274: "TARGET_29050"
1275: "sqrt %0,%1,1"
1276: [(set_attr "type" "fsqrt")])
1277:
1278: (define_insn "sqrtdf2"
1279: [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
1280: (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
1281: "TARGET_29050"
1282: "sqrt %0,%1,2"
1283: [(set_attr "type" "dsqrt")])
1284:
1285: ;; SRA
1286: (define_insn "ashrsi3"
1287: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1288: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1289: (match_operand:QI 2 "srcb_operand" "rn")))]
1290: ""
1291: "sra %0,%1,%Q2")
1292:
1293: ;; SRL
1294: (define_insn "lshrsi3"
1295: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1296: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1297: (match_operand:QI 2 "srcb_operand" "rn")))]
1298: ""
1299: "srl %0,%1,%Q2")
1300:
1301: ;; STORE
1302: ;;
1303: ;; These somewhat bogus patterns exist to set OPT = 001/010 for partial-word
1304: ;; stores on systems with DW not set.
1305: (define_insn ""
1306: [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r")
1307: (const_int -4)))
1308: (match_operand:SI 1 "gpc_reg_operand" "r"))]
1309: "! TARGET_DW_ENABLE"
1310: "store 0,1,%1,%0"
1311: [(set_attr "type" "store")])
1312:
1313: (define_insn ""
1314: [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r")
1315: (const_int -3)))
1316: (match_operand:SI 1 "gpc_reg_operand" "r"))]
1317: "! TARGET_DW_ENABLE"
1318: "store 0,2,%1,%0"
1319: [(set_attr "type" "store")])
1320:
1321: ;; STOREM
1322: (define_expand "store_multiple"
1323: [(use (match_operand 0 "" ""))
1324: (use (match_operand 1 "" ""))
1325: (use (match_operand 2 "" ""))]
1326: ""
1327: "
1328: { rtx pat;
1329:
1330: if (TARGET_NO_STOREM_BUG)
1331: pat = gen_store_multiple_no_bug (operands[0], operands[1], operands[2]);
1332: else
1333: pat = gen_store_multiple_bug (operands[0], operands[1], operands[2]);
1334:
1335: if (pat)
1336: emit_insn (pat);
1337: else
1338: FAIL;
1339:
1340: DONE;
1341: }")
1342:
1343: (define_expand "store_multiple_no_bug"
1344: [(set (match_dup 4)
1345: (match_operand:PSI 2 "const_int_operand" ""))
1346: (match_par_dup 3 [(set (match_operand:SI 0 "" "")
1347: (match_operand:SI 1 "" ""))])]
1348: ""
1349: "
1350: {
1351: int regno;
1352: int count;
1353: rtx from;
1354: int i;
1355:
1356: /* Support only storing a constant number of hard registers to memory. */
1357: if (GET_CODE (operands[2]) != CONST_INT
1358: || operands[2] == const1_rtx
1359: || GET_CODE (operands[0]) != MEM
1360: || GET_CODE (operands[1]) != REG
1361: || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
1362: FAIL;
1363:
1364: count = INTVAL (operands[2]);
1365: regno = REGNO (operands[1]);
1366:
1367: /* CR gets set to the number of registers minus one. */
1368: operands[2] = GEN_INT(count - 1);
1369:
1370: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 2));
1371: from = memory_address (SImode, XEXP (operands[0], 0));
1372: XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode,
1373: gen_rtx (MEM, SImode, from),
1374: gen_rtx (REG, SImode, regno));
1375: operands[4] = gen_reg_rtx (PSImode);
1376: XVECEXP (operands[3], 0, 1) = gen_rtx (USE, VOIDmode, operands[4]);
1377: XVECEXP (operands[3], 0, 2) = gen_rtx (CLOBBER, VOIDmode, operands[4]);
1378:
1379: for (i = 1; i < count; i++)
1380: XVECEXP (operands[3], 0, i + 2)
1381: = gen_rtx (SET, VOIDmode,
1382: gen_rtx (MEM, SImode, plus_constant (from, i * 4)),
1383: gen_rtx (REG, SImode, regno + i));
1384: }")
1385:
1386: (define_expand "store_multiple_bug"
1387: [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
1388: (match_operand:SI 1 "" ""))
1389: (use (match_operand:SI 2 "" ""))])]
1390: ""
1391: "
1392: {
1393: int regno;
1394: int count;
1395: rtx from;
1396: int i;
1397:
1398: /* Support only storing a constant number of hard registers to memory. */
1399: if (GET_CODE (operands[2]) != CONST_INT
1400: || operands[2] == const1_rtx
1401: || GET_CODE (operands[0]) != MEM
1402: || GET_CODE (operands[1]) != REG
1403: || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
1404: FAIL;
1405:
1406: count = INTVAL (operands[2]);
1407: regno = REGNO (operands[1]);
1408:
1409: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1));
1410: from = memory_address (SImode, XEXP (operands[0], 0));
1411: XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode,
1412: gen_rtx (MEM, SImode, from),
1413: gen_rtx (REG, SImode, regno));
1414: XVECEXP (operands[3], 0, 1)
1415: = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, PSImode));
1416:
1417: for (i = 1; i < count; i++)
1418: XVECEXP (operands[3], 0, i + 1)
1419: = gen_rtx (SET, VOIDmode,
1420: gen_rtx (MEM, SImode, plus_constant (from, i * 4)),
1421: gen_rtx (REG, SImode, regno + i));
1422: }")
1423:
1424: (define_insn ""
1425: [(set (match_operand 0 "memory_operand" "=m")
1426: (match_operand 1 "gpc_reg_operand" "r"))
1427: (clobber (match_scratch:PSI 2 "=&c"))]
1428: "!TARGET_NO_STOREM_BUG
1429: && GET_MODE (operands[0]) == GET_MODE (operands[1])
1430: && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD"
1431: "mtsrim cr,%S1\;storem 0,0,%1,%0"
1432: [(set_attr "type" "multi")])
1433:
1434: (define_insn ""
1435: [(match_parallel 0 "store_multiple_operation"
1436: [(set (match_operand:SI 1 "memory_operand" "=m")
1437: (match_operand:SI 2 "gpc_reg_operand" "r"))
1438: (clobber (match_scratch:PSI 3 "=&c"))])]
1439: "!TARGET_NO_STOREM_BUG"
1440: "mtsrim cr,%V0\;storem 0,0,%2,%1"
1441: [(set_attr "type" "multi")])
1442:
1443: (define_insn ""
1444: [(set (match_operand 0 "memory_operand" "=m")
1445: (match_operand 1 "gpc_reg_operand" "r"))
1446: (use (match_operand:PSI 2 "register_operand" "+c"))
1447: (clobber (match_dup 2))]
1448: "TARGET_NO_STOREM_BUG
1449: && GET_MODE (operands[0]) == GET_MODE (operands[1])
1450: && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD"
1451: "storem 0,0,%1,%0"
1452: [(set_attr "type" "store")])
1453:
1454: (define_insn ""
1455: [(match_parallel 0 "store_multiple_operation"
1456: [(set (match_operand:SI 1 "memory_operand" "=m")
1457: (match_operand:SI 2 "gpc_reg_operand" "r"))
1458: (use (match_operand:PSI 3 "register_operand" "+c"))
1459: (clobber (match_dup 3))])]
1460: "TARGET_NO_STOREM_BUG"
1461: "storem 0,0,%2,%1"
1462: [(set_attr "type" "store")])
1463:
1464: ;; SUB
1465: ;;
1466: ;; Either operand can be a register or an 8-bit constant, but both cannot be
1467: ;; constants (can't usually occur anyway).
1468: (define_expand "subsi3"
1469: [(set (match_operand:SI 0 "gpc_reg_operand" "")
1470: (minus:SI (match_operand:SI 1 "srcb_operand" "")
1471: (match_operand:SI 2 "srcb_operand" "")))]
1472: ""
1473: "
1474: {
1475: if (GET_CODE (operands[0]) == CONST_INT
1476: && GET_CODE (operands[1]) == CONST_INT)
1477: operands[1] = force_reg (SImode, operands[1]);
1478: }")
1479:
1480: (define_insn ""
1481: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1482: (minus:SI (match_operand:SI 1 "srcb_operand" "r,I")
1483: (match_operand:SI 2 "srcb_operand" "rI,r")))]
1484: "register_operand (operands[1], SImode)
1485: || register_operand (operands[2], SImode)"
1486: "@
1487: sub %0,%1,%2
1488: subr %0,%2,%1")
1489:
1490: (define_insn "subdi3"
1491: [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1492: (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
1493: (match_operand:DI 2 "gpc_reg_operand" "r")))]
1494: ""
1495: "sub %L0,%L1,%L2\;subc %0,%1,%2"
1496: [(set_attr "type" "multi")])
1497:
1498: ;; SUBR (also used above in SUB)
1499: (define_insn "negdi2"
1500: [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1501: (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
1502: ""
1503: "subr %L0,%L1,0\;subrc %0,%1,0"
1504: [(set_attr "type" "multi")])
1505:
1506: (define_insn "negsi2"
1507: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1508: (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1509: ""
1510: "subr %0,%1,0")
1511:
1512: ;; XNOR
1513: (define_insn ""
1514: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1515: (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1516: (match_operand:SI 2 "srcb_operand" "rI"))))]
1517: ""
1518: "xnor %0,%1,%2")
1519:
1520: ;; XOR
1521: (define_insn "xorsi3"
1522: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1523: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1524: (match_operand:SI 2 "srcb_operand" "rI")))]
1525: ""
1526: "xor %0,%1,%2")
1527:
1528: ;; Can use XOR to negate floating-point values, but we are better off not doing
1529: ;; it that way on the 29050 so it can combine with the fmac insns.
1530: (define_expand "negsf2"
1531: [(parallel [(set (match_operand:SF 0 "register_operand" "")
1532: (neg:SF (match_operand:SF 1 "register_operand" "")))
1533: (clobber (match_scratch:SI 2 ""))])]
1534: ""
1535: "
1536: {
1537: rtx result;
1538: rtx target;
1539:
1540: if (! TARGET_29050)
1541: {
1542: target = operand_subword_force (operands[0], 0, SFmode);
1543: result = expand_binop (SImode, xor_optab,
1544: operand_subword_force (operands[1], 0, SFmode),
1545: GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
1546: if (result == 0)
1547: abort ();
1548:
1549: if (result != target)
1550: emit_move_insn (result, target);
1551:
1552: /* Make a place for REG_EQUAL. */
1553: emit_move_insn (operands[0], operands[0]);
1554: DONE;
1555: }
1556: }")
1557:
1558: (define_expand "negdf2"
1559: [(parallel [(set (match_operand:DF 0 "register_operand" "")
1560: (neg:DF (match_operand:DF 1 "register_operand" "")))
1561: (clobber (match_scratch:SI 2 ""))])]
1562: ""
1563: "
1564: {
1565: rtx result;
1566: rtx target;
1567: rtx insns;
1568:
1569: if (! TARGET_29050)
1570: {
1571: start_sequence ();
1572: target = operand_subword (operands[0], 0, 1, DFmode);
1573: result = expand_binop (SImode, xor_optab,
1574: operand_subword_force (operands[1], 0, DFmode),
1575: GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
1576: if (result == 0)
1577: abort ();
1578:
1579: if (result != target)
1580: emit_move_insn (result, target);
1581:
1582: emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
1583: operand_subword_force (operands[1], 1, DFmode));
1584:
1585: insns = get_insns ();
1586: end_sequence ();
1587:
1588: emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
1589: DONE;
1590: }
1591: }")
1592:
1593: ;; Sign extend and truncation operations.
1594: (define_insn "zero_extendqihi2"
1595: [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
1596: (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1597: ""
1598: "and %0,%1,255")
1599:
1600: (define_insn "zero_extendqisi2"
1601: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1602: (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1603: ""
1604: "and %0,%1,255")
1605:
1606: (define_insn "zero_extendhisi2"
1607: [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1608: (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0")))]
1609: ""
1610: "consth %0,0")
1611:
1612: (define_expand "extendqihi2"
1613: [(set (match_dup 2)
1614: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1615: (const_int 24)))
1616: (set (match_operand:HI 0 "gpc_reg_operand" "")
1617: (ashiftrt:SI (match_dup 2)
1618: (const_int 24)))]
1619: ""
1620: "
1621: { operands[0] = gen_lowpart (SImode, operands[0]);
1622: operands[1] = gen_lowpart (SImode, operands[1]);
1623: operands[2] = gen_reg_rtx (SImode); }")
1624:
1625: (define_expand "extendqisi2"
1626: [(set (match_dup 2)
1627: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1628: (const_int 24)))
1629: (set (match_operand:SI 0 "gpc_reg_operand" "")
1630: (ashiftrt:SI (match_dup 2)
1631: (const_int 24)))]
1632: ""
1633: "
1634: { operands[1] = gen_lowpart (SImode, operands[1]);
1635: operands[2] = gen_reg_rtx (SImode); }")
1636:
1637: (define_expand "extendhisi2"
1638: [(set (match_dup 2)
1639: (ashift:SI (match_operand:HI 1 "gpc_reg_operand" "")
1640: (const_int 16)))
1641: (set (match_operand:SI 0 "gpc_reg_operand" "")
1642: (ashiftrt:SI (match_dup 2)
1643: (const_int 16)))]
1644: ""
1645: "
1646: { operands[1] = gen_lowpart (SImode, operands[1]);
1647: operands[2] = gen_reg_rtx (SImode); }")
1648:
1649: ;; Define the methods used to move data around.
1650: ;;
1651: ;; movsi:
1652: ;;
1653: ;; If storing into memory, force source into register.
1654: (define_expand "movsi"
1655: [(set (match_operand:SI 0 "general_operand" "")
1656: (match_operand:SI 1 "general_operand" ""))]
1657: ""
1658: "
1659: {
1660: if (GET_CODE (operands[0]) == MEM && ! gpc_reg_operand (operands[1], SImode))
1661: operands[1] = copy_to_mode_reg (SImode, operands[1]);
1662: else if (spec_reg_operand (operands[0], SImode)
1663: && ! (register_operand (operands[1], SImode)
1664: || cint_16_operand (operands[1], SImode)))
1665: operands[1] = force_reg (SImode, operands[1]);
1666: }")
1667:
1668: (define_expand "movpsi"
1669: [(set (match_operand:PSI 0 "general_operand" "")
1670: (match_operand:PSI 1 "general_operand" ""))]
1671: ""
1672: "
1673: {
1674: if (GET_CODE (operands[0]) == MEM
1675: && ! gpc_reg_operand (operands[1], PSImode))
1676: operands[1] = copy_to_mode_reg (PSImode, operands[1]);
1677: else if (spec_reg_operand (operands[0], PSImode)
1678: && ! (register_operand (operands[1], PSImode)
1679: || cint_16_operand (operands[1], PSImode)))
1680: operands[1] = force_reg (PSImode, operands[1]);
1681: }")
1682:
1683: (define_split
1684: [(set (match_operand:SI 0 "gpc_reg_operand" "")
1685: (match_operand:SI 1 "long_const_operand" ""))]
1686: ""
1687: [(set (match_dup 0)
1688: (and:SI (match_dup 1)
1689: (const_int 65535)))
1690: (set (match_dup 0)
1691: (ior:SI (zero_extend:SI (match_dup 2))
1692: (and:SI (match_dup 1)
1693: (const_int -65536))))]
1694: " operands[2] = gen_lowpart (HImode, operands[0]); ")
1695:
1696: ;; Subroutines to load/store halfwords. Operands 0 and 1 are the output and
1697: ;; input, respectively, except that the address is passed for a MEM instead
1698: ;; of the MEM itself and the short item is passed in QImode.
1699: ;;
1700: ;; Operand 2 is a scratch general register and operand 3 is a scratch register
1701: ;; used for BP. When called before reload, pseudos are passed for both
1702: ;; operands. During reload, R_TAV is used for the general register, and
1703: ;; a reload register of class BR_REGS (R_VP) for BP.
1704: ;;
1705: ;; We have two versions of the store operations, for when halfword writes are
1706: ;; supported and when they are not.
1707: (define_expand "loadhi"
1708: [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "")
1709: (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
1710: (const_int -4))))
1711: (set (match_operand:PSI 3 "register_operand" "")
1712: (truncate:PSI (match_dup 1)))])
1713: (set (match_operand:SI 0 "gpc_reg_operand" "")
1714: (zero_extract:SI (match_dup 2)
1715: (const_int 16)
1716: (ashift:PSI (match_dup 3) (const_int 3))))]
1717: ""
1718: "")
1719:
1720: (define_expand "storehinhww"
1721: [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "")
1722: (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "")
1723: (const_int -4))))
1724: (set (match_operand:PSI 3 "register_operand" "")
1725: (truncate:PSI (match_dup 0)))])
1726: (set (zero_extract:SI (match_dup 2)
1727: (const_int 16)
1728: (ashift:PSI (match_dup 3) (const_int 3)))
1729: (match_operand:SI 1 "gpc_reg_operand" ""))
1730: (set (mem:SI (match_dup 0))
1731: (match_dup 2))]
1732: ""
1733: "")
1734:
1735: (define_expand "storehihww"
1736: [(set (match_operand:PSI 3 "register_operand" "")
1737: (truncate:PSI (match_operand:SI 0 "gpc_reg_operand" "")))
1738: (set (match_operand:SI 2 "gpc_reg_operand" "")
1739: (ior:SI (and:SI (not:SI (ashift:SI (const_int 65535)
1740: (ashift:PSI (match_dup 3)
1741: (const_int 3))))
1742: (match_operand:SI 1 "gpc_reg_operand" ""))
1743: (ashift:SI (zero_extend:SI (match_dup 4))
1744: (ashift:PSI (match_dup 3) (const_int 3)))))
1745: (set (mem:SI (and:SI (match_dup 0)
1746: (const_int -3)))
1747: (match_dup 2))]
1748: ""
1749: "
1750: { operands[4] = gen_lowpart (HImode, operands[1]); }")
1751:
1752: (define_expand "movhi"
1753: [(set (match_operand:HI 0 "general_operand" "")
1754: (match_operand:HI 1 "general_operand" ""))]
1755: ""
1756: "
1757: { if (GET_CODE (operands[0]) == MEM)
1758: {
1759: if (! gpc_reg_operand (operands[1], HImode))
1760: operands[1] = copy_to_mode_reg (HImode, operands[1]);
1761: if (! TARGET_DW_ENABLE)
1762: {
1763: rtx general = gen_reg_rtx (SImode);
1764: rtx bp = gen_reg_rtx (PSImode);
1765: rtx (*fcn) ()
1766: = TARGET_BYTE_WRITES ? gen_storehihww : gen_storehinhww;
1767: rtx seq = (*fcn) (XEXP (operands[0], 0),
1768: gen_lowpart (SImode, operands[1]),
1769: general, bp);
1770:
1771: a29k_set_memflags (seq, operands[0]);
1772: emit_insn (seq);
1773: DONE;
1774: }
1775: }
1776: else if (GET_CODE (operands[1]) == MEM)
1777: {
1778: if (! TARGET_DW_ENABLE)
1779: {
1780: rtx general = gen_reg_rtx (SImode);
1781: rtx bp = gen_reg_rtx (PSImode);
1782: rtx seq = gen_loadqi (gen_lowpart (SImode, operands[0]),
1783: XEXP (operands[1], 0), general, bp);
1784:
1785: a29k_set_memflags (seq, operands[1]);
1786: emit_insn (seq);
1787: DONE;
1788: }
1789: }
1790: }")
1791:
1792: (define_expand "reload_inhi"
1793: [(parallel [(match_operand:SI 0 "register_operand" "=r")
1794: (match_operand:SI 1 "reload_memory_operand" "m")
1795: (match_operand:PSI 2 "register_operand" "=b")])]
1796: "! TARGET_DW_ENABLE"
1797: "
1798: { rtx seq = gen_loadhi (gen_lowpart (SImode, operands[0]),
1799: a29k_get_reloaded_address (operands[1]),
1800: gen_rtx (REG, SImode, R_TAV),
1801: operands[2]);
1802:
1803: a29k_set_memflags (seq, operands[1]);
1804: emit_insn (seq);
1805: DONE;
1806: }")
1807:
1808: (define_expand "reload_outhi"
1809: [(parallel [(match_operand:SI 0 "reload_memory_operand" "=m")
1810: (match_operand:SI 1 "register_operand" "m")
1811: (match_operand:PSI 2 "register_operand" "=b")])]
1812: "! TARGET_DW_ENABLE"
1813: "
1814: { rtx (*fcn) () = TARGET_BYTE_WRITES ? gen_storehihww : gen_storehinhww;
1815: rtx seq = (*fcn) (a29k_get_reloaded_address (operands[0]),
1816: gen_lowpart (SImode, operands[1]),
1817: gen_rtx (REG, SImode, R_TAV), operands[2]);
1818:
1819: a29k_set_memflags (seq, operands[0]);
1820: emit_insn (seq);
1821: DONE;
1822: }")
1823:
1824: ;; Subroutines to load/store bytes. Operands 0 and 1 are the output and
1825: ;; input, respectively, except that the address is passed for a MEM instead
1826: ;; of the MEM itself and the short item is passed in QImode.
1827: ;;
1828: ;; Operand 2 is a scratch general register and operand 3 is a scratch register
1829: ;; used for BP. When called before reload, pseudos are passed for both
1830: ;; operands. During reload, R_TAV is used for the general register, and
1831: ;; a reload register of class BR_REGS (R_VP) for BP.
1832: ;;
1833: ;; We have two versions of the store operations, for when byte writes are
1834: ;; supported and when they are not.
1835: (define_expand "loadqi"
1836: [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "")
1837: (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
1838: (const_int -4))))
1839: (set (match_operand:PSI 3 "register_operand" "")
1840: (truncate:PSI (match_dup 1)))])
1841: (set (match_operand:SI 0 "gpc_reg_operand" "")
1842: (zero_extract:SI (match_dup 2)
1843: (const_int 8)
1844: (ashift:PSI (match_dup 3) (const_int 3))))]
1845: ""
1846: "")
1847:
1848: (define_expand "storeqinhww"
1849: [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "")
1850: (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "")
1851: (const_int -4))))
1852: (set (match_operand:PSI 3 "register_operand" "")
1853: (truncate:PSI (match_dup 0)))])
1854: (set (zero_extract:SI (match_dup 2)
1855: (const_int 8)
1856: (ashift:PSI (match_dup 3)
1857: (const_int 3)))
1858: (match_operand:SI 1 "gpc_reg_operand" ""))
1859: (set (mem:SI (match_dup 0))
1860: (match_dup 2))]
1861: ""
1862: "")
1863:
1864: (define_expand "storeqihww"
1865: [(set (match_operand:PSI 3 "register_operand" "")
1866: (truncate:PSI (match_operand:SI 0 "gpc_reg_operand" "")))
1867: (set (match_operand:SI 2 "gpc_reg_operand" "")
1868: (ior:SI (and:SI (not:SI (ashift:SI (const_int 255)
1869: (ashift:PSI (match_dup 3)
1870: (const_int 3))))
1871: (match_operand:SI 1 "gpc_reg_operand" ""))
1872: (ashift:SI (zero_extend:SI (match_dup 4))
1873: (ashift:PSI (match_dup 3)
1874: (const_int 3)))))
1875: (set (mem:SI (and:SI (match_dup 0)
1876: (const_int -4)))
1877: (match_dup 2))]
1878: ""
1879: "
1880: { operands[4] = gen_lowpart (QImode, operands[1]); }")
1881:
1882: (define_expand "movqi"
1883: [(set (match_operand:QI 0 "general_operand" "")
1884: (match_operand:QI 1 "general_operand" ""))]
1885: ""
1886: "
1887: { if (GET_CODE (operands[0]) == MEM)
1888: {
1889: if (! gpc_reg_operand (operands[1], QImode))
1890: operands[1] = copy_to_mode_reg (QImode, operands[1]);
1891: if (! TARGET_DW_ENABLE)
1892: {
1893: rtx general = gen_reg_rtx (SImode);
1894: rtx bp = gen_reg_rtx (PSImode);
1895: rtx (*fcn) ()
1896: = TARGET_BYTE_WRITES ? gen_storeqihww : gen_storeqinhww;
1897: rtx seq = (*fcn) (XEXP (operands[0], 0),
1898: gen_lowpart (SImode, operands[1]),
1899: general, bp);
1900:
1901: a29k_set_memflags (seq, operands[0]);
1902: emit_insn (seq);
1903: }
1904: }
1905: else if (GET_CODE (operands[1]) == MEM)
1906: {
1907: if (! TARGET_DW_ENABLE)
1908: {
1909: rtx general = gen_reg_rtx (SImode);
1910: rtx bp = gen_reg_rtx (PSImode);
1911: rtx seq = gen_loadqi (gen_lowpart (SImode, operands[0]),
1912: XEXP (operands[1], 0), general, bp);
1913:
1914: a29k_set_memflags (seq, operands[1]);
1915: emit_insn (seq);
1916: DONE;
1917: }
1918: }
1919: }")
1920:
1921: (define_expand "reload_inqi"
1922: [(parallel [(match_operand:SI 0 "register_operand" "=r")
1923: (match_operand:SI 1 "reload_memory_operand" "m")
1924: (match_operand:PSI 2 "register_operand" "=b")])]
1925: "! TARGET_DW_ENABLE"
1926: "
1927: { rtx seq = gen_loadqi (gen_lowpart (SImode, operands[0]),
1928: a29k_get_reloaded_address (operands[1]),
1929: gen_rtx (REG, SImode, R_TAV),
1930: operands[2]);
1931:
1932: a29k_set_memflags (seq, operands[1]);
1933: emit_insn (seq);
1934: DONE;
1935: }")
1936:
1937: (define_expand "reload_outqi"
1938: [(parallel [(match_operand:SI 0 "reload_memory_operand" "=m")
1939: (match_operand:SI 1 "register_operand" "m")
1940: (match_operand:PSI 2 "register_operand" "=b")])]
1941: "! TARGET_DW_ENABLE"
1942: "
1943: { rtx (*fcn) () = TARGET_BYTE_WRITES ? gen_storeqihww : gen_storeqinhww;
1944: rtx seq = (*fcn) (a29k_get_reloaded_address (operands[0]),
1945: gen_lowpart (SImode, operands[1]),
1946: gen_rtx (REG, SImode, R_TAV), operands[2]);
1947:
1948: a29k_set_memflags (seq, operands[0]);
1949: emit_insn (seq);
1950: DONE;
1951: }")
1952:
1953: ;; Now the actual insns used to move data around. We include here the
1954: ;; DEFINE_SPLITs that may be needed. In some cases these will be
1955: ;; split again. For floating-point, if we can look inside the constant,
1956: ;; always split it. This can eliminate unnecessary insns.
1957: (define_insn ""
1958: [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m")
1959: (match_operand:SF 1 "in_operand" "r,E,F,m,r"))]
1960: "(gpc_reg_operand (operands[0], SFmode)
1961: || gpc_reg_operand (operands[1], SFmode))
1962: && ! TARGET_29050"
1963: "@
1964: sll %0,%1,0
1965: #
1966: const %0,%1\;consth %0,%1
1967: load 0,0,%0,%1
1968: store 0,0,%1,%0"
1969: [(set_attr "type" "misc,multi,multi,load,store")])
1970:
1971: (define_insn ""
1972: [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m,*a,r")
1973: (match_operand:SF 1 "in_operand" "r,E,F,m,r,r,*a"))]
1974: "(gpc_reg_operand (operands[0], SFmode)
1975: || gpc_reg_operand (operands[1], SFmode))
1976: && TARGET_29050"
1977: "@
1978: sll %0,%1,0
1979: #
1980: const %0,%1\;consth %0,%1
1981: load 0,0,%0,%1
1982: store 0,0,%1,%0
1983: mtacc %1,1,%0
1984: mfacc %0,1,%1"
1985: [(set_attr "type" "misc,multi,multi,load,store,fadd,fadd")])
1986:
1987: ;; Turn this into SImode. It will then be split up that way.
1988: (define_split
1989: [(set (match_operand:SF 0 "register_operand" "")
1990: (match_operand:SF 1 "float_const_operand" ""))]
1991: "HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT"
1992: [(set (match_dup 0)
1993: (match_dup 1))]
1994: "
1995: { operands[0] = operand_subword (operands[0], 0, 0, SFmode);
1996: operands[1] = operand_subword (operands[1], 0, 0, SFmode);
1997:
1998: if (operands[0] == 0 || operands[1] == 0)
1999: FAIL;
2000: }")
2001:
2002: (define_insn ""
2003: [(set (match_operand:DF 0 "out_operand" "=?r,?r,r,m")
2004: (match_operand:DF 1 "in_operand" "rE,F,m,r"))
2005: (clobber (match_scratch:PSI 2 "=X,X,&c,&c"))]
2006: "(gpc_reg_operand (operands[0], DFmode)
2007: || gpc_reg_operand (operands[1], DFmode))
2008: && ! TARGET_29050"
2009: "@
2010: #
2011: const %0,%1\;consth %0,%1\;const %L0,%L1\;consth %L0,%L1
2012: mtsrim cr,1\;loadm 0,0,%0,%1
2013: mtsrim cr,1\;storem 0,0,%1,%0"
2014: [(set_attr "type" "multi")])
2015:
2016: (define_insn ""
2017: [(set (match_operand:DF 0 "out_operand" "=?r,?r,r,m,?*a,?r")
2018: (match_operand:DF 1 "in_operand" "rE,F,m,r,r,*a"))
2019: (clobber (match_scratch:PSI 2 "=X,X,&c,&c,X,X"))]
2020: "(gpc_reg_operand (operands[0], DFmode)
2021: || gpc_reg_operand (operands[1], DFmode))
2022: && TARGET_29050"
2023: "@
2024: #
2025: const %0,%1\;consth %0,%1\;const %L0,%L1\;consth %L0,%L1
2026: mtsrim cr,1\;loadm 0,0,%0,%1
2027: mtsrim cr,1\;storem 0,0,%1,%0
2028: mtacc %1,2,%0
2029: mfacc %0,2,%1"
2030: [(set_attr "type" "multi,multi,multi,multi,fadd,fadd")])
2031:
2032: ;; Split register-register copies and constant loads into two SImode loads,
2033: ;; one for each word. In the constant case, they will get further split.
2034: ;; Don't so this until register allocation, though, since it will
2035: ;; interfere with register allocation. Normally copy the lowest-addressed
2036: ;; word first; the exception is if we are copying register to register and
2037: ;; the lowest register of the first operand is the highest register of the
2038: ;; second operand.
2039: (define_split
2040: [(set (match_operand:DF 0 "gpc_reg_operand" "")
2041: (match_operand:DF 1 "gpc_reg_or_float_constant_operand" ""))
2042: (clobber (match_scratch:PSI 2 ""))]
2043: "reload_completed"
2044: [(set (match_dup 3) (match_dup 4))
2045: (set (match_dup 5) (match_dup 6))]
2046: "
2047: { if (GET_CODE (operands[1]) == REG
2048: && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2049: {
2050: operands[3] = operand_subword (operands[0], 1, 1, DFmode);
2051: operands[4] = operand_subword (operands[1], 1, 1, DFmode);
2052: operands[5] = operand_subword (operands[0], 0, 1, DFmode);
2053: operands[6] = operand_subword (operands[1], 0, 1, DFmode);
2054: }
2055: else
2056: {
2057: operands[3] = operand_subword (operands[0], 0, 1, DFmode);
2058: operands[4] = operand_subword (operands[1], 0, 1, DFmode);
2059: operands[5] = operand_subword (operands[0], 1, 1, DFmode);
2060: operands[6] = operand_subword (operands[1], 1, 1, DFmode);
2061: }
2062:
2063: if (operands[3] == 0 || operands[4] == 0
2064: || operands[5] == 0 || operands[6] == 0)
2065: FAIL;
2066: }")
2067:
2068: ;; Split memory loads and stores into the MTSR and LOADM/STOREM.
2069: (define_split
2070: [(set (match_operand:DF 0 "out_operand" "")
2071: (match_operand:DF 1 "in_operand" ""))
2072: (clobber (reg:PSI 179))]
2073: "TARGET_NO_STOREM_BUG
2074: && (memory_operand (operands[0], DFmode)
2075: || memory_operand (operands[1], DFmode))"
2076: [(set (reg:PSI 179) (const_int 1))
2077: (parallel [(set (match_dup 0) (match_dup 1))
2078: (use (reg:PSI 179))
2079: (clobber (reg:PSI 179))])]
2080: "")
2081:
2082: ;; DI move is similar to DF move.
2083: (define_insn ""
2084: [(set (match_operand:DI 0 "out_operand" "=?r,r,m")
2085: (match_operand:DI 1 "in_operand" "rn,m,r"))
2086: (clobber (match_scratch:PSI 2 "=X,&c,&c"))]
2087: "(gpc_reg_operand (operands[0], DImode)
2088: || gpc_reg_operand (operands[1], DImode))"
2089: "@
2090: #
2091: mtsrim cr,1\;loadm 0,0,%0,%1
2092: mtsrim cr,1\;storem 0,0,%1,%0"
2093: [(set_attr "type" "multi")])
2094:
2095: (define_split
2096: [(set (match_operand:DI 0 "gpc_reg_operand" "")
2097: (match_operand:DI 1 "gpc_reg_or_integer_constant_operand" ""))
2098: (clobber (match_scratch:PSI 2 ""))]
2099: "reload_completed"
2100: [(set (match_dup 3) (match_dup 4))
2101: (set (match_dup 5) (match_dup 6))]
2102: "
2103: { if (GET_CODE (operands[1]) == REG
2104: && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2105: {
2106: operands[3] = operand_subword (operands[0], 1, 1, DImode);
2107: operands[4] = operand_subword (operands[1], 1, 1, DImode);
2108: operands[5] = operand_subword (operands[0], 0, 1, DImode);
2109: operands[6] = operand_subword (operands[1], 0, 1, DImode);
2110: }
2111: else
2112: {
2113: operands[3] = operand_subword (operands[0], 0, 1, DImode);
2114: operands[4] = operand_subword (operands[1], 0, 1, DImode);
2115: operands[5] = operand_subword (operands[0], 1, 1, DImode);
2116: operands[6] = operand_subword (operands[1], 1, 1, DImode);
2117: }
2118: }")
2119:
2120: (define_split
2121: [(set (match_operand:DI 0 "out_operand" "")
2122: (match_operand:DI 1 "in_operand" ""))
2123: (clobber (reg:PSI 179))]
2124: "TARGET_NO_STOREM_BUG
2125: && (memory_operand (operands[0], DImode)
2126: || memory_operand (operands[1], DImode))"
2127: [(set (reg:PSI 179) (const_int 1))
2128: (parallel [(set (match_dup 0) (match_dup 1))
2129: (use (reg:PSI 179))
2130: (clobber (reg:PSI 179))])]
2131: "")
2132:
2133: ;; TImode moves are very similar to DImode moves, except that we can't
2134: ;; have constants.
2135: (define_insn ""
2136: [(set (match_operand:TI 0 "out_operand" "=?r,r,m")
2137: (match_operand:TI 1 "in_operand" "r,m,r"))
2138: (clobber (match_scratch:PSI 2 "=X,&c,&c"))]
2139: "(gpc_reg_operand (operands[0], TImode)
2140: || gpc_reg_operand (operands[1], TImode))"
2141: "@
2142: #
2143: mtsrim cr,3\;loadm 0,0,%0,%1
2144: mtsrim cr,3\;storem 0,0,%1,%0"
2145: [(set_attr "type" "multi,multi,multi")])
2146:
2147: (define_split
2148: [(set (match_operand:TI 0 "gpc_reg_operand" "")
2149: (match_operand:TI 1 "gpc_reg_operand" ""))
2150: (clobber (match_scratch:PSI 2 ""))]
2151: "reload_completed"
2152: [(set (match_dup 3) (match_dup 4))
2153: (set (match_dup 5) (match_dup 6))
2154: (set (match_dup 7) (match_dup 8))
2155: (set (match_dup 9) (match_dup 10))]
2156: "
2157: {
2158: if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
2159: && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
2160: {
2161: operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 3);
2162: operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 3);
2163: operands[5] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2);
2164: operands[6] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
2165: operands[7] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
2166: operands[8] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2167: operands[9] = gen_rtx (REG, SImode, REGNO (operands[0]));
2168: operands[10] = gen_rtx (REG, SImode, REGNO (operands[1]));
2169: }
2170: else
2171: {
2172: operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]));
2173: operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]));
2174: operands[5] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
2175: operands[6] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2176: operands[7] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2);
2177: operands[8] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
2178: operands[9] = gen_rtx (REG, SImode, REGNO (operands[0]) + 3);
2179: operands[10] = gen_rtx (REG, SImode, REGNO (operands[1]) + 3);
2180: }
2181: }")
2182:
2183: (define_split
2184: [(set (match_operand:TI 0 "out_operand" "")
2185: (match_operand:TI 1 "in_operand" ""))
2186: (clobber (reg:PSI 179))]
2187: "TARGET_NO_STOREM_BUG
2188: && (memory_operand (operands[0], TImode)
2189: || memory_operand (operands[1], TImode))"
2190: [(set (reg:PSI 179) (const_int 3))
2191: (parallel [(set (match_dup 0) (match_dup 1))
2192: (use (reg:PSI 179))
2193: (clobber (reg:PSI 179))])]
2194: "")
2195:
2196: (define_insn ""
2197: [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h")
2198: (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))]
2199: "(gpc_reg_operand (operands[0], SImode)
2200: || gpc_reg_operand (operands[1], SImode)
2201: || (spec_reg_operand (operands[0], SImode)
2202: && cint_16_operand (operands[1], SImode)))
2203: && ! TARGET_29050"
2204: "@
2205: sll %0,%1,0
2206: const %0,%1
2207: constn %0,%M1
2208: cpeq %0,gr1,gr1
2209: #
2210: load 0,0,%0,%1
2211: mfsr %0,%1
2212: store 0,0,%1,%0
2213: mtsr %0,%1
2214: mtsrim %0,%1"
2215: [(set_attr "type" "misc,misc,misc,misc,multi,load,misc,store,misc,misc")])
2216:
2217: (define_insn ""
2218: [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h")
2219: (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))]
2220: "(gpc_reg_operand (operands[0], SImode)
2221: || gpc_reg_operand (operands[1], SImode)
2222: || (spec_reg_operand (operands[0], SImode)
2223: && cint_16_operand (operands[1], SImode)))
2224: && TARGET_29050"
2225: "@
2226: sll %0,%1,0
2227: const %0,%1
2228: constn %0,%M1
2229: consthz %0,%1
2230: #
2231: load 0,0,%0,%1
2232: mfsr %0,%1
2233: store 0,0,%1,%0
2234: mtsr %0,%1
2235: mtsrim %0,%1"
2236: [(set_attr "type" "misc,misc,misc,misc,multi,load,misc,store,misc,misc")])
2237:
2238: (define_insn ""
2239: [(set (match_operand:PSI 0 "out_operand" "=*r,*r,*r,*r,m,h,h")
2240: (match_operand:PSI 1 "in_operand" "r,i,m,h,r,r,J"))]
2241: "(gpc_reg_operand (operands[0], PSImode)
2242: || gpc_reg_operand (operands[1], PSImode)
2243: || (spec_reg_operand (operands[0], PSImode)
2244: && cint_16_operand (operands[1], PSImode)))"
2245: "@
2246: sll %0,%1,0
2247: const %0,%1
2248: load 0,0,%0,%1
2249: mfsr %0,%1
2250: store 0,0,%1,%0
2251: mtsr %0,%1
2252: mtsrim %0,%1"
2253: [(set_attr "type" "misc,multi,load,misc,store,misc,misc")])
2254:
2255: (define_insn ""
2256: [(set (match_operand:HI 0 "out_operand" "=r,r,r,m,r,*h,*h")
2257: (match_operand:HI 1 "in_operand" "r,i,m,r,*h,r,i"))]
2258: "gpc_reg_operand (operands[0], HImode)
2259: || gpc_reg_operand (operands[1], HImode)
2260: || (spec_reg_operand (operands[0], HImode)
2261: && cint_16_operand (operands[1], HImode))"
2262: "@
2263: sll %0,%1,0
2264: const %0,%1
2265: load 0,2,%0,%1
2266: store 0,2,%1,%0
2267: mfsr %0,%1
2268: mtsr %0,%1
2269: mtsrim %0,%1"
2270: [(set_attr "type" "misc,misc,load,store,misc,misc,misc")])
2271:
2272: (define_insn ""
2273: [(set (match_operand:QI 0 "out_operand" "=r,r,r,m,r,*h,*h")
2274: (match_operand:QI 1 "in_operand" "r,i,m,r,*h,r,i"))]
2275: "gpc_reg_operand (operands[0], QImode)
2276: || gpc_reg_operand (operands[1], QImode)
2277: || (spec_reg_operand (operands[0], HImode)
2278: && cint_16_operand (operands[1], HImode))"
2279: "@
2280: sll %0,%1,0
2281: const %0,%1
2282: load 0,1,%0,%1
2283: store 0,1,%1,%0
2284: mfsr %0,%1
2285: mtsr %0,%1
2286: mtsrim %0,%1"
2287: [(set_attr "type" "misc,misc,load,store,misc,misc,misc")])
2288:
2289: ;; Define move insns for DI, TI, SF, and DF.
2290: ;;
2291: ;; In no case do we support mem->mem directly.
2292: ;;
2293: ;; For DI move of constant to register, split apart at this time since these
2294: ;; can require anywhere from 2 to 4 insns and determining which is complex.
2295: ;;
2296: ;; In other cases, handle similarly to SImode moves.
2297: ;;
2298: ;; However, indicate that DI, TI, and DF moves may clobber CR (reg 179).
2299: (define_expand "movdi"
2300: [(parallel [(set (match_operand:DI 0 "general_operand" "")
2301: (match_operand:DI 1 "general_operand" ""))
2302: (clobber (scratch:PSI))])]
2303: ""
2304: "
2305: {
2306: if (GET_CODE (operands[0]) == MEM)
2307: operands[1] = force_reg (DImode, operands[1]);
2308: }")
2309:
2310: (define_expand "movsf"
2311: [(set (match_operand:SF 0 "general_operand" "")
2312: (match_operand:SF 1 "general_operand" ""))]
2313: ""
2314: "
2315: { if (GET_CODE (operands[0]) == MEM)
2316: operands[1] = force_reg (SFmode, operands[1]);
2317: }")
2318:
2319: (define_expand "movdf"
2320: [(parallel [(set (match_operand:DF 0 "general_operand" "")
2321: (match_operand:DF 1 "general_operand" ""))
2322: (clobber (scratch:PSI))])]
2323: ""
2324: "
2325: { if (GET_CODE (operands[0]) == MEM)
2326: operands[1] = force_reg (DFmode, operands[1]);
2327: }")
2328:
2329: (define_expand "movti"
2330: [(parallel [(set (match_operand:TI 0 "general_operand" "")
2331: (match_operand:TI 1 "general_operand" ""))
2332: (clobber (scratch:PSI))])]
2333: ""
2334: "
2335: {
2336: if (GET_CODE (operands[0]) == MEM)
2337: operands[1] = force_reg (TImode, operands[1]);
2338:
2339: /* We can't handle constants in general because there is no rtl to represent
2340: 128 bit constants. Splitting happens to work for CONST_INTs so we split
2341: them for good code. Other constants will get forced to memory. */
2342:
2343: if (GET_CODE (operands[1]) == CONST_INT)
2344: {
2345: rtx part0, part1, part2, part3;
2346:
2347: part0 = operand_subword (operands[0], 0, 1, TImode);
2348: part1 = operand_subword (operands[0], 1, 1, TImode);
2349: part2 = operand_subword (operands[0], 2, 1, TImode);
2350: part3 = operand_subword (operands[0], 3, 1, TImode);
2351:
2352: emit_move_insn (part0, const0_rtx);
2353: emit_move_insn (part1, const0_rtx);
2354: emit_move_insn (part2, const0_rtx);
2355: emit_move_insn (part3, const0_rtx);
2356:
2357: DONE;
2358: }
2359: else if (CONSTANT_P (operands[1]))
2360: {
2361: operands[1] = force_const_mem (TImode, operands[1]);
2362: if (! memory_address_p (TImode, XEXP (operands[1], 0))
2363: && ! reload_in_progress)
2364: operands[1] = change_address (operands[1], TImode,
2365: XEXP (operands[1], 0));
2366: }
2367: }")
2368:
2369: ;; Here are the variants of the above for use during reload.
2370:
2371: (define_expand "reload_indf"
2372: [(parallel [(set (match_operand:DF 0 "register_operand" "=r")
2373: (match_operand:DF 1 "reload_memory_operand" "m"))
2374: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
2375: ""
2376: "")
2377:
2378: (define_expand "reload_outdf"
2379: [(parallel [(set (match_operand:DF 0 "reload_memory_operand" "=m")
2380: (match_operand:DF 1 "register_operand" "r"))
2381: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
2382: ""
2383: "")
2384:
2385: (define_expand "reload_indi"
2386: [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
2387: (match_operand:DI 1 "reload_memory_operand" "m"))
2388: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
2389: ""
2390: "")
2391:
2392: (define_expand "reload_outdi"
2393: [(parallel [(set (match_operand:DI 0 "reload_memory_operand" "=m")
2394: (match_operand:DI 1 "register_operand" "r"))
2395: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
2396: ""
2397: "")
2398:
2399: (define_expand "reload_inti"
2400: [(parallel [(set (match_operand:TI 0 "register_operand" "=r")
2401: (match_operand:TI 1 "reload_memory_operand" "m"))
2402: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
2403: ""
2404: "")
2405:
2406: (define_expand "reload_outti"
2407: [(parallel [(set (match_operand:TI 0 "reload_memory_operand" "=m")
2408: (match_operand:TI 1 "register_operand" "r"))
2409: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
2410: ""
2411: "")
2412:
2413: ;; For compare operations, we simply store the comparison operands and
2414: ;; do nothing else. The following branch or scc insn will output whatever
2415: ;; is needed.
2416: (define_expand "cmpsi"
2417: [(set (cc0)
2418: (compare (match_operand:SI 0 "gpc_reg_operand" "")
2419: (match_operand:SI 1 "srcb_operand" "")))]
2420: ""
2421: "
2422: {
2423: a29k_compare_op0 = operands[0];
2424: a29k_compare_op1 = operands[1];
2425: a29k_compare_fp_p = 0;
2426: DONE;
2427: }")
2428:
2429: (define_expand "cmpsf"
2430: [(set (cc0)
2431: (compare (match_operand:SF 0 "gpc_reg_operand" "")
2432: (match_operand:SF 1 "gpc_reg_operand" "")))]
2433: ""
2434: "
2435: {
2436: a29k_compare_op0 = operands[0];
2437: a29k_compare_op1 = operands[1];
2438: a29k_compare_fp_p = 1;
2439: DONE;
2440: }")
2441:
2442: (define_expand "cmpdf"
2443: [(set (cc0)
2444: (compare (match_operand:DF 0 "gpc_reg_operand" "")
2445: (match_operand:DF 1 "gpc_reg_operand" "")))]
2446: ""
2447: "
2448: {
2449: a29k_compare_op0 = operands[0];
2450: a29k_compare_op1 = operands[1];
2451: a29k_compare_fp_p = 1;
2452: DONE;
2453: }")
2454:
2455: ;; We can generate bit-tests better if we use NE instead of EQ, but we
2456: ;; don't have an NE for floating-point. So we have to have two patterns
2457: ;; for EQ and two for NE.
2458:
2459: (define_expand "beq"
2460: [(set (match_dup 1) (ne:SI (match_dup 2) (match_dup 3)))
2461: (set (pc)
2462: (if_then_else (ge (match_dup 1) (const_int 0))
2463: (label_ref (match_operand 0 "" ""))
2464: (pc)))]
2465: ""
2466: "
2467: {
2468: if (GET_MODE_CLASS (GET_MODE (a29k_compare_op0)) == MODE_FLOAT)
2469: {
2470: emit_insn (gen_beq_fp (operands[0]));
2471: DONE;
2472: }
2473:
2474: operands[1] = gen_reg_rtx (SImode);
2475: operands[2] = a29k_compare_op0;
2476: operands[3] = a29k_compare_op1;
2477: }")
2478:
2479: (define_expand "beq_fp"
2480: [(set (match_dup 1) (eq:SI (match_dup 2) (match_dup 3)))
2481: (set (pc)
2482: (if_then_else (lt (match_dup 1) (const_int 0))
2483: (label_ref (match_operand 0 "" ""))
2484: (pc)))]
2485: ""
2486: "
2487: {
2488: operands[1] = gen_reg_rtx (SImode);
2489: operands[2] = a29k_compare_op0;
2490: operands[3] = a29k_compare_op1;
2491: }")
2492:
2493: (define_expand "bne"
2494: [(set (match_dup 1) (ne:SI (match_dup 2) (match_dup 3)))
2495: (set (pc)
2496: (if_then_else (lt (match_dup 1) (const_int 0))
2497: (label_ref (match_operand 0 "" ""))
2498: (pc)))]
2499: ""
2500: "
2501: {
2502: if (GET_MODE_CLASS (GET_MODE (a29k_compare_op0)) == MODE_FLOAT)
2503: {
2504: emit_insn (gen_bne_fp (operands[0]));
2505: DONE;
2506: }
2507:
2508: operands[1] = gen_reg_rtx (SImode);
2509: operands[2] = a29k_compare_op0;
2510: operands[3] = a29k_compare_op1;
2511: }")
2512:
2513: (define_expand "bne_fp"
2514: [(set (match_dup 1) (eq:SI (match_dup 2) (match_dup 3)))
2515: (set (pc)
2516: (if_then_else (ge (match_dup 1) (const_int 0))
2517: (label_ref (match_operand 0 "" ""))
2518: (pc)))]
2519: ""
2520: "
2521: {
2522: operands[1] = gen_reg_rtx (SImode);
2523: operands[2] = a29k_compare_op0;
2524: operands[3] = a29k_compare_op1;
2525: }")
2526:
2527: ;; We don't have a floating-point "lt" insn, so we have to use "gt" in that
2528: ;; case with the operands swapped. The operands must both be registers in
2529: ;; the floating-point case, so we know that swapping them is OK.
2530: (define_expand "blt"
2531: [(set (match_dup 1) (match_dup 2))
2532: (set (pc)
2533: (if_then_else (lt (match_dup 1) (const_int 0))
2534: (label_ref (match_operand 0 "" ""))
2535: (pc)))]
2536: ""
2537: "
2538: {
2539: operands[1] = gen_reg_rtx (SImode);
2540: if (a29k_compare_fp_p)
2541: operands[2] = gen_rtx (GT, SImode, a29k_compare_op1, a29k_compare_op0);
2542: else
2543: operands[2] = gen_rtx (LT, SImode, a29k_compare_op0, a29k_compare_op1);
2544: }")
2545:
2546: ;; Similarly for "le".
2547: (define_expand "ble"
2548: [(set (match_dup 1) (match_dup 2))
2549: (set (pc)
2550: (if_then_else (lt (match_dup 1) (const_int 0))
2551: (label_ref (match_operand 0 "" ""))
2552: (pc)))]
2553: ""
2554: "
2555: {
2556: operands[1] = gen_reg_rtx (SImode);
2557: if (a29k_compare_fp_p)
2558: operands[2] = gen_rtx (GE, SImode, a29k_compare_op1, a29k_compare_op0);
2559: else
2560: operands[2] = gen_rtx (LE, SImode, a29k_compare_op0, a29k_compare_op1);
2561: }")
2562:
2563: (define_expand "bltu"
2564: [(set (match_dup 1) (ltu:SI (match_dup 2) (match_dup 3)))
2565: (set (pc)
2566: (if_then_else (lt (match_dup 1) (const_int 0))
2567: (label_ref (match_operand 0 "" ""))
2568: (pc)))]
2569: ""
2570: "
2571: {
2572: operands[1] = gen_reg_rtx (SImode);
2573: operands[2] = a29k_compare_op0;
2574: operands[3] = a29k_compare_op1;
2575: }")
2576:
2577: (define_expand "bleu"
2578: [(set (match_dup 1) (leu:SI (match_dup 2) (match_dup 3)))
2579: (set (pc)
2580: (if_then_else (lt (match_dup 1) (const_int 0))
2581: (label_ref (match_operand 0 "" ""))
2582: (pc)))]
2583: ""
2584: "
2585: {
2586: operands[1] = gen_reg_rtx (SImode);
2587: operands[2] = a29k_compare_op0;
2588: operands[3] = a29k_compare_op1;
2589: }")
2590:
2591: (define_expand "bgt"
2592: [(set (match_dup 1) (gt:SI (match_dup 2) (match_dup 3)))
2593: (set (pc)
2594: (if_then_else (lt (match_dup 1) (const_int 0))
2595: (label_ref (match_operand 0 "" ""))
2596: (pc)))]
2597: ""
2598: "
2599: {
2600: operands[1] = gen_reg_rtx (SImode);
2601: operands[2] = a29k_compare_op0;
2602: operands[3] = a29k_compare_op1;
2603: }")
2604:
2605: (define_expand "bge"
2606: [(set (match_dup 1) (ge:SI (match_dup 2) (match_dup 3)))
2607: (set (pc)
2608: (if_then_else (lt (match_dup 1) (const_int 0))
2609: (label_ref (match_operand 0 "" ""))
2610: (pc)))]
2611: ""
2612: "
2613: {
2614: operands[1] = gen_reg_rtx (SImode);
2615: operands[2] = a29k_compare_op0;
2616: operands[3] = a29k_compare_op1;
2617: }")
2618:
2619: (define_expand "bgtu"
2620: [(set (match_dup 1) (gtu:SI (match_dup 2) (match_dup 3)))
2621: (set (pc)
2622: (if_then_else (lt (match_dup 1) (const_int 0))
2623: (label_ref (match_operand 0 "" ""))
2624: (pc)))]
2625: ""
2626: "
2627: {
2628: operands[1] = gen_reg_rtx (SImode);
2629: operands[2] = a29k_compare_op0;
2630: operands[3] = a29k_compare_op1;
2631: }")
2632:
2633: (define_expand "bgeu"
2634: [(set (match_dup 1) (geu:SI (match_dup 2) (match_dup 3)))
2635: (set (pc)
2636: (if_then_else (lt (match_dup 1) (const_int 0))
2637: (label_ref (match_operand 0 "" ""))
2638: (pc)))]
2639: ""
2640: "
2641: {
2642: operands[1] = gen_reg_rtx (SImode);
2643: operands[2] = a29k_compare_op0;
2644: operands[3] = a29k_compare_op1;
2645: }")
2646:
2647: (define_expand "seq"
2648: [(set (match_operand:SI 0 "gpc_reg_operand" "")
2649: (eq:SI (match_dup 1) (match_dup 2)))]
2650: ""
2651: "
2652: {
2653: operands[1] = a29k_compare_op0;
2654: operands[2] = a29k_compare_op1;
2655: }")
2656:
2657: ;; This is the most complicated case, because we don't have a floating-point
2658: ;; "ne" insn. If integer, handle normally. If floating-point, write the
2659: ;; compare and then write an insn to reverse the test.
2660: (define_expand "sne_fp"
2661: [(set (match_dup 3)
2662: (eq:SI (match_operand 1 "gpc_reg_operand" "")
2663: (match_operand 2 "gpc_reg_operand" "")))
2664: (set (match_operand:SI 0 "gpc_reg_operand" "")
2665: (ge:SI (match_dup 3) (const_int 0)))]
2666: ""
2667: "
2668: { operands[3] = gen_reg_rtx (SImode);
2669: }");
2670:
2671: (define_expand "sne"
2672: [(set (match_operand:SI 0 "gpc_reg_operand" "")
2673: (ne:SI (match_dup 1) (match_dup 2)))]
2674: ""
2675: "
2676: {
2677: operands[1] = a29k_compare_op0;
2678: operands[2] = a29k_compare_op1;
2679:
2680: if (a29k_compare_fp_p)
2681: {
2682: emit_insn (gen_sne_fp (operands[0], operands[1], operands[2]));
2683: DONE;
2684: }
2685: }")
2686:
2687: ;; We don't have a floating-point "lt" insn, so use "gt" and swap the
2688: ;; operands, the same as we do "blt".
2689: (define_expand "slt"
2690: [(set (match_operand:SI 0 "gpc_reg_operand" "")
2691: (match_dup 1))]
2692: ""
2693: "
2694: {
2695: if (a29k_compare_fp_p)
2696: operands[1] = gen_rtx (GT, SImode, a29k_compare_op1, a29k_compare_op0);
2697: else
2698: operands[1] = gen_rtx (LT, SImode, a29k_compare_op0, a29k_compare_op1);
2699: }")
2700:
2701: ;; Similarly for "le"
2702: (define_expand "sle"
2703: [(set (match_operand:SI 0 "gpc_reg_operand" "")
2704: (match_dup 1))]
2705: ""
2706: "
2707: {
2708: if (a29k_compare_fp_p)
2709: operands[1] = gen_rtx (GE, SImode, a29k_compare_op1, a29k_compare_op0);
2710: else
2711: operands[1] = gen_rtx (LE, SImode, a29k_compare_op0, a29k_compare_op1);
2712: }")
2713:
2714: (define_expand "sltu"
2715: [(set (match_operand:SI 0 "gpc_reg_operand" "")
2716: (ltu:SI (match_dup 1) (match_dup 2)))]
2717: ""
2718: "
2719: {
2720: operands[1] = a29k_compare_op0;
2721: operands[2] = a29k_compare_op1;
2722: }")
2723:
2724: (define_expand "sleu"
2725: [(set (match_operand:SI 0 "gpc_reg_operand" "")
2726: (leu:SI (match_dup 1) (match_dup 2)))]
2727: ""
2728: "
2729: {
2730: operands[1] = a29k_compare_op0;
2731: operands[2] = a29k_compare_op1;
2732: }")
2733:
2734: (define_expand "sgt"
2735: [(set (match_operand:SI 0 "gpc_reg_operand" "")
2736: (gt:SI (match_dup 1) (match_dup 2)))]
2737: ""
2738: "
2739: {
2740: operands[1] = a29k_compare_op0;
2741: operands[2] = a29k_compare_op1;
2742: }")
2743:
2744: (define_expand "sge"
2745: [(set (match_operand:SI 0 "gpc_reg_operand" "")
2746: (ge:SI (match_dup 1) (match_dup 2)))]
2747: ""
2748: "
2749: {
2750: operands[1] = a29k_compare_op0;
2751: operands[2] = a29k_compare_op1;
2752: }")
2753:
2754: (define_expand "sgtu"
2755: [(set (match_operand:SI 0 "gpc_reg_operand" "")
2756: (gtu:SI (match_dup 1) (match_dup 2)))]
2757: ""
2758: "
2759: {
2760: operands[1] = a29k_compare_op0;
2761: operands[2] = a29k_compare_op1;
2762: }")
2763:
2764: (define_expand "sgeu"
2765: [(set (match_operand:SI 0 "gpc_reg_operand" "")
2766: (geu:SI (match_dup 1) (match_dup 2)))]
2767: ""
2768: "
2769: {
2770: operands[1] = a29k_compare_op0;
2771: operands[2] = a29k_compare_op1;
2772: }")
2773:
2774: ;; Now define the actual jump insns.
2775: (define_insn ""
2776: [(set (pc)
2777: (if_then_else (match_operator 0 "branch_operator"
2778: [(match_operand:SI 1 "gpc_reg_operand" "r")
2779: (const_int 0)])
2780: (label_ref (match_operand 2 "" ""))
2781: (pc)))]
2782: ""
2783: "jmp%b0 %1,%l2%#"
2784: [(set_attr "type" "branch")])
2785:
2786: (define_insn ""
2787: [(set (pc)
2788: (if_then_else (match_operator 0 "branch_operator"
2789: [(match_operand:SI 1 "gpc_reg_operand" "r")
2790: (const_int 0)])
2791: (return)
2792: (pc)))]
2793: "null_epilogue ()"
2794: "jmp%b0i %1,lr0%#"
2795: [(set_attr "type" "branch")])
2796:
2797: (define_insn ""
2798: [(set (pc)
2799: (if_then_else (match_operator 0 "branch_operator"
2800: [(match_operand:SI 1 "gpc_reg_operand" "r")
2801: (const_int 0)])
2802: (pc)
2803: (label_ref (match_operand 2 "" ""))))]
2804: ""
2805: "jmp%B0 %1,%l2%#"
2806: [(set_attr "type" "branch")])
2807:
2808: (define_insn ""
2809: [(set (pc)
2810: (if_then_else (match_operator 0 "branch_operator"
2811: [(match_operand:SI 1 "gpc_reg_operand" "r")
2812: (const_int 0)])
2813: (pc)
2814: (return)))]
2815: "null_epilogue ()"
2816: "jmp%B0i %1,lr0%#"
2817: [(set_attr "type" "branch")])
2818:
2819: (define_insn "jump"
2820: [(set (pc)
2821: (label_ref (match_operand 0 "" "")))]
2822: ""
2823: "jmp %e0%E0"
2824: [(set_attr "type" "branch")])
2825:
2826: (define_insn "return"
2827: [(return)]
2828: "null_epilogue ()"
2829: "jmpi lr0%#"
2830: [(set_attr "type" "branch")])
2831:
2832: (define_insn "indirect_jump"
2833: [(set (pc)
2834: (match_operand:SI 0 "gpc_reg_operand" "r"))]
2835: ""
2836: "jmpi %0%#"
2837: [(set_attr "type" "branch")])
2838:
2839: (define_insn "tablejump"
2840: [(set (pc)
2841: (match_operand:SI 0 "gpc_reg_operand" "r"))
2842: (use (label_ref (match_operand 1 "" "")))]
2843: ""
2844: "jmpi %0%#"
2845: [(set_attr "type" "branch")])
2846:
2847: ;; JMPFDEC
2848: (define_insn ""
2849: [(set (pc)
2850: (if_then_else (ge (match_operand:SI 0 "gpc_reg_operand" "r")
2851: (const_int 0))
2852: (label_ref (match_operand 1 "" ""))
2853: (pc)))
2854: (set (match_dup 0)
2855: (plus:SI (match_dup 0)
2856: (const_int -1)))]
2857: ""
2858: "jmpfdec %0,%l1%#"
2859: [(set_attr "type" "branch")])
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