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1.1 root 1: ;;- Machine description for GNU compiler, Clipper Version
2: ;; Copyright (C) 1987, 1988, 1991, 1993 Free Software Foundation, Inc.
3:
4: ;; Contributed by Holger Teutsch ([email protected])
5:
6: ;; This file is part of GNU CC.
7:
8: ;; GNU CC is free software; you can redistribute it and/or modify
9: ;; it under the terms of the GNU General Public License as published by
10: ;; the Free Software Foundation; either version 2, or (at your option)
11: ;; any later version.
12:
13: ;; GNU CC is distributed in the hope that it will be useful,
14: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16: ;; GNU General Public License for more details.
17:
18: ;; You should have received a copy of the GNU General Public License
19: ;; along with GNU CC; see the file COPYING. If not, write to
20: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21:
22:
23: ;;- Instruction patterns. When multiple patterns apply,
24: ;;- the first one in the file is chosen.
25: ;;-
26: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
27: ;;-
28: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
29: ;;- updates for most instructions.
30:
31: ;;
32: ;; define attributes
33: ;;
34: ;; instruction type
35: ;;
36: ;; unknown is temporary in order to generate 'cc clobber' until attribute
37: ;; assignment is consistent
38: ;;
39: (define_attr "type" "load,store,arith,fp,branch,unknown"
40: (const_string "unknown"))
41:
42: ;; condition code setting
43: ;;
44: ;; clobber destroyed
45: ;; unchanged
46: ;; set1 set cc_status.value1, e.g. sub r0,r1
47: ;; set2 set value1 and value2, e.g. mov r0,r1
48: ;; change0 may be side effect, i.e. load mem,r0
49: ;;
50: ;; note: loadi and loadq are 'arith' instructions that set the condition codes
51: ;; mul,div,mod do NOT set the condition codes
52: ;;
53: (define_attr "cc" "clobber,unchanged,set1,set2,change0"
54: (cond [(eq_attr "type" "load") (const_string "change0")
55: (eq_attr "type" "store,branch") (const_string "unchanged")
56: (eq_attr "type" "arith") (if_then_else (match_operand:SI 0 "" "")
57: (const_string "set1")
58: (const_string "clobber"))
59: ]
60: (const_string "clobber")))
61:
62: ;;
63: ;; clipper seems to be a tradional risc processor
64: ;; we define a functional unit 'memory'
65: ;;
66: (define_function_unit "memory" 1 1 (eq_attr "type" "load") 4 0)
67:
68:
69: ;; We don't want to allow a constant operand for test insns because
70: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
71: ;; be folded while optimizing anyway.
72:
73: (define_insn "tstsi"
74: [(set (cc0)
75: (match_operand:SI 0 "int_reg_operand" "r"))]
76: ""
77: "cmpq $0,%0")
78:
79: (define_insn "cmpsi"
80: [(set (cc0)
81: (compare (match_operand:SI 0 "nonimmediate_operand" "r,r,n")
82: (match_operand:SI 1 "nonmemory_operand" "r,n,r")))]
83: ""
84: "*
85: {
86: int val;
87:
88: if (which_alternative == 0)
89: return \"cmpw %1,%0\";
90:
91: if (which_alternative == 1)
92: {
93: val = INTVAL (operands[1]);
94: if (0 <= val && val < 16)
95: return \"cmpq %1,%0\";
96: return \"cmpi %1,%0\";
97: }
98:
99: cc_status.flags |= CC_REVERSED; /* immediate must be first */
100:
101: val = INTVAL (operands[0]);
102:
103: if (0 <= val && val < 16)
104: return \"cmpq %0,%1\";
105:
106: return \"cmpi %0,%1\";
107: }")
108:
109: (define_insn "cmpdf"
110: [(set (cc0)
111: (compare (match_operand:DF 0 "fp_reg_operand" "f")
112: (match_operand:DF 1 "fp_reg_operand" "f")))]
113: ""
114: "cmpd %1,%0")
115:
116: (define_insn "cmpsf"
117: [(set (cc0)
118: (compare (match_operand:SF 0 "fp_reg_operand" "f")
119: (match_operand:SF 1 "fp_reg_operand" "f")))]
120: ""
121: "cmps %1,%0")
122:
123:
124: ;;
125: ;; double and single float move
126: ;;
127: (define_expand "movdf"
128: [(set (match_operand:DF 0 "general_operand" "")
129: (match_operand:DF 1 "general_operand" ""))]
130: ""
131: "
132: {
133: if (GET_CODE (operands[0]) == MEM)
134: {
135: if (GET_CODE (operands[1]) == CONST_DOUBLE)
136: operands[1] = force_reg (DFmode,
137: force_const_mem (DFmode, operands[1]));
138: else if (GET_CODE (operands[1]) != REG)
139: operands[1] = force_reg (DFmode, operands[1]);
140: }
141:
142: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
143: operands[1] = force_const_mem (DFmode, operands[1]);
144: }")
145:
146: ;;
147: ;; provide two patterns with different predicates as we don't want combine
148: ;; to recombine a mem -> mem move
149: ;;
150: (define_insn ""
151: [(set (match_operand:DF 0 "register_operand" "=*rf")
152: (match_operand:DF 1 "nonimmediate_operand" "*rfo"))]
153: ""
154: "*
155: {
156: #define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16)
157:
158: if (FP_REG_P (operands[0]))
159: {
160: if (FP_REG_P (operands[1])) /* f -> f */
161: return \"movd %1,%0\";
162:
163: if (GET_CODE (operands[1]) == REG) /* r -> f */
164: return \"movld %1,%0\";
165:
166: return \"loadd %1,%0\"; /* m -> f */
167: }
168:
169: if (FP_REG_P (operands[1]))
170: {
171: if (GET_CODE (operands[0]) == REG) /* f -> r */
172: return \"movdl %1,%0\";
173:
174: abort ();
175: }
176:
177: if (GET_CODE (operands[1]) == MEM) /* m -> r */
178: {
179: rtx xops[4];
180: xops[0] = operands[0];
181: xops[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
182: xops[2] = operands[1];
183: xops[3] = adj_offsettable_operand (operands[1], 4);
184: output_asm_insn (\"loadw %2,%0\;loadw %3,%1\", xops);
185: return \"\";
186: }
187:
188: if (GET_CODE (operands[1]) == REG) /* r -> r */
189: {
190: rtx xops[4];
191: xops[0] = operands[0];
192: xops[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
193: xops[2] = operands[1];
194: xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
195: output_asm_insn (\"movw %2,%0\;movw %3,%1\", xops);
196: return \"\";
197: }
198:
199: abort ();
200: #undef FP_REG_P
201: }")
202:
203:
204: (define_insn ""
205: [(set (match_operand:DF 0 "memory_operand" "=o,m")
206: (match_operand:DF 1 "register_operand" "*rf,f"))]
207: ""
208: "*
209: {
210: rtx xops[4];
211:
212: if (REGNO (operands[1]) >= 16) /* f -> m */
213: return \"stord %1,%0\";
214:
215: xops[0] = operands[0]; /* r -> o */
216: xops[1] = adj_offsettable_operand (operands[0], 4);
217: xops[2] = operands[1];
218: xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
219: output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops);
220: return \"\";
221: }"
222: [(set_attr "type" "store,store")
223: (set_attr "cc" "clobber,unchanged")])
224:
225:
226: (define_expand "movsf"
227: [(set (match_operand:SF 0 "general_operand" "")
228: (match_operand:SF 1 "general_operand" ""))]
229: ""
230: "
231: {
232: if (GET_CODE (operands[0]) == MEM)
233: {
234: if (GET_CODE (operands[1]) == CONST_DOUBLE)
235: operands[1] = force_reg (SFmode,
236: force_const_mem (SFmode, operands[1]));
237: else if (GET_CODE (operands[1]) != REG)
238: operands[1] = force_reg (SFmode, operands[1]);
239: }
240:
241: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
242: operands[1] = force_const_mem (SFmode, operands[1]);
243: }")
244:
245: ;;
246: ;; provide two patterns with different predicates as we don't want combine
247: ;; to recombine a mem -> mem move
248: ;;
249: (define_insn ""
250: [(set (match_operand:SF 0 "register_operand" "=*rf")
251: (match_operand:SF 1 "nonimmediate_operand" "*rfm"))]
252: ""
253: "*
254: {
255: #define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16)
256:
257: if (FP_REG_P (operands[0]))
258: {
259: if (FP_REG_P (operands[1])) /* f -> f */
260: return \"movs %1,%0\";
261: if (GET_CODE (operands[1]) == REG) /* r -> f */
262: return
263: \"subq $8,sp\;storw %1,(sp)\;loads (sp),%0\;addq $8,sp\";
264: return \"loads %1,%0\"; /* m -> f */
265: }
266:
267: if (FP_REG_P (operands[1]))
268: {
269: if (GET_CODE (operands[0]) == REG) /* f -> r */
270: return
271: \"subq $8,sp\;stors %1,(sp)\;loadw (sp),%0\;addq $8,sp\";
272: abort ();
273: }
274:
275: if (GET_CODE (operands[1]) == MEM) /* m -> r */
276: return \"loadw %1,%0\";
277:
278: if (GET_CODE (operands[1]) == REG) /* r -> r */
279: return \"movw %1,%0\";
280:
281: abort ();
282: #undef FP_REG_P
283: }")
284:
285: (define_insn ""
286: [(set (match_operand:SF 0 "memory_operand" "=m")
287: (match_operand:SF 1 "register_operand" "*rf"))]
288: ""
289: "*
290: {
291: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) >= 16)
292: return \"stors %1,%0\"; /* f-> m */
293:
294: return \"storw %1,%0\"; /* r -> m */
295: }"
296: [(set_attr "type" "store")])
297:
298:
299: (define_expand "movdi"
300: [(set (match_operand:DI 0 "general_operand" "")
301: (match_operand:DI 1 "general_operand" ""))]
302: ""
303: "
304: {
305: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG)
306: operands[1] = force_reg (DImode, operands[1]);
307: }")
308:
309: ;; If an operand is a MEM but not offsetable, we can't load it into
310: ;; a register, so we must force the third alternative to be the one
311: ;; reloaded. Hence we show the first as more expensive.
312: (define_insn ""
313: [(set (match_operand:DI 0 "register_operand" "=?r,r,r")
314: (match_operand:DI 1 "general_operand" "r,n,o"))]
315: ""
316: "*
317: {
318: rtx xoperands[2],yoperands[2];
319:
320: xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
321:
322: if (which_alternative == 0) /* r -> r */
323: {
324: output_asm_insn (\"movw %1,%0\", operands);
325: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
326: output_asm_insn (\"movw %1,%0\", xoperands);
327: return \"\";
328: }
329:
330: if (which_alternative == 1) /* n -> r */
331: {
332: if (GET_CODE (operands[1]) == CONST_INT)
333: {
334: output_asm_insn (\"loadi %1,%0\", operands);
335: output_asm_insn (\"loadq $0,%0\", xoperands);
336: return \"\";
337: }
338:
339: if (GET_CODE (operands[1]) != CONST_DOUBLE)
340: abort ();
341:
342: yoperands[0] = operands[0];
343: yoperands[1] = gen_rtx (CONST_INT, VOIDmode,
344: CONST_DOUBLE_LOW (operands[1]));
345: output_asm_insn (\"loadi %1,%0\", yoperands);
346:
347: xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
348: CONST_DOUBLE_HIGH (operands[1]));
349: output_asm_insn (\"loadi %1,%0\", xoperands);
350: return \"\";
351: }
352: /* m -> r */
353: output_asm_insn (\"loadw %1,%0\", operands);
354: xoperands[1] = adj_offsettable_operand (operands[1], 4);
355: output_asm_insn (\"loadw %1,%0\", xoperands);
356: return \"\";
357: }"
358: [(set_attr "type" "arith,arith,load")
359: (set_attr "cc" "clobber,clobber,clobber")])
360:
361: (define_insn ""
362: [(set (match_operand:DI 0 "memory_operand" "=o")
363: (match_operand:DI 1 "register_operand" "r"))]
364: ""
365: "*
366: {
367: rtx xops[4];
368: xops[0] = operands[0];
369: xops[1] = adj_offsettable_operand (operands[0], 4);
370: xops[2] = operands[1];
371: xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
372: output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops);
373: return \"\";
374: }"
375: [(set_attr "type" "store")
376: (set_attr "cc" "clobber")])
377:
378: (define_expand "movsi"
379: [(set (match_operand:SI 0 "general_operand" "")
380: (match_operand:SI 1 "general_operand" ""))]
381: ""
382: "
383: {
384: if (GET_CODE (operands[0]) == MEM &&
385: GET_CODE (operands[1]) != REG)
386: operands[1] = force_reg (SImode, operands[1]);
387: }")
388:
389: ;; provide 2 patterns with different predicates as 'general_operand' in both
390: ;; positions results in a 'mem -> mem' move from combine that must be reloaded
391: ;;
392:
393: (define_insn ""
394: [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
395: (match_operand:SI 1 "general_operand" "r,m,n,i"))]
396: ""
397: "*
398: {
399: int val;
400:
401: if (which_alternative == 0)
402: return \"movw %1,%0\"; /* reg -> reg */
403:
404: if (which_alternative == 1)
405: return \"loadw %1,%0\"; /* mem -> reg */
406:
407: if (which_alternative == 2)
408: {
409: val = INTVAL (operands[1]); /* known const ->reg */
410:
411: if (val == -1)
412: return \"notq $0,%0\";
413:
414: if (val < 0 || val >= 16)
415: return \"loadi %1,%0\";
416:
417: return \"loadq %1,%0\";
418: }
419:
420: if (which_alternative == 3) /* unknown const */
421: return \"loada %a1,%0\";
422: }"
423: [(set_attr "type" "arith,load,arith,load")
424: (set_attr "cc" "set2,change0,set1,change0")])
425:
426:
427: (define_insn ""
428: [(set (match_operand:SI 0 "memory_operand" "=m")
429: (match_operand:SI 1 "int_reg_operand" "r"))]
430: ""
431: "storw %1,%0"
432: [(set_attr "type" "store")])
433:
434: ;; movhi
435: ;;
436: ;; loadh mem to reg
437: ;; storh reg to mem
438: ;;
439: ;;
440: (define_expand "movhi"
441: [(set (match_operand:HI 0 "general_operand" "")
442: (match_operand:HI 1 "general_operand" ""))]
443: ""
444: "
445: {
446: if (GET_CODE (operands[0]) == MEM
447: && ! register_operand (operands[1], HImode))
448: operands[1] = force_reg (HImode, operands[1]);
449: }")
450:
451:
452: (define_insn ""
453: [(set (match_operand:HI 0 "register_operand" "=r,r,r")
454: (match_operand:HI 1 "general_operand" "r,m,n"))]
455: ""
456: "@
457: movw %1,%0
458: loadh %1,%0
459: loadi %1,%0"
460: [(set_attr "type" "arith,load,arith")])
461:
462: (define_insn ""
463: [(set (match_operand:HI 0 "memory_operand" "=m")
464: (match_operand:HI 1 "register_operand" "r"))]
465: ""
466: "storh %1,%0"
467: [(set_attr "type" "store")])
468:
469: ;; movqi
470: ;;
471: ;; loadb mem to reg
472: ;; storb reg to mem
473: ;;
474: (define_expand "movqi"
475: [(set (match_operand:QI 0 "general_operand" "")
476: (match_operand:QI 1 "general_operand" ""))]
477: ""
478: "
479: {
480: if (GET_CODE (operands[0]) == MEM &&
481: ! register_operand (operands[1], QImode))
482: operands[1] = force_reg (QImode, operands[1]);
483: }")
484:
485:
486: (define_insn ""
487: [(set (match_operand:QI 0 "register_operand" "=r,r,r")
488: (match_operand:QI 1 "general_operand" "r,m,n"))]
489: ""
490: "@
491: movw %1,%0
492: loadb %1,%0
493: loadi %1,%0"
494: [(set_attr "type" "arith,load,arith")])
495:
496: (define_insn ""
497: [(set (match_operand:QI 0 "memory_operand" "=m")
498: (match_operand:QI 1 "register_operand" "r"))]
499: ""
500: "storb %1,%0"
501: [(set_attr "type" "store")])
502:
503:
504: ;;
505: ;; block move
506: ;;
507: (define_expand "movstrsi"
508: [(parallel
509: [(set (match_operand:BLK 0 "memory_operand" "")
510: (match_operand:BLK 1 "memory_operand" ""))
511: (use (match_operand:SI 2 "general_operand" ""))
512: (use (match_operand:SI 3 "const_int_operand" ""))
513: (clobber (match_scratch:SI 4 ""))
514: (clobber (match_scratch:SI 5 ""))
515: (clobber (match_dup 6))
516: (clobber (match_dup 7))])]
517: ""
518: "
519: {
520: rtx addr0, addr1;
521:
522: addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
523: addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
524:
525: operands[6] = addr0;
526: operands[7] = addr1;
527:
528: operands[0] = gen_rtx (MEM, BLKmode, addr0);
529: operands[1] = gen_rtx (MEM, BLKmode, addr1);
530:
531: if (GET_CODE (operands[2]) != CONST_INT)
532: operands[2] = force_reg (SImode, operands[2]);
533: }")
534:
535: ;;
536: ;; there is a problem with this insn in gcc-2.2.3
537: ;; (clobber (match_dup 2)) does not prevent use of this operand later
538: ;; we always use a scratch register and leave operand 2 unchanged
539: ;;
540: (define_insn ""
541: [(set (mem:BLK (match_operand:SI 0 "register_operand" "r"))
542: (mem:BLK (match_operand:SI 1 "register_operand" "r")))
543: (use (match_operand:SI 2 "nonmemory_operand" "rn"))
544: (use (match_operand:SI 3 "const_int_operand" "n"))
545: (clobber (match_scratch:SI 4 "=r"))
546: (clobber (match_scratch:SI 5 "=r"))
547: (clobber (match_dup 0))
548: (clobber (match_dup 1))]
549: ""
550: "*
551: {
552: extern void clipper_movstr ();
553: clipper_movstr (operands);
554: return \"\";
555: }"
556: [(set_attr "cc" "clobber")])
557:
558:
559:
560: ;; Extension and truncation insns.
561: (define_insn "extendhisi2"
562: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
563: (sign_extend:SI (match_operand:HI 1 "general_operand" "0,m")))]
564: ""
565: "@
566: andi $65535,%0\;xori $32768,%0\;subi $32768,%0
567: loadh %1,%0"
568: [(set_attr "type" "arith,load")])
569:
570:
571: (define_insn "extendqihi2"
572: [(set (match_operand:HI 0 "int_reg_operand" "=r,r")
573: (sign_extend:HI (match_operand:QI 1 "general_operand" "0,m")))]
574: ""
575: "@
576: andi $255,%0\;xori $128,%0\;subi $128,%0
577: loadb %1,%0"
578: [(set_attr "type" "arith,load")
579: (set_attr "cc" "set1,change0")])
580:
581:
582: (define_insn "extendqisi2"
583: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
584: (sign_extend:SI (match_operand:QI 1 "general_operand" "0,m")))]
585: ""
586: "@
587: andi $255,%0\;xori $128,%0\;subi $128,%0
588: loadb %1,%0"
589: [(set_attr "type" "arith,load")])
590:
591:
592: (define_insn "extendsfdf2"
593: [(set (match_operand:DF 0 "fp_reg_operand" "=f")
594: (float_extend:DF (match_operand:SF 1 "fp_reg_operand" "f")))]
595: ""
596: "cnvsd %1,%0")
597:
598: (define_insn "truncdfsf2"
599: [(set (match_operand:SF 0 "fp_reg_operand" "=f")
600: (float_truncate:SF (match_operand:DF 1 "fp_reg_operand" "f")))]
601: ""
602: "cnvds %1,%0")
603:
604: (define_insn "zero_extendhisi2"
605: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
606: (zero_extend:SI (match_operand:HI 1 "general_operand" "0,m")))]
607: ""
608: "@
609: andi $65535,%0
610: loadhu %1,%0"
611: [(set_attr "type" "arith,load")])
612:
613:
614: (define_insn "zero_extendqihi2"
615: [(set (match_operand:HI 0 "int_reg_operand" "=r,r")
616: (zero_extend:HI (match_operand:QI 1 "general_operand" "0,m")))]
617: ""
618: "@
619: andi $255,%0
620: loadbu %1,%0"
621: [(set_attr "type" "arith,load")
622: (set_attr "cc" "clobber,clobber")])
623:
624:
625: (define_insn "zero_extendqisi2"
626: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
627: (zero_extend:SI (match_operand:QI 1 "general_operand" "0,m")))]
628: ""
629: "@
630: andi $255,%0
631: loadbu %1,%0"
632: [(set_attr "type" "arith,load")])
633:
634:
635:
636: ;; Fix-to-float conversion insns.
637:
638: (define_insn "floatsisf2"
639: [(set (match_operand:SF 0 "fp_reg_operand" "=f")
640: (float:SF (match_operand:SI 1 "int_reg_operand" "r")))]
641: ""
642: "cnvws %1,%0")
643:
644: (define_insn "floatsidf2"
645: [(set (match_operand:DF 0 "fp_reg_operand" "=f")
646: (float:DF (match_operand:SI 1 "int_reg_operand" "r")))]
647: ""
648: "cnvwd %1,%0")
649:
650:
651: ;; Float-to-fix conversion insns.
652:
653: (define_insn "fix_truncsfsi2"
654: [(set (match_operand:SI 0 "int_reg_operand" "=r")
655: (fix:SI (fix:SF (match_operand:SF 1 "fp_reg_operand" "f"))))]
656: ""
657: "cnvtsw %1,%0")
658:
659: (define_insn "fix_truncdfsi2"
660: [(set (match_operand:SI 0 "int_reg_operand" "=r")
661: (fix:SI (fix:DF (match_operand:DF 1 "fp_reg_operand" "f"))))]
662: ""
663: "cnvtdw %1,%0")
664:
665: ;;- All kinds of add instructions.
666:
667: (define_insn "adddf3"
668: [(set (match_operand:DF 0 "fp_reg_operand" "=f")
669: (plus:DF (match_operand:DF 1 "fp_reg_operand" "0")
670: (match_operand:DF 2 "fp_reg_operand" "f")))]
671: ""
672: "addd %2,%0"
673: [(set_attr "type" "fp")])
674:
675:
676: (define_insn "addsf3"
677: [(set (match_operand:SF 0 "fp_reg_operand" "=f")
678: (plus:SF (match_operand:SF 1 "fp_reg_operand" "0")
679: (match_operand:SF 2 "fp_reg_operand" "f")))]
680: ""
681: "adds %2,%0"
682: [(set_attr "type" "fp")])
683:
684: (define_insn "adddi3"
685: [(set (match_operand:DI 0 "int_reg_operand" "=r")
686: (plus:DI (match_operand:DI 1 "int_reg_operand" "%0")
687: (match_operand:DI 2 "int_reg_operand" "r")))]
688: ""
689: "*
690: {
691: rtx xoperands[4];
692:
693: xoperands[0] = operands[0];
694: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
695: xoperands[2] = operands[2];
696: xoperands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
697: output_asm_insn (\"addw %2,%0\;addwc %3,%1\", xoperands);
698: return \"\";
699: }"
700: [(set_attr "type" "arith")
701: (set_attr "cc" "clobber")])
702:
703: (define_insn "addsi3"
704: [(set (match_operand:SI 0 "int_reg_operand" "=r,r,r")
705: (plus:SI (match_operand:SI 1 "int_reg_operand" "%0,r,r")
706: (match_operand:SI 2 "nonmemory_operand" "rn,0,rn")))]
707: ""
708: "*
709: {
710: if (which_alternative == 2) /* 3 address version */
711: {
712: if (GET_CODE (operands[2]) == CONST_INT)
713: return \"loada %a2(%1),%0\";
714: return \"loada [%2](%1),%0\";
715: }
716: /* 2 address version */
717: if (GET_CODE (operands[2]) == CONST_INT)
718: {
719: int val = INTVAL (operands[2]);
720:
721: if (val >= 16 || val == 0x80000000)
722: return \"addi %2,%0\";
723:
724: if (val < 0) /* change to sub */
725: {
726: rtx xops[2];
727:
728: val = -val;
729:
730: xops[0] = operands[0];
731: xops[1] = gen_rtx (CONST_INT, VOIDmode, val);
732:
733: if (val >= 16)
734: output_asm_insn (\"subi %1,%0\", xops);
735: else
736: output_asm_insn (\"subq %1,%0\", xops);
737:
738: return \"\";
739: }
740:
741: return \"addq %2,%0\";
742: }
743:
744: if (which_alternative == 0)
745: return \"addw %2,%0\";
746:
747: return \"addw %1,%0\";
748: }"
749: [(set_attr "type" "arith,arith,arith")
750: (set_attr "cc" "set1,set1,change0")])
751:
752:
753: ;;- All kinds of subtract instructions.
754:
755: (define_insn "subdi3"
756: [(set (match_operand:DI 0 "int_reg_operand" "=r")
757: (minus:DI (match_operand:DI 1 "int_reg_operand" "%0")
758: (match_operand:DI 2 "int_reg_operand" "r")))]
759: ""
760: "*
761: {
762: rtx xoperands[4];
763:
764: xoperands[0] = operands[0];
765: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
766: xoperands[2] = operands[2];
767: xoperands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
768: output_asm_insn (\"subw %2,%0\;subwc %3,%1\", xoperands);
769: return \"\";
770: }"
771: [(set_attr "type" "arith")
772: (set_attr "cc" "clobber")])
773:
774: (define_insn "subsi3"
775: [(set (match_operand:SI 0 "int_reg_operand" "=r")
776: (minus:SI (match_operand:SI 1 "int_reg_operand" "0")
777: (match_operand:SI 2 "nonmemory_operand" "rn")))]
778: ""
779: "*
780: {
781: if (GET_CODE (operands[2]) == CONST_INT)
782: {
783: int val = INTVAL (operands[2]);
784:
785: if (val < 0 || val >= 16)
786: return \"subi %2,%0\";
787: else
788: return \"subq %2,%0\";
789: }
790:
791: return \"subw %2,%0\";
792: }"
793: [(set_attr "type" "arith")])
794:
795: (define_insn "subdf3"
796: [(set (match_operand:DF 0 "fp_reg_operand" "=f")
797: (minus:DF (match_operand:DF 1 "fp_reg_operand" "0")
798: (match_operand:DF 2 "fp_reg_operand" "f")))]
799: ""
800: "subd %2,%0"
801: [(set_attr "type" "fp")])
802:
803: (define_insn "subsf3"
804: [(set (match_operand:SF 0 "fp_reg_operand" "=f")
805: (minus:SF (match_operand:SF 1 "fp_reg_operand" "0")
806: (match_operand:SF 2 "fp_reg_operand" "f")))]
807: ""
808: "subs %2,%0"
809: [(set_attr "type" "fp")])
810:
811:
812: ;;- Multiply instructions.
813:
814: (define_insn "muldf3"
815: [(set (match_operand:DF 0 "fp_reg_operand" "=f")
816: (mult:DF (match_operand:DF 1 "fp_reg_operand" "0")
817: (match_operand:DF 2 "fp_reg_operand" "f")))]
818: ""
819: "muld %2,%0"
820: [(set_attr "type" "fp")])
821:
822: (define_insn "mulsf3"
823: [(set (match_operand:SF 0 "fp_reg_operand" "=f")
824: (mult:SF (match_operand:SF 1 "fp_reg_operand" "0")
825: (match_operand:SF 2 "fp_reg_operand" "f")))]
826: ""
827: "muls %2,%0"
828: [(set_attr "type" "fp")])
829:
830: (define_insn "mulsidi3"
831: [(set (match_operand:DI 0 "int_reg_operand" "=r")
832: (mult:DI (sign_extend:DI (match_operand:SI 1 "int_reg_operand" "%0"))
833: (sign_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))]
834: ""
835: "mulwx %2,%0"
836: [(set_attr "type" "arith")
837: (set_attr "cc" "clobber")])
838:
839: (define_insn "umulsidi3"
840: [(set (match_operand:DI 0 "int_reg_operand" "=r")
841: (mult:DI (zero_extend:DI (match_operand:SI 1 "int_reg_operand" "%0"))
842: (zero_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))]
843: ""
844: "mulwux %2,%0"
845: [(set_attr "type" "arith")
846: (set_attr "cc" "clobber")])
847:
848: (define_insn "mulsi3"
849: [(set (match_operand:SI 0 "int_reg_operand" "=r")
850: (mult:SI (match_operand:SI 1 "int_reg_operand" "%0")
851: (match_operand:SI 2 "int_reg_operand" "r")))]
852: ""
853: "mulw %2,%0"
854: [(set_attr "type" "arith")
855: (set_attr "cc" "clobber")])
856:
857:
858: ;;- Divide and mod instructions.
859:
860: (define_insn "divdf3"
861: [(set (match_operand:DF 0 "fp_reg_operand" "=f")
862: (div:DF (match_operand:DF 1 "fp_reg_operand" "0")
863: (match_operand:DF 2 "fp_reg_operand" "f")))]
864: ""
865: "divd %2,%0"
866: [(set_attr "type" "fp")])
867:
868: (define_insn "divsf3"
869: [(set (match_operand:SF 0 "fp_reg_operand" "=f")
870: (div:SF (match_operand:SF 1 "fp_reg_operand" "0")
871: (match_operand:SF 2 "fp_reg_operand" "f")))]
872: ""
873: "divs %2,%0"
874: [(set_attr "type" "fp")])
875:
876: (define_insn "divsi3"
877: [(set (match_operand:SI 0 "int_reg_operand" "=r")
878: (div:SI (match_operand:SI 1 "int_reg_operand" "0")
879: (match_operand:SI 2 "int_reg_operand" "r")))]
880: ""
881: "divw %2,%0"
882: [(set_attr "type" "arith")
883: (set_attr "cc" "clobber")])
884:
885: (define_insn "udivsi3"
886: [(set (match_operand:SI 0 "int_reg_operand" "=r")
887: (udiv:SI (match_operand:SI 1 "int_reg_operand" "0")
888: (match_operand:SI 2 "int_reg_operand" "r")))]
889: ""
890: "divwu %2,%0"
891: [(set_attr "type" "arith")
892: (set_attr "cc" "clobber")])
893:
894:
895: (define_insn "modsi3"
896: [(set (match_operand:SI 0 "int_reg_operand" "=r")
897: (mod:SI (match_operand:SI 1 "int_reg_operand" "0")
898: (match_operand:SI 2 "int_reg_operand" "r")))]
899: ""
900: "modw %2,%0"
901: [(set_attr "type" "arith")
902: (set_attr "cc" "clobber")])
903:
904: (define_insn "umodsi3"
905: [(set (match_operand:SI 0 "int_reg_operand" "=r")
906: (umod:SI (match_operand:SI 1 "int_reg_operand" "0")
907: (match_operand:SI 2 "int_reg_operand" "r")))]
908: ""
909: "modwu %2,%0"
910: [(set_attr "type" "arith")
911: (set_attr "cc" "clobber")])
912:
913: ;;
914: ;; bit and/or instructions
915: ;;
916: (define_insn "andsi3"
917: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
918: (and:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
919: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
920: ""
921: "@
922: andw %2,%0
923: andi %2,%0"
924: [(set_attr "type" "arith")])
925:
926: (define_insn "iorsi3"
927: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
928: (ior:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
929: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
930: ""
931: "@
932: orw %2,%0
933: ori %2,%0"
934: [(set_attr "type" "arith")])
935:
936: (define_insn "xorsi3"
937: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
938: (xor:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
939: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
940: ""
941: "@
942: xorw %2,%0
943: xori %2,%0"
944: [(set_attr "type" "arith")])
945:
946: (define_insn "negdf2"
947: [(set (match_operand:DF 0 "fp_reg_operand" "=f")
948: (neg:DF (match_operand:DF 1 "fp_reg_operand" "f")))]
949: ""
950: "negd %1,%0"
951: [(set_attr "type" "fp")])
952:
953: (define_insn "negsf2"
954: [(set (match_operand:SF 0 "fp_reg_operand" "=f")
955: (neg:SF (match_operand:SF 1 "fp_reg_operand" "f")))]
956: ""
957: "negs %1,%0"
958: [(set_attr "type" "fp")])
959:
960: (define_insn "negsi2"
961: [(set (match_operand:SI 0 "int_reg_operand" "=r")
962: (neg:SI (match_operand:SI 1 "int_reg_operand" "r")))]
963: ""
964: "negw %1,%0"
965: [(set_attr "type" "arith")])
966:
967:
968: (define_insn "one_cmplsi2"
969: [(set (match_operand:SI 0 "int_reg_operand" "=r")
970: (not:SI (match_operand:SI 1 "int_reg_operand" "r")))]
971: ""
972: "notw %1,%0"
973: [(set_attr "type" "arith")])
974:
975:
976:
977: ;; Right shift on the clipper works by negating the shift count,
978: ;; then emitting a right shift with the shift count negated. This means
979: ;; that all actual shift counts in the RTL will be positive.
980:
981: (define_expand "ashrdi3"
982: [(set (match_operand:DI 0 "int_reg_operand" "")
983: (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "")
984: (match_operand:SI 2 "nonmemory_operand" "")))]
985: ""
986: "
987: {
988: if (GET_CODE (operands[2]) != CONST_INT)
989: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
990: }")
991:
992: (define_insn ""
993: [(set (match_operand:DI 0 "int_reg_operand" "=r")
994: (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
995: (match_operand:SI 2 "const_int_operand" "n")))]
996: ""
997: "shali $%n2,%0"
998: [(set_attr "type" "arith")])
999:
1000: (define_insn ""
1001: [(set (match_operand:DI 0 "int_reg_operand" "=r")
1002: (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
1003: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1004: ""
1005: "shal %2,%0"
1006: [(set_attr "type" "arith")])
1007:
1008: (define_expand "ashrsi3"
1009: [(set (match_operand:SI 0 "int_reg_operand" "")
1010: (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "")
1011: (match_operand:SI 2 "nonmemory_operand" "")))]
1012: ""
1013: "
1014: {
1015: if (GET_CODE (operands[2]) != CONST_INT)
1016: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1017: }")
1018:
1019: (define_insn ""
1020: [(set (match_operand:SI 0 "int_reg_operand" "=r")
1021: (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
1022: (match_operand:SI 2 "const_int_operand" "n")))]
1023: ""
1024: "shai $%n2,%0"
1025: [(set_attr "type" "arith")])
1026:
1027: (define_insn ""
1028: [(set (match_operand:SI 0 "int_reg_operand" "=r")
1029: (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
1030: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1031: ""
1032: "shaw %2,%0"
1033: [(set_attr "type" "arith")])
1034:
1035: ;;
1036: ;; left shift
1037: ;;
1038:
1039: (define_insn "ashldi3"
1040: [(set (match_operand:DI 0 "int_reg_operand" "=r,r")
1041: (ashift:DI (match_operand:DI 1 "int_reg_operand" "0,0")
1042: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1043: ""
1044: "@
1045: shal %2,%0
1046: shali %2,%0"
1047: [(set_attr "type" "arith")])
1048:
1049:
1050: (define_insn "ashlsi3"
1051: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
1052: (ashift:SI (match_operand:SI 1 "int_reg_operand" "0,0")
1053: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1054: ""
1055: "*
1056: {
1057: int val;
1058:
1059: if (which_alternative == 0)
1060: return \"shaw %2,%0\";
1061:
1062: val = INTVAL (operands[2]);
1063:
1064: if (val == 2)
1065: return \"addw %0,%0\;addw %0,%0\";
1066:
1067: if (val == 1)
1068: return \"addw %0,%0\";
1069:
1070: return \"shai %2,%0\";
1071: }"
1072: [(set_attr "type" "arith")])
1073:
1074: ;;
1075: ;; logical shift
1076: ;;
1077:
1078: (define_expand "lshrdi3"
1079: [(set (match_operand:DI 0 "int_reg_operand" "")
1080: (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "")
1081: (match_operand:SI 2 "nonmemory_operand" "")))]
1082: ""
1083: "
1084: {
1085: if (GET_CODE (operands[2]) != CONST_INT)
1086: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1087: }")
1088:
1089: (define_insn ""
1090: [(set (match_operand:DI 0 "int_reg_operand" "=r")
1091: (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
1092: (match_operand:SI 2 "const_int_operand" "n")))]
1093: ""
1094: "shlli $%n2,%0"
1095: [(set_attr "type" "arith")])
1096:
1097: (define_insn ""
1098: [(set (match_operand:DI 0 "int_reg_operand" "=r")
1099: (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
1100: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1101: ""
1102: "shll %2,%0"
1103: [(set_attr "type" "arith")])
1104:
1105: (define_expand "lshrsi3"
1106: [(set (match_operand:SI 0 "int_reg_operand" "")
1107: (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "")
1108: (match_operand:SI 2 "nonmemory_operand" "")))]
1109: ""
1110: "
1111: {
1112: if (GET_CODE (operands[2]) != CONST_INT)
1113: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1114: }")
1115:
1116: (define_insn ""
1117: [(set (match_operand:SI 0 "int_reg_operand" "=r")
1118: (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
1119: (match_operand:SI 2 "const_int_operand" "n")))]
1120: ""
1121: "shli $%n2,%0"
1122: [(set_attr "type" "arith")])
1123:
1124: (define_insn ""
1125: [(set (match_operand:SI 0 "int_reg_operand" "=r")
1126: (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
1127: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1128: ""
1129: "shlw %2,%0"
1130: [(set_attr "type" "arith")])
1131:
1132: (define_insn "lshldi3"
1133: [(set (match_operand:DI 0 "int_reg_operand" "=r,r")
1134: (lshift:DI (match_operand:DI 1 "int_reg_operand" "0,0")
1135: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1136: ""
1137: "@
1138: shll %2,%0
1139: shlli %2,%0"
1140: [(set_attr "type" "arith")])
1141:
1142: (define_insn "lshlsi3"
1143: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
1144: (lshift:SI (match_operand:SI 1 "int_reg_operand" "0,0")
1145: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1146: ""
1147: "@
1148: shlw %2,%0
1149: shli %2,%0"
1150: [(set_attr "type" "arith")])
1151:
1152: ;;
1153: ;; rotate insn
1154: ;;
1155: (define_expand "rotrdi3"
1156: [(set (match_operand:DI 0 "int_reg_operand" "")
1157: (rotatert:DI (match_operand:DI 1 "int_reg_operand" "")
1158: (match_operand:SI 2 "nonmemory_operand" "")))]
1159: ""
1160: "
1161: {
1162: if (GET_CODE (operands[2]) != CONST_INT)
1163: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1164: }")
1165:
1166: (define_insn ""
1167: [(set (match_operand:DI 0 "int_reg_operand" "=r")
1168: (rotatert:DI (match_operand:DI 1 "int_reg_operand" "0")
1169: (match_operand:SI 2 "const_int_operand" "n")))]
1170: ""
1171: "rotli $%n2,%0"
1172: [(set_attr "type" "arith")])
1173:
1174: (define_insn ""
1175: [(set (match_operand:DI 0 "int_reg_operand" "=r")
1176: (rotatert:DI (match_operand:DI 1 "int_reg_operand" "0")
1177: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1178: ""
1179: "rotl %2,%0"
1180: [(set_attr "type" "arith")])
1181:
1182: (define_expand "rotrsi3"
1183: [(set (match_operand:SI 0 "int_reg_operand" "")
1184: (rotatert:SI (match_operand:SI 1 "int_reg_operand" "")
1185: (match_operand:SI 2 "nonmemory_operand" "")))]
1186: ""
1187: "
1188: {
1189: if (GET_CODE (operands[2]) != CONST_INT)
1190: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1191: }")
1192:
1193: (define_insn ""
1194: [(set (match_operand:SI 0 "int_reg_operand" "=r")
1195: (rotatert:SI (match_operand:SI 1 "int_reg_operand" "0")
1196: (match_operand:SI 2 "const_int_operand" "n")))]
1197: ""
1198: "roti $%n2,%0"
1199: [(set_attr "type" "arith")])
1200:
1201: (define_insn ""
1202: [(set (match_operand:SI 0 "int_reg_operand" "=r")
1203: (rotatert:SI (match_operand:SI 1 "int_reg_operand" "0")
1204: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1205: ""
1206: "rotw %2,%0"
1207: [(set_attr "type" "arith")])
1208:
1209: (define_insn "rotldi3"
1210: [(set (match_operand:DI 0 "int_reg_operand" "=r,r")
1211: (rotate:DI (match_operand:DI 1 "int_reg_operand" "0,0")
1212: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1213: ""
1214: "@
1215: rotl %2,%0
1216: rotli %2,%0"
1217: [(set_attr "type" "arith")])
1218:
1219: (define_insn "rotlsi3"
1220: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
1221: (rotate:SI (match_operand:SI 1 "int_reg_operand" "0,0")
1222: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1223: ""
1224: "@
1225: rotw %2,%0
1226: roti %2,%0"
1227: [(set_attr "type" "arith")])
1228:
1229:
1230: ;;
1231: ;; jump and branch insns
1232: ;;
1233: (define_insn "jump"
1234: [(set (pc)
1235: (label_ref (match_operand 0 "" "")))]
1236: ""
1237: "b %l0"
1238: [(set_attr "type" "branch")])
1239:
1240: (define_insn "tablejump"
1241: [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1242: (use (label_ref (match_operand 1 "" "")))]
1243: ""
1244: "b (%0)"
1245: [(set_attr "type" "branch")])
1246:
1247: (define_insn "beq"
1248: [(set (pc)
1249: (if_then_else (eq (cc0)
1250: (const_int 0))
1251: (label_ref (match_operand 0 "" ""))
1252: (pc)))]
1253: ""
1254: "breq %l0"
1255: [(set_attr "type" "branch")])
1256:
1257: (define_insn "bne"
1258: [(set (pc)
1259: (if_then_else (ne (cc0)
1260: (const_int 0))
1261: (label_ref (match_operand 0 "" ""))
1262: (pc)))]
1263: ""
1264: "brne %l0"
1265: [(set_attr "type" "branch")])
1266:
1267: (define_insn "bgt"
1268: [(set (pc)
1269: (if_then_else (gt (cc0)
1270: (const_int 0))
1271: (label_ref (match_operand 0 "" ""))
1272: (pc)))]
1273: ""
1274: "brgt %l0"
1275: [(set_attr "type" "branch")])
1276:
1277: (define_insn "bgtu"
1278: [(set (pc)
1279: (if_then_else (gtu (cc0)
1280: (const_int 0))
1281: (label_ref (match_operand 0 "" ""))
1282: (pc)))]
1283: ""
1284: "brgtu %l0"
1285: [(set_attr "type" "branch")])
1286:
1287: (define_insn "blt"
1288: [(set (pc)
1289: (if_then_else (lt (cc0)
1290: (const_int 0))
1291: (label_ref (match_operand 0 "" ""))
1292: (pc)))]
1293: ""
1294: "brlt %l0"
1295: [(set_attr "type" "branch")])
1296:
1297: (define_insn "bltu"
1298: [(set (pc)
1299: (if_then_else (ltu (cc0)
1300: (const_int 0))
1301: (label_ref (match_operand 0 "" ""))
1302: (pc)))]
1303: ""
1304: "brltu %l0"
1305: [(set_attr "type" "branch")])
1306:
1307: (define_insn "bge"
1308: [(set (pc)
1309: (if_then_else (ge (cc0)
1310: (const_int 0))
1311: (label_ref (match_operand 0 "" ""))
1312: (pc)))]
1313: ""
1314: "brge %l0"
1315: [(set_attr "type" "branch")])
1316:
1317: (define_insn "bgeu"
1318: [(set (pc)
1319: (if_then_else (geu (cc0)
1320: (const_int 0))
1321: (label_ref (match_operand 0 "" ""))
1322: (pc)))]
1323: ""
1324: "brgeu %l0"
1325: [(set_attr "type" "branch")])
1326:
1327: (define_insn "ble"
1328: [(set (pc)
1329: (if_then_else (le (cc0)
1330: (const_int 0))
1331: (label_ref (match_operand 0 "" ""))
1332: (pc)))]
1333: ""
1334: "brle %l0"
1335: [(set_attr "type" "branch")])
1336:
1337: (define_insn "bleu"
1338: [(set (pc)
1339: (if_then_else (leu (cc0)
1340: (const_int 0))
1341: (label_ref (match_operand 0 "" ""))
1342: (pc)))]
1343: ""
1344: "brleu %l0"
1345: [(set_attr "type" "branch")])
1346:
1347: ;; Recognize reversed jumps.
1348: (define_insn ""
1349: [(set (pc)
1350: (if_then_else (match_operator 0 "comparison_operator"
1351: [(cc0)
1352: (const_int 0)])
1353: (pc)
1354: (label_ref (match_operand 1 "" ""))))]
1355: ""
1356: "br%C0 %l1" ; %C0 negates condition
1357: [(set_attr "type" "branch")])
1358:
1359: ;;
1360: ;; call instructions
1361: ;;
1362: (define_insn "call"
1363: [(call (match_operand:QI 0 "general_operand" "m")
1364: (match_operand:SI 1 "general_operand" ""))]
1365: ;; Operand 1 not used on the clipper.
1366: ""
1367: "call sp,%0")
1368:
1369: (define_insn "call_value"
1370: [(set (match_operand 0 "" "=rf")
1371: (call (match_operand:QI 1 "general_operand" "m")
1372: (match_operand:SI 2 "general_operand" "g")))]
1373: ;; Operand 2 not used on the clipper
1374: ""
1375: "call sp,%1")
1376:
1377: (define_insn "indirect_jump"
1378: [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1379: ""
1380: "b (%0)"
1381: [(set_attr "type" "branch")])
1382:
1383:
1384: (define_insn "nop"
1385: [(const_int 0)]
1386: ""
1387: "noop"
1388: [(set_attr "type" "arith")
1389: (set_attr "cc" "unchanged")])
1390:
1391:
1392:
1393: ;; while (--foo >= 0)
1394: ;;
1395: ;; Combiners for 'decrement test and branch' do not work for clipper.
1396: ;; These patters are jump_insns that do not allow output reloads and clipper
1397: ;; can only decrement and test registers.
1398: ;;
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