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1.1 ! root 1: ;;- Machine description for GNU compiler ! 2: ;;- Elxsi Version ! 3: ;; Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc. ! 4: ;; This port done by Mike Stump <[email protected]> in 1988, and is the first ! 5: ;; 64 bit port of GNU CC. ! 6: ;; Based upon the VAX port. ! 7: ! 8: ;; This file is part of GNU CC. ! 9: ! 10: ;; GNU CC is free software; you can redistribute it and/or modify ! 11: ;; it under the terms of the GNU General Public License as published by ! 12: ;; the Free Software Foundation; either version 1, or (at your option) ! 13: ;; any later version. ! 14: ! 15: ;; GNU CC is distributed in the hope that it will be useful, ! 16: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ! 17: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 18: ;; GNU General Public License for more details. ! 19: ! 20: ;; You should have received a copy of the GNU General Public License ! 21: ;; along with GNU CC; see the file COPYING. If not, write to ! 22: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! 23: ! 24: ! 25: ;;- Instruction patterns. When multiple patterns apply, ! 26: ;;- the first one in the file is chosen. ! 27: ;;- ! 28: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ! 29: ;;- ! 30: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code ! 31: ;;- updates for most instructions. ! 32: ! 33: ! 34: (define_insn "" ! 35: [(set (reg:SI 15) ! 36: (plus:SI (reg:SI 15) ! 37: (match_operand:SI 0 "general_operand" "g")))] ! 38: "" ! 39: "add.64\\t.sp,%0") ! 40: ! 41: (define_insn "" ! 42: [(set (reg:SI 15) ! 43: (plus:SI (match_operand:SI 0 "general_operand" "g") ! 44: (reg:SI 15)))] ! 45: "" ! 46: "add.64\\t.sp,%0") ! 47: ! 48: (define_insn "" ! 49: [(set (match_operand:SI 0 "register_operand" "r") ! 50: (plus:SI (reg:SI 15) ! 51: (match_operand:SI 1 "general_operand" "g")))] ! 52: "" ! 53: "ld.32\\t%0,.sp\;add.64\\t%0,%1") ! 54: ! 55: (define_insn "" ! 56: [(set (match_operand:SI 0 "register_operand" "r") ! 57: (plus:SI (match_operand:SI 1 "general_operand" "g") ! 58: (reg:SI 15)))] ! 59: "" ! 60: "ld.32\\t%0,.sp\;add.64\\t%0,%1") ! 61: ! 62: (define_insn "" ! 63: [(set (reg:SI 15) ! 64: (minus:SI (reg:SI 15) ! 65: (match_operand:SI 0 "general_operand" "g")))] ! 66: "" ! 67: "sub.64\\t.sp,%0") ! 68: ! 69: (define_insn "" ! 70: [(set (reg:SI 15) ! 71: (match_operand:SI 0 "general_operand" "rm"))] ! 72: "" ! 73: "ld.32\\t.sp,%0") ! 74: ! 75: (define_insn "" ! 76: [(set (match_operand:SI 0 "general_operand" "m,r") ! 77: (reg:SI 15))] ! 78: "" ! 79: "* ! 80: if (which_alternative == 0) ! 81: return \"st.32\\t.sp,%0\"; ! 82: return \"ld.32\\t%0,.sp\"; ! 83: ") ! 84: ! 85: ; tstdi is first test insn so that it is the one to match ! 86: ; a constant argument. ! 87: ! 88: (define_insn "tstdi" ! 89: [(set (cc0) ! 90: (match_operand:DI 0 "register_operand" "r"))] ! 91: "" ! 92: "* ! 93: extern rtx cmp_op0, cmp_op1; ! 94: cmp_op0=operands[0]; cmp_op1=0; ! 95: return \";\\ttstdi\\t%0\"; ! 96: ") ! 97: ! 98: (define_insn "tstdf" ! 99: [(set (cc0) ! 100: (match_operand:DF 0 "register_operand" "r"))] ! 101: "" ! 102: "* ! 103: extern rtx cmp_op0, cmp_op1; ! 104: cmp_op0=operands[0]; cmp_op1=0; ! 105: return \";\\ttstdf\\t%0\"; ! 106: ") ! 107: ! 108: (define_insn "tstsf" ! 109: [(set (cc0) ! 110: (match_operand:SF 0 "register_operand" "r"))] ! 111: "" ! 112: "* ! 113: extern rtx cmp_op0, cmp_op1; ! 114: cmp_op0=operands[0]; cmp_op1=0; ! 115: return \";\\ttstsf\\t%0\"; ! 116: ") ! 117: ! 118: (define_insn "cmpdi" ! 119: [(set (cc0) ! 120: (compare (match_operand:DI 0 "register_operand" "r") ! 121: (match_operand:DI 1 "general_operand" "rm")))] ! 122: "" ! 123: "* ! 124: extern rtx cmp_op0, cmp_op1; ! 125: cmp_op0=operands[0]; cmp_op1=operands[1]; ! 126: return \";\\tcmpdi\\t%0,%1\"; ! 127: ") ! 128: ! 129: (define_insn "cmpdf" ! 130: [(set (cc0) ! 131: (compare (match_operand:DF 0 "register_operand" "r") ! 132: (match_operand:DF 1 "general_operand" "rm")))] ! 133: "" ! 134: "* ! 135: extern rtx cmp_op0, cmp_op1; ! 136: cmp_op0=operands[0]; cmp_op1=operands[1]; ! 137: return \";\\tcmpdf\\t%0,%1\"; ! 138: ") ! 139: ! 140: (define_insn "cmpsf" ! 141: [(set (cc0) ! 142: (compare (match_operand:SF 0 "register_operand" "r") ! 143: (match_operand:SF 1 "general_operand" "rm")))] ! 144: "" ! 145: "* ! 146: extern rtx cmp_op0, cmp_op1; ! 147: cmp_op0=operands[0]; cmp_op1=operands[1]; ! 148: return \";\\tcmpsf\\t%0,%1\"; ! 149: ") ! 150: ! 151: (define_insn "" ! 152: [(set (match_operand:DI 0 "register_operand" "=r") ! 153: (eq (match_operand:DI 1 "register_operand" "r") ! 154: (match_operand:DI 2 "general_operand" "g")))] ! 155: "" ! 156: "cmp.64\\t%0,%1,%2:eq") ! 157: ! 158: (define_insn "" ! 159: [(set (match_operand:DI 0 "register_operand" "=r") ! 160: (ne (match_operand:DI 1 "register_operand" "r") ! 161: (match_operand:DI 2 "general_operand" "g")))] ! 162: "" ! 163: "cmp.64\\t%0,%1,%2:ne") ! 164: ! 165: (define_insn "" ! 166: [(set (match_operand:DI 0 "register_operand" "=r") ! 167: (le (match_operand:DI 1 "register_operand" "r") ! 168: (match_operand:DI 2 "general_operand" "g")))] ! 169: "" ! 170: "cmp.64\\t%0,%1,%2:le") ! 171: ! 172: (define_insn "" ! 173: [(set (match_operand:DI 0 "register_operand" "=r") ! 174: (leu (match_operand:DI 1 "register_operand" "r") ! 175: (match_operand:DI 2 "general_operand" "g")))] ! 176: "" ! 177: "cmpu.64\\t%0,%1,%2:le") ! 178: ! 179: (define_insn "" ! 180: [(set (match_operand:DI 0 "register_operand" "=r") ! 181: (lt (match_operand:DI 1 "register_operand" "r") ! 182: (match_operand:DI 2 "general_operand" "g")))] ! 183: "" ! 184: "cmp.64\\t%0,%1,%2:lt") ! 185: ! 186: (define_insn "" ! 187: [(set (match_operand:DI 0 "register_operand" "=r") ! 188: (ltu (match_operand:DI 1 "register_operand" "r") ! 189: (match_operand:DI 2 "general_operand" "g")))] ! 190: "" ! 191: "cmpu.64\\t%0,%1,%2:lt") ! 192: ! 193: (define_insn "" ! 194: [(set (match_operand:DI 0 "register_operand" "=r") ! 195: (ge (match_operand:DI 1 "register_operand" "r") ! 196: (match_operand:DI 2 "general_operand" "g")))] ! 197: "" ! 198: "cmp.64\\t%0,%1,%2:ge") ! 199: ! 200: (define_insn "" ! 201: [(set (match_operand:DI 0 "register_operand" "=r") ! 202: (geu (match_operand:DI 1 "register_operand" "r") ! 203: (match_operand:DI 2 "general_operand" "g")))] ! 204: "" ! 205: "cmpu.64\\t%0,%1,%2:ge") ! 206: ! 207: (define_insn "" ! 208: [(set (match_operand:DI 0 "register_operand" "=r") ! 209: (gt (match_operand:DI 1 "register_operand" "r") ! 210: (match_operand:DI 2 "general_operand" "g")))] ! 211: "" ! 212: "cmp.64\\t%0,%1,%2:gt") ! 213: ! 214: (define_insn "" ! 215: [(set (match_operand:DI 0 "register_operand" "=r") ! 216: (gtu (match_operand:DI 1 "register_operand" "r") ! 217: (match_operand:DI 2 "general_operand" "g")))] ! 218: "" ! 219: "cmpu.64\\t%0,%1,%2:gt") ! 220: ! 221: (define_insn "seq" ! 222: [(set (match_operand:DI 0 "register_operand" "=r") ! 223: (eq (cc0) (const_int 0)))] ! 224: "" ! 225: "* return cmp_set(\"\", \"eq\", operands[0]); ") ! 226: ! 227: (define_insn "sne" ! 228: [(set (match_operand:DI 0 "register_operand" "=r") ! 229: (ne (cc0) (const_int 0)))] ! 230: "" ! 231: "* return cmp_set(\"\", \"ne\", operands[0]); ") ! 232: ! 233: (define_insn "sle" ! 234: [(set (match_operand:DI 0 "register_operand" "=r") ! 235: (le (cc0) (const_int 0)))] ! 236: "" ! 237: "* return cmp_set(\"\", \"le\", operands[0]); ") ! 238: ! 239: (define_insn "sleu" ! 240: [(set (match_operand:DI 0 "register_operand" "=r") ! 241: (leu (cc0) (const_int 0)))] ! 242: "" ! 243: "* return cmp_set(\"u\", \"le\", operands[0]); ") ! 244: ! 245: (define_insn "slt" ! 246: [(set (match_operand:DI 0 "register_operand" "=r") ! 247: (lt (cc0) (const_int 0)))] ! 248: "" ! 249: "* return cmp_set(\"\", \"lt\", operands[0]); ") ! 250: ! 251: (define_insn "sltu" ! 252: [(set (match_operand:DI 0 "register_operand" "=r") ! 253: (ltu (cc0) (const_int 0)))] ! 254: "" ! 255: "* return cmp_set(\"u\", \"lt\", operands[0]); ") ! 256: ! 257: (define_insn "sge" ! 258: [(set (match_operand:DI 0 "register_operand" "=r") ! 259: (ge (cc0) (const_int 0)))] ! 260: "" ! 261: "* return cmp_set(\"\", \"ge\", operands[0]); ") ! 262: ! 263: (define_insn "sgeu" ! 264: [(set (match_operand:DI 0 "register_operand" "=r") ! 265: (geu (cc0) (const_int 0)))] ! 266: "" ! 267: "* return cmp_set(\"u\", \"ge\", operands[0]); ") ! 268: ! 269: (define_insn "sgt" ! 270: [(set (match_operand:DI 0 "register_operand" "=r") ! 271: (gt (cc0) (const_int 0)))] ! 272: "" ! 273: "* return cmp_set(\"\", \"gt\", operands[0]); ") ! 274: ! 275: (define_insn "sgtu" ! 276: [(set (match_operand:DI 0 "register_operand" "=r") ! 277: (gtu (cc0) (const_int 0)))] ! 278: "" ! 279: "* return cmp_set(\"u\", \"gt\", operands[0]); ") ! 280: ! 281: (define_insn "" ! 282: [(set (match_operand:SI 0 "register_operand" "=r") ! 283: (eq (match_operand:SI 1 "register_operand" "r") ! 284: (match_operand:SI 2 "general_operand" "m")))] ! 285: "" ! 286: "cmp.32\\t%0,%1,%2:eq") ! 287: ! 288: (define_insn "" ! 289: [(set (match_operand:SI 0 "register_operand" "=r") ! 290: (ne (match_operand:SI 1 "register_operand" "r") ! 291: (match_operand:SI 2 "general_operand" "m")))] ! 292: "" ! 293: "cmp.32\\t%0,%1,%2:ne") ! 294: ! 295: (define_insn "" ! 296: [(set (match_operand:SI 0 "register_operand" "=r") ! 297: (le (match_operand:SI 1 "register_operand" "r") ! 298: (match_operand:SI 2 "general_operand" "m")))] ! 299: "" ! 300: "cmp.32\\t%0,%1,%2:le") ! 301: ! 302: (define_insn "" ! 303: [(set (match_operand:SI 0 "register_operand" "=r") ! 304: (leu (match_operand:SI 1 "register_operand" "r") ! 305: (match_operand:SI 2 "general_operand" "m")))] ! 306: "" ! 307: "cmpu.32\\t%0,%1,%2:le") ! 308: ! 309: (define_insn "" ! 310: [(set (match_operand:SI 0 "register_operand" "=r") ! 311: (lt (match_operand:SI 1 "register_operand" "r") ! 312: (match_operand:SI 2 "general_operand" "m")))] ! 313: "" ! 314: "cmp.32\\t%0,%1,%2:lt") ! 315: ! 316: (define_insn "" ! 317: [(set (match_operand:SI 0 "register_operand" "=r") ! 318: (ltu (match_operand:SI 1 "register_operand" "r") ! 319: (match_operand:SI 2 "general_operand" "m")))] ! 320: "" ! 321: "cmpu.32\\t%0,%1,%2:lt") ! 322: ! 323: (define_insn "" ! 324: [(set (match_operand:SI 0 "register_operand" "=r") ! 325: (ge (match_operand:SI 1 "register_operand" "r") ! 326: (match_operand:SI 2 "general_operand" "m")))] ! 327: "" ! 328: "cmp.32\\t%0,%1,%2:ge") ! 329: ! 330: (define_insn "" ! 331: [(set (match_operand:SI 0 "register_operand" "=r") ! 332: (geu (match_operand:SI 1 "register_operand" "r") ! 333: (match_operand:SI 2 "general_operand" "m")))] ! 334: "" ! 335: "cmpu.32\\t%0,%1,%2:ge") ! 336: ! 337: (define_insn "" ! 338: [(set (match_operand:SI 0 "register_operand" "=r") ! 339: (gt (match_operand:SI 1 "register_operand" "r") ! 340: (match_operand:SI 2 "general_operand" "m")))] ! 341: "" ! 342: "cmp.32\\t%0,%1,%2:gt") ! 343: ! 344: (define_insn "" ! 345: [(set (match_operand:SI 0 "register_operand" "=r") ! 346: (gtu (match_operand:SI 1 "register_operand" "r") ! 347: (match_operand:SI 2 "general_operand" "m")))] ! 348: "" ! 349: "cmpu.32\\t%0,%1,%2:gt") ! 350: ! 351: (define_insn "" ! 352: [(set (match_operand:HI 0 "register_operand" "=r") ! 353: (eq (match_operand:HI 1 "register_operand" "r") ! 354: (match_operand:HI 2 "general_operand" "m")))] ! 355: "" ! 356: "cmp.16\\t%0,%1,%2:eq") ! 357: ! 358: (define_insn "" ! 359: [(set (match_operand:HI 0 "register_operand" "=r") ! 360: (ne (match_operand:HI 1 "register_operand" "r") ! 361: (match_operand:HI 2 "general_operand" "m")))] ! 362: "" ! 363: "cmp.16\\t%0,%1,%2:ne") ! 364: ! 365: (define_insn "" ! 366: [(set (match_operand:HI 0 "register_operand" "=r") ! 367: (le (match_operand:HI 1 "register_operand" "r") ! 368: (match_operand:HI 2 "general_operand" "m")))] ! 369: "" ! 370: "cmp.16\\t%0,%1,%2:le") ! 371: ! 372: (define_insn "" ! 373: [(set (match_operand:HI 0 "register_operand" "=r") ! 374: (leu (match_operand:HI 1 "register_operand" "r") ! 375: (match_operand:HI 2 "general_operand" "m")))] ! 376: "" ! 377: "cmpu.16\\t%0,%1,%2:le") ! 378: ! 379: (define_insn "" ! 380: [(set (match_operand:HI 0 "register_operand" "=r") ! 381: (lt (match_operand:HI 1 "register_operand" "r") ! 382: (match_operand:HI 2 "general_operand" "m")))] ! 383: "" ! 384: "cmp.16\\t%0,%1,%2:lt") ! 385: ! 386: (define_insn "" ! 387: [(set (match_operand:HI 0 "register_operand" "=r") ! 388: (ltu (match_operand:HI 1 "register_operand" "r") ! 389: (match_operand:HI 2 "general_operand" "m")))] ! 390: "" ! 391: "cmpu.16\\t%0,%1,%2:lt") ! 392: ! 393: (define_insn "" ! 394: [(set (match_operand:HI 0 "register_operand" "=r") ! 395: (ge (match_operand:HI 1 "register_operand" "r") ! 396: (match_operand:HI 2 "general_operand" "m")))] ! 397: "" ! 398: "cmp.16\\t%0,%1,%2:ge") ! 399: ! 400: (define_insn "" ! 401: [(set (match_operand:HI 0 "register_operand" "=r") ! 402: (geu (match_operand:HI 1 "register_operand" "r") ! 403: (match_operand:HI 2 "general_operand" "m")))] ! 404: "" ! 405: "cmpu.16\\t%0,%1,%2:ge") ! 406: ! 407: (define_insn "" ! 408: [(set (match_operand:HI 0 "register_operand" "=r") ! 409: (gt (match_operand:HI 1 "register_operand" "r") ! 410: (match_operand:HI 2 "general_operand" "m")))] ! 411: "" ! 412: "cmp.16\\t%0,%1,%2:gt") ! 413: ! 414: (define_insn "" ! 415: [(set (match_operand:HI 0 "register_operand" "=r") ! 416: (gtu (match_operand:HI 1 "register_operand" "r") ! 417: (match_operand:HI 2 "general_operand" "m")))] ! 418: "" ! 419: "cmpu.16\\t%0,%1,%2:gt") ! 420: ! 421: (define_insn "" ! 422: [(set (match_operand:QI 0 "register_operand" "=r") ! 423: (eq (match_operand:QI 1 "register_operand" "r") ! 424: (match_operand:QI 2 "general_operand" "m")))] ! 425: "" ! 426: "cmp.8\\t%0,%1,%2:eq") ! 427: ! 428: (define_insn "" ! 429: [(set (match_operand:QI 0 "register_operand" "=r") ! 430: (ne (match_operand:QI 1 "register_operand" "r") ! 431: (match_operand:QI 2 "general_operand" "m")))] ! 432: "" ! 433: "cmp.8\\t%0,%1,%2:ne") ! 434: ! 435: (define_insn "" ! 436: [(set (match_operand:QI 0 "register_operand" "=r") ! 437: (le (match_operand:QI 1 "register_operand" "r") ! 438: (match_operand:QI 2 "general_operand" "m")))] ! 439: "" ! 440: "cmp.8\\t%0,%1,%2:le") ! 441: ! 442: (define_insn "" ! 443: [(set (match_operand:QI 0 "register_operand" "=r") ! 444: (leu (match_operand:QI 1 "register_operand" "r") ! 445: (match_operand:QI 2 "general_operand" "m")))] ! 446: "" ! 447: "cmpu.8\\t%0,%1,%2:le") ! 448: ! 449: (define_insn "" ! 450: [(set (match_operand:QI 0 "register_operand" "=r") ! 451: (lt (match_operand:QI 1 "register_operand" "r") ! 452: (match_operand:QI 2 "general_operand" "m")))] ! 453: "" ! 454: "cmp.8\\t%0,%1,%2:lt") ! 455: ! 456: (define_insn "" ! 457: [(set (match_operand:QI 0 "register_operand" "=r") ! 458: (ltu (match_operand:QI 1 "register_operand" "r") ! 459: (match_operand:QI 2 "general_operand" "m")))] ! 460: "" ! 461: "cmpu.8\\t%0,%1,%2:lt") ! 462: ! 463: (define_insn "" ! 464: [(set (match_operand:QI 0 "register_operand" "=r") ! 465: (ge (match_operand:QI 1 "register_operand" "r") ! 466: (match_operand:QI 2 "general_operand" "m")))] ! 467: "" ! 468: "cmp.8\\t%0,%1,%2:ge") ! 469: ! 470: (define_insn "" ! 471: [(set (match_operand:QI 0 "register_operand" "=r") ! 472: (geu (match_operand:QI 1 "register_operand" "r") ! 473: (match_operand:QI 2 "general_operand" "m")))] ! 474: "" ! 475: "cmpu.8\\t%0,%1,%2:ge") ! 476: ! 477: (define_insn "" ! 478: [(set (match_operand:QI 0 "register_operand" "=r") ! 479: (gt (match_operand:QI 1 "register_operand" "r") ! 480: (match_operand:QI 2 "general_operand" "m")))] ! 481: "" ! 482: "cmp.8\\t%0,%1,%2:gt") ! 483: ! 484: (define_insn "" ! 485: [(set (match_operand:QI 0 "register_operand" "=r") ! 486: (gtu (match_operand:QI 1 "register_operand" "r") ! 487: (match_operand:QI 2 "general_operand" "m")))] ! 488: "" ! 489: "cmpu.8\\t%0,%1,%2:gt") ! 490: ! 491: ! 492: ! 493: (define_insn "movdf" [(set (match_operand:DF 0 "general_operand" "=r,m") ! 494: (match_operand:DF 1 "general_operand" "rm,r"))] ! 495: "" ! 496: "* ! 497: { ! 498: if (which_alternative == 0) ! 499: return \"ld.64\\t%0,%1\"; ! 500: return \"st.64\\t%1,%0\"; ! 501: }") ! 502: ! 503: (define_insn "movsf" ! 504: [(set (match_operand:SF 0 "general_operand" "=r,m") ! 505: (match_operand:SF 1 "general_operand" "rm,r"))] ! 506: "" ! 507: "* ! 508: { ! 509: if (which_alternative == 0) ! 510: return \"ld.32\\t%0,%1\"; ! 511: return \"st.32\\t%1,%0\"; ! 512: }") ! 513: ! 514: (define_insn "movdi" ! 515: [(set (match_operand:DI 0 "general_operand" "=r,m,rm") ! 516: (match_operand:DI 1 "general_operand" "g,r,I"))] ! 517: "" ! 518: "* ! 519: if (which_alternative == 0) ! 520: return \"ld.64\\t%0,%1\"; ! 521: else if (which_alternative == 1) ! 522: return \"st.64\\t%1,%0\"; ! 523: else ! 524: if (GET_CODE(operands[1])==CONST_INT) { ! 525: if (INTVAL(operands[1]) >= 0) ! 526: return \"sti.64\\t%c1,%0\"; ! 527: else ! 528: return \"stin.64\\t%n1,%0\"; ! 529: } ! 530: ") ! 531: ! 532: (define_insn "movsi" ! 533: [(set (match_operand:SI 0 "general_operand" "=r,m,r") ! 534: (match_operand:SI 1 "general_operand" "rm,rI,i"))] ! 535: "" ! 536: "* ! 537: if (which_alternative == 0) ! 538: return \"ld.32\\t%0,%1\"; ! 539: else if (which_alternative == 1) { ! 540: if (GET_CODE(operands[1])==CONST_INT) { ! 541: if (INTVAL(operands[1]) >= 0) ! 542: return \"sti.32\\t%c1,%0\"; ! 543: else ! 544: return \"stin.32\\t%n1,%0\"; ! 545: } ! 546: return \"st.32\\t%1,%0\"; ! 547: } else ! 548: return \"ld.64\\t%0,%1 ; I only want 32\"; ! 549: ") ! 550: ! 551: (define_insn "movhi" ! 552: [(set (match_operand:HI 0 "general_operand" "=r,m,r") ! 553: (match_operand:HI 1 "general_operand" "m,rI,ri"))] ! 554: "" ! 555: "* ! 556: { ! 557: if (which_alternative == 0) ! 558: return \"ld.16\\t%0,%1\"; ! 559: if (which_alternative == 2) ! 560: return \"ld.64\\t%0,%1\\t; I only want 16\"; ! 561: if (GET_CODE(operands[1])==CONST_INT) { ! 562: if (INTVAL(operands[1]) >= 0) ! 563: return \"sti.16\\t%c1,%0\"; ! 564: else ! 565: return \"stin.16\\t%n1,%0\"; ! 566: } ! 567: return \"st.16\\t%1,%0\"; ! 568: }") ! 569: ! 570: (define_insn "movqi" ! 571: [(set (match_operand:QI 0 "general_operand" "=r,m,r") ! 572: (match_operand:QI 1 "general_operand" "m,rI,ri"))] ! 573: "" ! 574: "* ! 575: { ! 576: if (which_alternative == 0) ! 577: return \"ld.8\\t%0,%1\"; ! 578: if (which_alternative == 2) ! 579: return \"ld.64\\t%0,%1\\t; I only want 8\"; ! 580: if (GET_CODE(operands[1])==CONST_INT) { ! 581: if (INTVAL(operands[1]) >= 0) ! 582: return \"sti.8\\t%c1,%0\"; ! 583: else ! 584: return \"stin.8\\t%n1,%0\"; ! 585: } ! 586: return \"st.8\\t%1,%0\"; ! 587: }") ! 588: ! 589: ;; Extension and truncation insns. ! 590: ;; Those for integer source operand ! 591: ;; are ordered widest source type first. ! 592: ! 593: (define_insn "truncdfsf2" ! 594: [(set (match_operand:SF 0 "register_operand" "=r") ! 595: (truncate:SF (match_operand:DF 1 "general_operand" "rm")))] ! 596: "" ! 597: "cvt.ds\\t%0,%1") ! 598: ! 599: (define_insn "truncdiqi2" ! 600: [(set (match_operand:QI 0 "general_operand" "=r,m,r") ! 601: (truncate:QI (match_operand:DI 1 "general_operand" "m,r,0")))] ! 602: "" ! 603: "* ! 604: { ! 605: if (which_alternative == 0) ! 606: return \"ld.8\\t%0,%1\"; ! 607: else if (which_alternative == 1) ! 608: return \"st.8\\t%1,%0\"; ! 609: return \"\"; ! 610: }") ! 611: ! 612: (define_insn "truncdihi2" ! 613: [(set (match_operand:HI 0 "general_operand" "=r,m,r") ! 614: (truncate:HI (match_operand:DI 1 "general_operand" "m,r,0")))] ! 615: "" ! 616: "* ! 617: { ! 618: if (which_alternative == 0) ! 619: return \"ld.16\\t%0,%1\"; ! 620: if (which_alternative == 1) ! 621: return \"st.16\\t%1,%0\"; ! 622: return \"\"; ! 623: }") ! 624: ! 625: (define_insn "truncdisi2" ! 626: [(set (match_operand:SI 0 "general_operand" "=r,m") ! 627: (truncate:SI (match_operand:DI 1 "general_operand" "rm,r")))] ! 628: "" ! 629: "* ! 630: { ! 631: if (which_alternative == 0) ! 632: return \"ld.32\\t%0,%1\"; ! 633: return \"st.32\\t%1,%0\"; ! 634: }") ! 635: ! 636: (define_insn "truncsiqi2" ! 637: [(set (match_operand:QI 0 "general_operand" "=r,m,r") ! 638: (truncate:QI (match_operand:SI 1 "general_operand" "m,r,0")))] ! 639: "" ! 640: "* ! 641: { ! 642: if (which_alternative == 0) ! 643: return \"ld.8\\t%0,%1\"; ! 644: if (which_alternative == 1) ! 645: return \"st.8\\t%1,%0\"; ! 646: return \"\"; ! 647: }") ! 648: ! 649: (define_insn "truncsihi2" ! 650: [(set (match_operand:HI 0 "general_operand" "=r,m,r") ! 651: (truncate:HI (match_operand:SI 1 "general_operand" "m,r,0")))] ! 652: "" ! 653: "* ! 654: { ! 655: if (which_alternative == 0) ! 656: return \"ld.16\\t%0,%1\"; ! 657: if (which_alternative == 1) ! 658: return \"st.16\\t%1,%0\"; ! 659: return \"\"; ! 660: }") ! 661: ! 662: (define_insn "trunchiqi2" ! 663: [(set (match_operand:QI 0 "general_operand" "=r,m,r") ! 664: (truncate:QI (match_operand:HI 1 "general_operand" "m,r,0")))] ! 665: "" ! 666: "* ! 667: { ! 668: if (which_alternative == 0) ! 669: return \"ld.8\\t%0,%1\"; ! 670: if (which_alternative == 1) ! 671: return \"st.8\\t%1,%0\"; ! 672: return \"\"; ! 673: }") ! 674: ! 675: (define_insn "extendsfdf2" ! 676: [(set (match_operand:DF 0 "register_operand" "=r") ! 677: (sign_extend:DF (match_operand:SF 1 "general_operand" "rm")))] ! 678: "" ! 679: "cvt.sd\\t%0,%1") ! 680: ! 681: (define_insn "extendsidi2" ! 682: [(set (match_operand:DI 0 "register_operand" "=r") ! 683: (sign_extend:DI (match_operand:SI 1 "general_operand" "rm")))] ! 684: "" ! 685: "ld.32\\t%0,%1") ! 686: ! 687: (define_insn "extendhisi2" ! 688: [(set (match_operand:SI 0 "register_operand" "=r,r") ! 689: (sign_extend:SI (match_operand:HI 1 "general_operand" "m,r")))] ! 690: "" ! 691: "* ! 692: if (which_alternative==0) ! 693: return \"ld.16\\t%0,%1\"; ! 694: return \"extract\\t%0,%1:bit 48,16\"; ! 695: ") ! 696: ! 697: (define_insn "extendhidi2" ! 698: [(set (match_operand:DI 0 "register_operand" "=r,r") ! 699: (sign_extend:DI (match_operand:HI 1 "general_operand" "m,r")))] ! 700: "" ! 701: "* ! 702: if (which_alternative==0) ! 703: return \"ld.16\\t%0,%1\"; ! 704: return \"extract\\t%0,%1:bit 48,16\"; ! 705: ") ! 706: ! 707: (define_insn "extendqihi2" ! 708: [(set (match_operand:HI 0 "register_operand" "=r,r") ! 709: (sign_extend:HI (match_operand:QI 1 "general_operand" "m,r")))] ! 710: "" ! 711: "* ! 712: if (which_alternative==0) ! 713: return \"ld.8\\t%0,%1\"; ! 714: return \"extract\\t%0,%1:bit 56,8\"; ! 715: ") ! 716: ! 717: (define_insn "extendqisi2" ! 718: [(set (match_operand:SI 0 "register_operand" "=r,r") ! 719: (sign_extend:SI (match_operand:QI 1 "general_operand" "m,r")))] ! 720: "" ! 721: "* ! 722: if (which_alternative==0) ! 723: return \"ld.8\\t%0,%1\"; ! 724: return \"extract\\t%0,%1:bit 56,8\"; ! 725: ") ! 726: ! 727: (define_insn "extendqidi2" ! 728: [(set (match_operand:DI 0 "register_operand" "=r,r") ! 729: (sign_extend:DI (match_operand:QI 1 "general_operand" "m,r")))] ! 730: "" ! 731: "* ! 732: if (which_alternative==0) ! 733: return \"ld.8\\t%0,%1\"; ! 734: return \"extract\\t%0,%1:bit 56,8\"; ! 735: ") ! 736: ! 737: (define_insn "zero_extendsidi2" ! 738: [(set (match_operand:DI 0 "register_operand" "=r") ! 739: (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))] ! 740: "" ! 741: "ldz.32\\t%0,%1") ! 742: ! 743: ! 744: (define_insn "zero_extendhisi2" ! 745: [(set (match_operand:SI 0 "register_operand" "=r,r") ! 746: (zero_extend:SI (match_operand:HI 1 "general_operand" "m,r")))] ! 747: "" ! 748: "* ! 749: if (which_alternative==0) ! 750: return \"ldz.16\\t%0,%1\"; ! 751: return \"extractz\\t%0,%1:bit 48,16\"; ! 752: ") ! 753: ! 754: (define_insn "zero_extendhidi2" ! 755: [(set (match_operand:DI 0 "register_operand" "=r,r") ! 756: (zero_extend:DI (match_operand:HI 1 "general_operand" "m,r")))] ! 757: "" ! 758: "* ! 759: if (which_alternative==0) ! 760: return \"ldz.16\\t%0,%1\"; ! 761: return \"extractz\\t%0,%1:bit 48,16\"; ! 762: ") ! 763: ! 764: (define_insn "zero_extendqihi2" ! 765: [(set (match_operand:HI 0 "register_operand" "=r,r") ! 766: (zero_extend:HI (match_operand:QI 1 "general_operand" "m,r")))] ! 767: "" ! 768: "* ! 769: if (which_alternative==0) ! 770: return \"ldz.8\\t%0,%1\"; ! 771: return \"extractz\\t%0,%1:bit 56,8\"; ! 772: ") ! 773: ! 774: (define_insn "zero_extendqisi2" ! 775: [(set (match_operand:SI 0 "register_operand" "=r,r") ! 776: (zero_extend:SI (match_operand:QI 1 "general_operand" "m,r")))] ! 777: "" ! 778: "* ! 779: if (which_alternative==0) ! 780: return \"ldz.8\\t%0,%1\"; ! 781: return \"extractz\\t%0,%1:bit 56,8\"; ! 782: ") ! 783: ! 784: (define_insn "zero_extendqidi2" ! 785: [(set (match_operand:DI 0 "register_operand" "=r,r") ! 786: (zero_extend:DI (match_operand:QI 1 "general_operand" "m,r")))] ! 787: "" ! 788: "* ! 789: if (which_alternative==0) ! 790: return \"ldz.8\\t%0,%1\"; ! 791: return \"extractz\\t%0,%1:bit 56,8\"; ! 792: ") ! 793: ! 794: ! 795: ! 796: (define_insn "lshldi3" ! 797: [(set (match_operand:DI 0 "register_operand" "=r") ! 798: (lshift:DI (match_operand:DI 1 "register_operand" "r") ! 799: (match_operand:SI 2 "general_operand" "rn")))] ! 800: "" ! 801: "sll\\t%0,%1,%2") ! 802: ! 803: (define_insn "ashrdi3" ! 804: [(set (match_operand:DI 0 "register_operand" "=r") ! 805: (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") ! 806: (match_operand:SI 2 "general_operand" "rn")))] ! 807: "" ! 808: "sra\\t%0,%1,%2") ! 809: ! 810: (define_insn "lshrdi3" ! 811: [(set (match_operand:DI 0 "register_operand" "=r") ! 812: (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") ! 813: (match_operand:SI 2 "general_operand" "rn")))] ! 814: "" ! 815: "srl\\t%0,%1,%2") ! 816: ! 817: (define_insn "ashldi3" ! 818: [(set (match_operand:DI 0 "register_operand" "=r") ! 819: (ashift:DI (match_operand:DI 1 "register_operand" "r") ! 820: (match_operand:SI 2 "general_operand" "rn")))] ! 821: "" ! 822: "sla\\t%0,%1,%2") ! 823: ! 824: (define_insn "anddi3" ! 825: [(set (match_operand:DI 0 "register_operand" "=r,r") ! 826: (and:DI (match_operand:DI 1 "general_operand" "%0,r") ! 827: (match_operand:DI 2 "general_operand" "g,g")))] ! 828: "1 /*which_alternative == 0 || check356(operands[2])*/" ! 829: "* ! 830: if (which_alternative == 0) ! 831: return \"and\\t%0,%2\"; ! 832: return \"and\\t%0,%1,%2\"; ! 833: ") ! 834: ! 835: (define_insn "iordi3" ! 836: [(set (match_operand:DI 0 "register_operand" "=r,r") ! 837: (ior:DI (match_operand:DI 1 "general_operand" "%0,r") ! 838: (match_operand:DI 2 "general_operand" "g,g")))] ! 839: "1 /*which_alternative == 0 || check356(operands[2])*/" ! 840: "* ! 841: if (which_alternative == 0) ! 842: return \"or\\t%0,%2\"; ! 843: return \"or\\t%0,%1,%2\"; ! 844: ") ! 845: ! 846: (define_insn "xordi3" ! 847: [(set (match_operand:DI 0 "register_operand" "=r,r") ! 848: (xor:DI (match_operand:DI 1 "general_operand" "%0,r") ! 849: (match_operand:DI 2 "general_operand" "g,g")))] ! 850: "1 /*which_alternative == 0 || check356(operands[2])*/" ! 851: "* ! 852: if (which_alternative == 0) ! 853: return \"xor\\t%0,%2\"; ! 854: return \"xor\\t%0,%1,%2\"; ! 855: ") ! 856: ! 857: (define_insn "one_cmpldi2" ! 858: [(set (match_operand:DI 0 "register_operand" "=r") ! 859: (not:DI (match_operand:DI 1 "general_operand" "rm")))] ! 860: "" ! 861: "not\\t%0,%1") ! 862: ! 863: ;; gcc 2.1 does not widen ~si into ~di. ! 864: (define_insn "one_cmplsi2" ! 865: [(set (match_operand:SI 0 "register_operand" "=r") ! 866: (not:DI (match_operand:SI 1 "register_operand" "r")))] ! 867: "" ! 868: "not\\t%0,%1") ! 869: ! 870: (define_insn "negdi2" ! 871: [(set (match_operand:DI 0 "register_operand" "=r") ! 872: (neg:DI (match_operand:DI 1 "general_operand" "rm")))] ! 873: "" ! 874: "neg.64\\t%0,%1") ! 875: ! 876: (define_insn "negsi2" ! 877: [(set (match_operand:SI 0 "register_operand" "=r,r") ! 878: (neg:SI (match_operand:SI 1 "general_operand" "m,r")))] ! 879: "" ! 880: "* ! 881: if (which_alternative == 0) ! 882: return \"neg.32\\t%0,%1\"; ! 883: return \"neg.64\\t%0,%1 ; I only want 32\"; ! 884: ") ! 885: ! 886: (define_insn "neghi2" ! 887: [(set (match_operand:HI 0 "register_operand" "=r,r") ! 888: (neg:HI (match_operand:HI 1 "general_operand" "m,r")))] ! 889: "" ! 890: "* ! 891: if (which_alternative == 0) ! 892: return \"neg.16\\t%0,%1\"; ! 893: return \"neg.64\\t%0,%1 ; I only want 16\"; ! 894: ") ! 895: ! 896: (define_insn "adddf3" ! 897: [(set (match_operand:DF 0 "register_operand" "=r") ! 898: (plus:DF (match_operand:DF 1 "general_operand" "%0") ! 899: (match_operand:DF 2 "general_operand" "rm")))] ! 900: "" ! 901: "fadd.64\\t%0,%2") ! 902: ! 903: (define_insn "addsf3" ! 904: [(set (match_operand:SF 0 "register_operand" "=r") ! 905: (plus:SF (match_operand:SF 1 "general_operand" "%0") ! 906: (match_operand:SF 2 "general_operand" "rm")))] ! 907: "" ! 908: "fadd.32\\t%0,%2") ! 909: ! 910: ;; There is also an addi.64 4,.r0'' optimization ! 911: (define_insn "adddi3" ! 912: [(set (match_operand:DI 0 "register_operand" "=r,r") ! 913: (plus:DI (match_operand:DI 1 "general_operand" "%0,r") ! 914: (match_operand:DI 2 "general_operand" "g,g")))] ! 915: "1 /*which_alternative == 0 || check356(operands[2])*/" ! 916: "* ! 917: if (which_alternative == 0) ! 918: return \"add.64\\t%0,%2\"; ! 919: return \"add.64\\t%0,%1,%2\"; ! 920: ") ! 921: ! 922: (define_insn "addsi3" ! 923: [(set (match_operand:SI 0 "register_operand" "=r,r,r") ! 924: (plus:SI (match_operand:SI 1 "general_operand" "%0,r,0") ! 925: (match_operand:SI 2 "general_operand" "m,m,g")))] ! 926: "1 /*which_alternative != 1 || check356(operands[2])*/" ! 927: "* ! 928: if (which_alternative == 0) ! 929: return \"add.32\\t%0,%2\"; ! 930: if (which_alternative == 1) ! 931: return \"add.32\\t%0,%1,%2\"; ! 932: return \"add.64\\t%0,%2 ; I only want 32\"; ! 933: ") ! 934: ! 935: (define_insn "addhi3" ! 936: [(set (match_operand:HI 0 "register_operand" "=r,r,r") ! 937: (plus:HI (match_operand:HI 1 "general_operand" "%0,r,0") ! 938: (match_operand:HI 2 "general_operand" "m,m,g")))] ! 939: "1 /*which_alternative != 1 || check356(operands[2])*/" ! 940: "* ! 941: if (which_alternative == 0) ! 942: return \"add.16\\t%0,%2\"; ! 943: if (which_alternative == 1) ! 944: return \"add.16\\t%0,%1,%2\"; ! 945: return \"add.64\\t%0,%2 ; I only want 16\"; ! 946: ") ! 947: ! 948: (define_insn "subdf3" ! 949: [(set (match_operand:DF 0 "register_operand" "=r") ! 950: (minus:DF (match_operand:DF 1 "general_operand" "0") ! 951: (match_operand:DF 2 "general_operand" "rm")))] ! 952: "" ! 953: "fsub.64\\t%0,%2") ! 954: ! 955: (define_insn "subsf3" ! 956: [(set (match_operand:SF 0 "register_operand" "=r") ! 957: (minus:SF (match_operand:SF 1 "general_operand" "0") ! 958: (match_operand:SF 2 "general_operand" "rm")))] ! 959: "" ! 960: "fsub.32\\t%0,%2") ! 961: ! 962: (define_insn "subdi3" ! 963: [(set (match_operand:DI 0 "register_operand" "=r,r,r") ! 964: (minus:DI (match_operand:DI 1 "general_operand" "0,g,r") ! 965: (match_operand:DI 2 "general_operand" "g,r,g")))] ! 966: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" ! 967: "* ! 968: if (which_alternative == 0) ! 969: return \"sub.64\\t%0,%2\"; ! 970: else if (which_alternative == 1) ! 971: return \"subr.64\\t%0,%2,%1\"; ! 972: else ! 973: return \"sub.64\\t%0,%1,%2\"; ! 974: ") ! 975: ! 976: (define_insn "subsi3" ! 977: [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") ! 978: (minus:SI (match_operand:SI 1 "general_operand" "0,m,r,0") ! 979: (match_operand:SI 2 "general_operand" "m,r,m,g")))] ! 980: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" ! 981: "* ! 982: if (which_alternative == 0) ! 983: return \"sub.32\\t%0,%2\"; ! 984: else if (which_alternative == 1) ! 985: return \"subr.32\\t%0,%2,%1\"; ! 986: else if (which_alternative == 2) ! 987: return \"sub.32\\t%0,%1,%2\"; ! 988: else ! 989: return \"sub.64\\t%0,%2 ; I only want 32\"; ! 990: ") ! 991: ! 992: (define_insn "subhi3" ! 993: [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") ! 994: (minus:HI (match_operand:HI 1 "general_operand" "0,m,r,0") ! 995: (match_operand:HI 2 "general_operand" "m,r,m,g")))] ! 996: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" ! 997: "* ! 998: if (which_alternative == 0) ! 999: return \"sub.16\\t%0,%2\"; ! 1000: else if (which_alternative == 1) ! 1001: return \"subr.16\\t%0,%2,%1\"; ! 1002: else if (which_alternative == 2) ! 1003: return \"sub.16\\t%0,%1,%2\"; ! 1004: else ! 1005: return \"sub.64\\t%0,%2 ; I only want 16\"; ! 1006: ") ! 1007: ! 1008: (define_insn "muldf3" ! 1009: [(set (match_operand:DF 0 "register_operand" "=r") ! 1010: (mult:DF (match_operand:DF 1 "general_operand" "%0") ! 1011: (match_operand:DF 2 "general_operand" "rm")))] ! 1012: "" ! 1013: "fmul.64\\t%0,%2") ! 1014: ! 1015: (define_insn "mulsf3" ! 1016: [(set (match_operand:SF 0 "register_operand" "=r") ! 1017: (mult:SF (match_operand:SF 1 "general_operand" "%0") ! 1018: (match_operand:SF 2 "general_operand" "rm")))] ! 1019: "" ! 1020: "fmul.32\\t%0,%2") ! 1021: ! 1022: (define_insn "muldi3" ! 1023: [(set (match_operand:DI 0 "register_operand" "=r,r") ! 1024: (mult:DI (match_operand:DI 1 "general_operand" "%0,r") ! 1025: (match_operand:DI 2 "general_operand" "g,g")))] ! 1026: "1 /*which_alternative == 0 || check356(operands[2])*/" ! 1027: "* ! 1028: if (which_alternative == 0) ! 1029: return \"mul.64\\t%0,%2\"; ! 1030: return \"mul.64\\t%0,%1,%2\"; ! 1031: ") ! 1032: ! 1033: (define_insn "mulsi3" ! 1034: [(set (match_operand:SI 0 "register_operand" "=r,r,r") ! 1035: (mult:SI (match_operand:SI 1 "general_operand" "%0,r,0") ! 1036: (match_operand:SI 2 "general_operand" "m,m,g")))] ! 1037: "1 /*which_alternative == 0 || check356(operands[2])*/" ! 1038: "* ! 1039: if (which_alternative == 0) ! 1040: return \"mul.32\\t%0,%2\"; ! 1041: else if (which_alternative == 1) ! 1042: return \"mul.32\\t%0,%1,%2\"; ! 1043: else ! 1044: return \"mul.64\\t%0,%2 ; I only want 32\"; ! 1045: ") ! 1046: ! 1047: (define_insn "mulhi3" ! 1048: [(set (match_operand:HI 0 "register_operand" "=r,r,r") ! 1049: (mult:HI (match_operand:HI 1 "general_operand" "%0,r,0") ! 1050: (match_operand:HI 2 "general_operand" "m,m,g")))] ! 1051: "1 /*which_alternative == 0 || check356(operands[2])*/" ! 1052: "* ! 1053: if (which_alternative == 0) ! 1054: return \"mul.16\\t%0,%2\"; ! 1055: else if (which_alternative == 1) ! 1056: return \"mul.16\\t%0,%1,%2\"; ! 1057: else ! 1058: return \"mul.64\\t%0,%2 ; I only want 16\"; ! 1059: ") ! 1060: ! 1061: (define_insn "divdf3" ! 1062: [(set (match_operand:DF 0 "register_operand" "=r") ! 1063: (div:DF (match_operand:DF 1 "general_operand" "0") ! 1064: (match_operand:DF 2 "general_operand" "rm")))] ! 1065: "" ! 1066: "fdiv.64\\t%0,%2") ! 1067: ! 1068: (define_insn "divsf3" ! 1069: [(set (match_operand:SF 0 "register_operand" "=r") ! 1070: (div:SF (match_operand:SF 1 "general_operand" "0") ! 1071: (match_operand:SF 2 "general_operand" "rm")))] ! 1072: "" ! 1073: "fdiv.32\\t%0,%2") ! 1074: ! 1075: (define_insn "divdi3" ! 1076: [(set (match_operand:DI 0 "register_operand" "=r,r,r") ! 1077: (div:DI (match_operand:DI 1 "general_operand" "0,g,r") ! 1078: (match_operand:DI 2 "general_operand" "g,r,g")))] ! 1079: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" ! 1080: "* ! 1081: if (which_alternative == 0) ! 1082: return \"div.64\\t%0,%2\"; ! 1083: else if (which_alternative == 1) ! 1084: return \"divr.64\\t%0,%2,%1\"; ! 1085: else ! 1086: return \"div.64\\t%0,%1,%2\"; ! 1087: ") ! 1088: ! 1089: (define_insn "divsi3" ! 1090: [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") ! 1091: (div:SI (match_operand:SI 1 "general_operand" "0,m,r,0") ! 1092: (match_operand:SI 2 "general_operand" "m,r,m,g")))] ! 1093: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" ! 1094: "* ! 1095: /* We don't ignore high bits. */ ! 1096: if (0) { ! 1097: if (which_alternative == 0) ! 1098: return \"div.32\\t%0,%2\"; ! 1099: else if (which_alternative == 1) ! 1100: return \"divr.32\\t%0,%2,%1\"; ! 1101: else if (which_alternative == 2) ! 1102: return \"div.32\\t%0,%1,%2\"; ! 1103: else ! 1104: return \"ld.32\\t%0,%0\;div.64\\t%0,%2 ; I only want 32\"; ! 1105: } else { ! 1106: if (which_alternative == 0) ! 1107: return \"ld.32\\t%0,%0\;div.32\\t%0,%2\"; ! 1108: else if (which_alternative == 1) ! 1109: return \"ld.32\\t%2,%2\;divr.32\\t%0,%2,%1\"; ! 1110: else if (which_alternative == 2) ! 1111: return \"ld.32\\t%1,%1\;div.32\\t%0,%1,%2\"; ! 1112: else ! 1113: return \"ld.32\\t%0,%0\;div.64\\t%0,%2 ; I only want 32\"; ! 1114: } ! 1115: ") ! 1116: ! 1117: (define_insn "divhi3" ! 1118: [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") ! 1119: (div:HI (match_operand:HI 1 "general_operand" "0,m,r,0,0") ! 1120: (match_operand:HI 2 "general_operand" "m,r,m,r,i")))] ! 1121: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" ! 1122: "* ! 1123: if (which_alternative == 0) ! 1124: return \"extract\\t%0,%0:bit 48,16\;div.16\\t%0,%2\"; ! 1125: else if (which_alternative == 1) ! 1126: return \"extract\\t%2,%2:bit 48,16\;divr.16\\t%0,%2,%1\"; ! 1127: else if (which_alternative == 2) ! 1128: return \"extract\\t%1,%1:bit 48,16\;div.16\\t%0,%1,%2\"; ! 1129: else if (which_alternative == 3) ! 1130: return \"extract\\t%0,%0:bit 48,16\;extract\\t%2,%2:bit 48,16\;div.64\\t%0,%2 ; I only want 16\"; ! 1131: else ! 1132: return \"extract\\t%0,%0:bit 48,16\;div.64\\t%0,%2 ; I only want 16\"; ! 1133: ") ! 1134: ! 1135: (define_insn "modhi3" ! 1136: [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") ! 1137: (mod:HI (match_operand:HI 1 "general_operand" "0,m,r,0,0") ! 1138: (match_operand:HI 2 "general_operand" "m,r,m,r,i")))] ! 1139: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" ! 1140: "* ! 1141: if (which_alternative == 0) ! 1142: return \"extract\\t%0,%0:bit 48,16\;rem.16\\t%0,%2\"; ! 1143: else if (which_alternative == 1) ! 1144: return \"extract\\t%2,%2:bit 48,16\;remr.16\\t%0,%2,%1\"; ! 1145: else if (which_alternative == 2) ! 1146: return \"extract\\t%1,%1:bit 48,16\;rem.16\\t%0,%1,%2\"; ! 1147: else if (which_alternative == 3) ! 1148: return \"extract\\t%0,%0:bit 48,16\;extract\\t%2,%2:bit 48,16\;rem.64\\t%0,%2 ; I only want 16\"; ! 1149: else ! 1150: return \"extract\\t%0,%0:bit 48,16\;rem.64\\t%0,%2 ; I only want 16\"; ! 1151: ") ! 1152: ! 1153: (define_insn "moddi3" ! 1154: [(set (match_operand:DI 0 "register_operand" "=r,r,r") ! 1155: (mod:DI (match_operand:DI 1 "general_operand" "0,g,r") ! 1156: (match_operand:DI 2 "general_operand" "g,r,g")))] ! 1157: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" ! 1158: "* ! 1159: if (which_alternative == 0) ! 1160: return \"rem.64\\t%0,%2\"; ! 1161: else if (which_alternative == 1) ! 1162: return \"remr.64\\t%0,%2,%1\"; ! 1163: else ! 1164: return \"rem.64\\t%0,%1,%2\"; ! 1165: ") ! 1166: ! 1167: (define_insn "modsi3" ! 1168: [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") ! 1169: (mod:SI (match_operand:SI 1 "general_operand" "0,m,r,0") ! 1170: (match_operand:SI 2 "general_operand" "m,r,m,g")))] ! 1171: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" ! 1172: "* ! 1173: /* There is a micro code bug with the below... */ ! 1174: if (0) { ! 1175: if (which_alternative == 0) ! 1176: return \"rem.32\\t%0,%2\"; ! 1177: else if (which_alternative == 1) ! 1178: return \"remr.32\\t%0,%2,%1\"; ! 1179: else if (which_alternative == 2) ! 1180: return \"rem.32\\t%0,%1,%2\"; ! 1181: else ! 1182: return \"ld.32\\t%0,%0\;rem.64\\t%0,%2 ; I only want 32\"; ! 1183: } else { ! 1184: if (which_alternative == 0) ! 1185: return \"ld.32\\t%0,%0\;rem.32\\t%0,%2\"; ! 1186: else if (which_alternative == 1) ! 1187: return \"ld.32\\t%2,%2\;remr.32\\t%0,%2,%1\"; ! 1188: else if (which_alternative == 2) ! 1189: return \"ld.32\\t%1,%1\;rem.32\\t%0,%1,%2\"; ! 1190: else ! 1191: return \"ld.32\\t%0,%0\;rem.64\\t%0,%2 ; I only want 32\"; ! 1192: } ! 1193: ") ! 1194: ! 1195: ! 1196: (define_insn "jump" ! 1197: [(set (pc) ! 1198: (label_ref (match_operand 0 "" "")))] ! 1199: "" ! 1200: "jmp\\t%l0") ! 1201: ! 1202: (define_insn "indirect_jump" ! 1203: [(set (pc) (match_operand:SI 0 "register_operand" "r"))] ! 1204: "" ! 1205: ;; Maybe %l0 is better, maybe we can relax register only. ! 1206: "verify this before use ld.32\\t.r0,%0\;br.reg\\t.r0") ! 1207: ! 1208: (define_insn "beq" ! 1209: [(set (pc) ! 1210: (if_then_else (eq (cc0) ! 1211: (const_int 0)) ! 1212: (label_ref (match_operand 0 "" "")) ! 1213: (pc)))] ! 1214: "" ! 1215: "* return cmp_jmp(\"\", 2, operands[0]); ") ! 1216: ! 1217: (define_insn "bne" ! 1218: [(set (pc) ! 1219: (if_then_else (ne (cc0) ! 1220: (const_int 0)) ! 1221: (label_ref (match_operand 0 "" "")) ! 1222: (pc)))] ! 1223: "" ! 1224: "* return cmp_jmp(\"\", 8, operands[0]); ") ! 1225: ! 1226: (define_insn "bgt" ! 1227: [(set (pc) ! 1228: (if_then_else (gt (cc0) ! 1229: (const_int 0)) ! 1230: (label_ref (match_operand 0 "" "")) ! 1231: (pc)))] ! 1232: "" ! 1233: "* return cmp_jmp(\"\", 0, operands[0]); ") ! 1234: ! 1235: (define_insn "bgtu" ! 1236: [(set (pc) ! 1237: (if_then_else (gtu (cc0) ! 1238: (const_int 0)) ! 1239: (label_ref (match_operand 0 "" "")) ! 1240: (pc)))] ! 1241: "" ! 1242: "* return cmp_jmp(\"u\", 0, operands[0]); ") ! 1243: ! 1244: (define_insn "blt" ! 1245: [(set (pc) ! 1246: (if_then_else (lt (cc0) ! 1247: (const_int 0)) ! 1248: (label_ref (match_operand 0 "" "")) ! 1249: (pc)))] ! 1250: "" ! 1251: "* return cmp_jmp(\"\", 6, operands[0]); ") ! 1252: ! 1253: (define_insn "bltu" ! 1254: [(set (pc) ! 1255: (if_then_else (ltu (cc0) ! 1256: (const_int 0)) ! 1257: (label_ref (match_operand 0 "" "")) ! 1258: (pc)))] ! 1259: "" ! 1260: "* return cmp_jmp(\"u\", 6, operands[0]); ") ! 1261: ! 1262: (define_insn "bge" ! 1263: [(set (pc) ! 1264: (if_then_else (ge (cc0) ! 1265: (const_int 0)) ! 1266: (label_ref (match_operand 0 "" "")) ! 1267: (pc)))] ! 1268: "" ! 1269: "* return cmp_jmp(\"\", 4, operands[0]); ") ! 1270: ! 1271: (define_insn "bgeu" ! 1272: [(set (pc) ! 1273: (if_then_else (geu (cc0) ! 1274: (const_int 0)) ! 1275: (label_ref (match_operand 0 "" "")) ! 1276: (pc)))] ! 1277: "" ! 1278: "* return cmp_jmp(\"u\", 4, operands[0]); ") ! 1279: ! 1280: (define_insn "ble" ! 1281: [(set (pc) ! 1282: (if_then_else (le (cc0) ! 1283: (const_int 0)) ! 1284: (label_ref (match_operand 0 "" "")) ! 1285: (pc)))] ! 1286: "" ! 1287: "* return cmp_jmp(\"\", 10, operands[0]); ") ! 1288: ! 1289: (define_insn "bleu" ! 1290: [(set (pc) ! 1291: (if_then_else (leu (cc0) ! 1292: (const_int 0)) ! 1293: (label_ref (match_operand 0 "" "")) ! 1294: (pc)))] ! 1295: "" ! 1296: "* return cmp_jmp(\"u\", 10, operands[0]); ") ! 1297: ! 1298: (define_insn "" ! 1299: [(set (pc) ! 1300: (if_then_else (eq (cc0) ! 1301: (const_int 0)) ! 1302: (pc) ! 1303: (label_ref (match_operand 0 "" ""))))] ! 1304: "" ! 1305: "* return cmp_jmp(\"\", 8, operands[0]); ") ! 1306: ! 1307: (define_insn "" ! 1308: [(set (pc) ! 1309: (if_then_else (ne (cc0) ! 1310: (const_int 0)) ! 1311: (pc) ! 1312: (label_ref (match_operand 0 "" ""))))] ! 1313: "" ! 1314: "* return cmp_jmp(\"\", 2, operands[0]); ") ! 1315: ! 1316: (define_insn "" ! 1317: [(set (pc) ! 1318: (if_then_else (gt (cc0) ! 1319: (const_int 0)) ! 1320: (pc) ! 1321: (label_ref (match_operand 0 "" ""))))] ! 1322: "" ! 1323: "* return cmp_jmp(\"\", 10, operands[0]); ") ! 1324: ! 1325: (define_insn "" ! 1326: [(set (pc) ! 1327: (if_then_else (gtu (cc0) ! 1328: (const_int 0)) ! 1329: (pc) ! 1330: (label_ref (match_operand 0 "" ""))))] ! 1331: "" ! 1332: "* return cmp_jmp(\"u\", 10, operands[0]); ") ! 1333: ! 1334: (define_insn "" ! 1335: [(set (pc) ! 1336: (if_then_else (lt (cc0) ! 1337: (const_int 0)) ! 1338: (pc) ! 1339: (label_ref (match_operand 0 "" ""))))] ! 1340: "" ! 1341: "* return cmp_jmp(\"\", 4, operands[0]); ") ! 1342: ! 1343: (define_insn "" ! 1344: [(set (pc) ! 1345: (if_then_else (ltu (cc0) ! 1346: (const_int 0)) ! 1347: (pc) ! 1348: (label_ref (match_operand 0 "" ""))))] ! 1349: "" ! 1350: "* return cmp_jmp(\"u\", 4, operands[0]); ") ! 1351: ! 1352: (define_insn "" ! 1353: [(set (pc) ! 1354: (if_then_else (ge (cc0) ! 1355: (const_int 0)) ! 1356: (pc) ! 1357: (label_ref (match_operand 0 "" ""))))] ! 1358: "" ! 1359: "* return cmp_jmp(\"\", 6, operands[0]); ") ! 1360: ! 1361: (define_insn "" ! 1362: [(set (pc) ! 1363: (if_then_else (geu (cc0) ! 1364: (const_int 0)) ! 1365: (pc) ! 1366: (label_ref (match_operand 0 "" ""))))] ! 1367: "" ! 1368: "* return cmp_jmp(\"u\", 6, operands[0]); ") ! 1369: ! 1370: (define_insn "" ! 1371: [(set (pc) ! 1372: (if_then_else (le (cc0) ! 1373: (const_int 0)) ! 1374: (pc) ! 1375: (label_ref (match_operand 0 "" ""))))] ! 1376: "" ! 1377: "* return cmp_jmp(\"\", 0, operands[0]); ") ! 1378: ! 1379: (define_insn "" ! 1380: [(set (pc) ! 1381: (if_then_else (leu (cc0) ! 1382: (const_int 0)) ! 1383: (pc) ! 1384: (label_ref (match_operand 0 "" ""))))] ! 1385: "" ! 1386: "* return cmp_jmp(\"u\", 0, operands[0]); ") ! 1387: ! 1388: ;; Note that operand 1 is total size of args, in bytes, ! 1389: ;; and what the call insn wants is the number of words. ! 1390: (define_insn "call" ! 1391: [(call (match_operand:QI 0 "general_operand" "m") ! 1392: (match_operand:QI 1 "general_operand" "g"))] ! 1393: "" ! 1394: "* ! 1395: if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == REG) ! 1396: if (REGNO (XEXP (operands[0], 0)) != 0) ! 1397: return \"add.64\\t.sp,=-4\;ld.64\\t.r0,=.+11\;st.32\\t.r0,[.sp]\;br.reg\\t%r0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\"; ! 1398: else ! 1399: return \"add.64\\t.sp,=-4\;ld.64\\t.r1,=.+11\;st.32\\t.r1,[.sp]\;br.reg\\t%r0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\"; ! 1400: else ! 1401: return \"add.64\\t.sp,=-4\;call\\t%0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\"; ! 1402: ") ! 1403: ! 1404: (define_insn "call_value" ! 1405: [(set (match_operand 0 "" "g") ! 1406: (call (match_operand:QI 1 "general_operand" "m") ! 1407: (match_operand:QI 2 "general_operand" "g")))] ! 1408: "" ! 1409: "* ! 1410: if (GET_CODE (operands[1]) == MEM && GET_CODE (XEXP (operands[1], 0)) == REG) ! 1411: if (REGNO (XEXP (operands[1], 0)) != 0) ! 1412: return \"add.64\\t.sp,=-4\;ld.64\\t.r0,=.+11\;st.32\\t.r0,[.sp]\;br.reg\\t%r1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\"; ! 1413: else ! 1414: return \"add.64\\t.sp,=-4\;ld.64\\t.r1,=.+11\;st.32\\t.r1,[.sp]\;br.reg\\t%r1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\"; ! 1415: else ! 1416: return \"add.64\\t.sp,=-4\;call\\t%1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\"; ! 1417: ") ! 1418: ! 1419: (define_insn "tablejump" ! 1420: [(set (pc) (match_operand:SI 0 "register_operand" "r")) ! 1421: (use (label_ref (match_operand 1 "" "")))] ! 1422: "" ! 1423: "br.reg\\t%0") ! 1424: ! 1425: (define_insn "nop" ! 1426: [(const_int 0)] ! 1427: "" ! 1428: "nop")
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