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1.1 root 1: ;;- Machine description for GNU compiler
2: ;;- Fujitsu Gmicro Version
3: ;;- Ported by M.Yuhara, Fujitsu Laboratories LTD.
4: ;;
5: ;; Copyright (C) 1990 Free Software Foundation, Inc.
6:
7: ;; This file is part of GNU CC.
8:
9: ;; GNU CC is free software; you can redistribute it and/or modify
10: ;; it under the terms of the GNU General Public License as published by
11: ;; the Free Software Foundation; either version 2, or (at your option)
12: ;; any later version.
13:
14: ;; GNU CC is distributed in the hope that it will be useful,
15: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17: ;; GNU General Public License for more details.
18: ;; Among other things, the copyright
19: ;; notice and this notice must be preserved on all copies.
20:
21:
22: ;; You should have received a copy of the GNU General Public License
23: ;; along with GNU CC; see the file COPYING. If not, write to
24: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25:
26:
27: ;;- instruction definitions
28:
29: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
30:
31: ;;- When naming insn's (operand 0 of define_insn) be careful about using
32: ;;- names from other targets machine descriptions.
33:
34: ;;- cpp macro #define NOTICE_UPDATE_CC is essentially a no-op for the
35: ;;- gmicro; no compares are eliminated.
36:
37: ;;- The original structure of this file is m68k.md.
38:
39: ;; ??? Work to be done:
40: ;; Add patterns for ACB and SCB instructions.
41: ;; Add define_insn patterns to recognize the insns that extend a byte
42: ;; to a word and add it into a word, etc.
43:
44: ;;- Some of these insn's are composites of several Gmicro op codes.
45: ;;- The assembler (or final @@??) insures that the appropriate one is
46: ;;- selected.
47:
48: (define_insn ""
49: [(set (match_operand:DF 0 "push_operand" "=m")
50: (match_operand:DF 1 "general_operand" "rmfF"))]
51: ""
52: "*
53: {
54: if (FPU_REG_P (operands[1]))
55: return \"fmov.d %f1,%0\";
56: return output_move_double (operands);
57: }")
58:
59: (define_insn ""
60: [(set (match_operand:DI 0 "push_operand" "=m")
61: (match_operand:DF 1 "general_operand" "rmF"))]
62: ""
63: "*
64: {
65: return output_move_double (operands);
66: }")
67:
68: ;; We don't want to allow a constant operand for test insns because
69: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
70: ;; be folded while optimizing anyway.
71:
72: (define_insn "tstsi"
73: [(set (cc0)
74: (match_operand:SI 0 "nonimmediate_operand" "rm"))]
75: ""
76: "cmp:z.w #0,%0")
77:
78: (define_insn "tsthi"
79: [(set (cc0)
80: (match_operand:HI 0 "nonimmediate_operand" "rm"))]
81: ""
82: "cmp:z.h #0,%0")
83:
84: (define_insn "tstqi"
85: [(set (cc0)
86: (match_operand:QI 0 "nonimmediate_operand" "rm"))]
87: ""
88: "cmp:z.b #0,%0")
89:
90:
91: (define_insn "tstsf"
92: [(set (cc0)
93: (match_operand:SF 0 "general_operand" "fmF"))]
94: "TARGET_FPU"
95: "*
96: {
97: cc_status.flags = CC_IN_FPU;
98: return \"ftst.s %0\";
99: }")
100:
101:
102: (define_insn "tstdf"
103: [(set (cc0)
104: (match_operand:DF 0 "general_operand" "fmF"))]
105: "TARGET_FPU"
106: "*
107: {
108: cc_status.flags = CC_IN_FPU;
109: return \"ftst.d %0\";
110: }")
111:
112: ;; compare instructions.
113:
114: ;; (operand0 - operand1)
115: (define_insn "cmpsi"
116: [(set (cc0)
117: (compare (match_operand:SI 0 "nonimmediate_operand" "ri,rm")
118: (match_operand:SI 1 "general_operand" "rm,rmi")))]
119: ""
120: "*
121: {
122: int signed_flag = my_signed_comp (insn);
123:
124: if (which_alternative == 0)
125: {
126: cc_status.flags |= CC_REVERSED;
127: if (signed_flag && GET_CODE (operands[0]) == CONST_INT)
128: {
129: register rtx xfoo;
130: xfoo = operands[1];
131: operands[0] = operands[1];
132: operands[1] = xfoo;
133: return cmp_imm_word (INTVAL (operands[1]), operands[0]);
134: }
135: if (signed_flag)
136: return \"cmp.w %0,%1\";
137: return \"cmpu.w %0,%1\";
138: }
139: if (signed_flag)
140: {
141: if (GET_CODE (operands[1]) == CONST_INT)
142: return cmp_imm_word (INTVAL (operands[1]), operands[0]);
143: return \"cmp.w %1,%0\";
144: }
145: else
146: return \"cmpu.w %1,%0\";
147: }")
148:
149: (define_insn "cmphi"
150: [(set (cc0)
151: (compare (match_operand:HI 0 "nonimmediate_operand" "ri,rm")
152: (match_operand:HI 1 "general_operand" "rm,rmi")))]
153: ""
154: "*
155: {
156: int signed_flag = my_signed_comp (insn);
157:
158: if (which_alternative == 0)
159: {
160: cc_status.flags |= CC_REVERSED;
161: if (signed_flag)
162: return \"cmp.h %0,%1\";
163: return \"cmpu.h %0,%1\";
164: }
165: if (signed_flag)
166: return \"cmp.h %1,%0\";
167: return \"cmpu.h %1,%0\";
168: }")
169:
170: (define_insn "cmpqi"
171: [(set (cc0)
172: (compare (match_operand:QI 0 "nonimmediate_operand" "ri,rm")
173: (match_operand:QI 1 "general_operand" "rm,rmi")))]
174: ""
175: "*
176: {
177: int signed_flag = my_signed_comp (insn);
178:
179: if (which_alternative == 0)
180: {
181: cc_status.flags |= CC_REVERSED;
182: if (signed_flag)
183: return \"cmp.b %0,%1\";
184: return \"cmpu.b %0,%1\";
185: }
186: if (signed_flag)
187: return \"cmp.b %1,%0\";
188: return \"cmpu.b %1,%0\";
189: }")
190:
191:
192: (define_insn "cmpdf"
193: [(set (cc0)
194: (compare (match_operand:DF 0 "general_operand" "f,mG")
195: (match_operand:DF 1 "general_operand" "fmG,f")))]
196: "TARGET_FPU"
197: "*
198: {
199: cc_status.flags = CC_IN_FPU;
200:
201: if (FPU_REG_P (operands[0]))
202: return \"fcmp.d %f1,%f0\";
203: cc_status.flags |= CC_REVERSED;
204: return \"fcmp.d %f0,%f1\";
205: }")
206:
207:
208: (define_insn "cmpsf"
209: [(set (cc0)
210: (compare (match_operand:SF 0 "general_operand" "f,mG")
211: (match_operand:SF 1 "general_operand" "fmG,f")))]
212: "TARGET_FPU"
213: "*
214: {
215: cc_status.flags = CC_IN_FPU;
216: if (FPU_REG_P (operands[0]))
217: return \"fcmp.s %f1,%0\";
218: cc_status.flags |= CC_REVERSED;
219: return \"fcmp.s %f0,%1\";
220: }")
221:
222: ;; Recognizers for btst instructions.
223:
224: (define_insn ""
225: [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "rm")
226: (const_int 1)
227: (match_operand:SI 1 "general_operand" "rmi")))]
228: ""
229: "btst %1.w,%0.b")
230:
231: (define_insn ""
232: [(set (cc0) (zero_extract (match_operand:HI 0 "nonimmediate_operand" "rm")
233: (const_int 1)
234: (match_operand:SI 1 "general_operand" "rmi")))]
235: ""
236: "btst %1.w,%0.h")
237:
238: (define_insn ""
239: [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "rm")
240: (const_int 1)
241: (match_operand:SI 1 "general_operand" "rmi")))]
242: ""
243: "btst %1.w,%0.w")
244:
245: ;; The following two patterns are like the previous two
246: ;; except that they use the fact that bit-number operands (offset)
247: ;; are automatically masked to 3 or 5 bits when the base is a register.
248:
249: (define_insn ""
250: [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "r")
251: (const_int 1)
252: (and:SI
253: (match_operand:SI 1 "general_operand" "rmi")
254: (const_int 7))))]
255: ""
256: "btst %1.w,%0.b")
257:
258: (define_insn ""
259: [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "r")
260: (const_int 1)
261: (and:SI
262: (match_operand:SI 1 "general_operand" "rmi")
263: (const_int 31))))]
264: ""
265: "btst %1.w,%0.w")
266:
267: ; More various size-patterns are allowed for btst, but not
268: ; included yet. M.Yuhara
269:
270:
271: (define_insn ""
272: [(set (cc0) (and:SI (sign_extend:SI (sign_extend:HI (match_operand:QI 0 "nonimmediate_operand" "rm")))
273: (match_operand:SI 1 "general_operand" "i")))]
274: "(GET_CODE (operands[1]) == CONST_INT
275: && (unsigned) INTVAL (operands[1]) < 0x100
276: && exact_log2 (INTVAL (operands[1])) >= 0)"
277: "*
278: {
279: register int log = exact_log2 (INTVAL (operands[1]));
280: operands[1] = gen_rtx (CONST_INT, VOIDmode, log);
281: return \"btst %1,%0.b\";
282: }")
283:
284: ; I can add more patterns like above. But not yet. M.Yuhara
285:
286:
287: ; mtst is supported only by G/300.
288:
289: (define_insn ""
290: [(set (cc0)
291: (and:SI (match_operand:SI 0 "general_operand" "%rmi")
292: (match_operand:SI 1 "general_operand" "rm")))]
293: "TARGET_G300"
294: "*
295: {
296: if (GET_CODE (operands[0]) == CONST_INT)
297: return \"mtst.w %0,%1\";
298: return \"mtst.w %1,%0\";
299: }")
300:
301: (define_insn ""
302: [(set (cc0)
303: (and:HI (match_operand:HI 0 "general_operand" "%rmi")
304: (match_operand:HI 1 "general_operand" "rm")))]
305: "TARGET_G300"
306: "*
307: {
308: if (GET_CODE (operands[0]) == CONST_INT)
309: return \"mtst.h %0,%1\";
310: return \"mtst.h %1,%0\";
311: }")
312:
313: (define_insn ""
314: [(set (cc0)
315: (and:QI (match_operand:QI 0 "general_operand" "%rmi")
316: (match_operand:QI 1 "general_operand" "rm")))]
317: "TARGET_G300"
318: "*
319: {
320: if (GET_CODE (operands[0]) == CONST_INT)
321: return \"mtst.b %0,%1\";
322: return \"mtst.b %1,%0\";
323: }")
324:
325:
326:
327: ;; move instructions
328:
329: /* added by M.Yuhara */
330: ;; 1.35.04 89.08.28 modification start
331: ;; register_operand -> general_operand
332: ;; ashift -> mult
333:
334: (define_insn ""
335: [(set (mem:SI (plus:SI
336: (match_operand:SI 0 "general_operand" "r")
337: (ashift:SI
338: (match_operand:SI 1 "general_operand" "r")
339: (const_int 2))))
340: (match_operand:SI 2 "general_operand" "rmi"))]
341: ""
342: "*
343: {
344: return \"mov.w %2,@(%0:b,%1*4)\";
345: }")
346:
347: (define_insn ""
348: [(set (mem:SI (plus:SI
349: (ashift:SI
350: (match_operand:SI 0 "general_operand" "r")
351: (const_int 2))
352: (match_operand:SI 1 "general_operand" "r")))
353: (match_operand:SI 2 "general_operand" "rmi"))]
354: ""
355: "*
356: {
357: return \"mov.w %2,@(%1:b,%0*4)\";
358: }")
359:
360:
361: (define_insn ""
362: [(set (mem:SI (plus:SI
363: (match_operand:SI 0 "register_operand" "r")
364: (mult:SI
365: (match_operand:SI 1 "register_operand" "r")
366: (const_int 4))))
367: (match_operand:SI 2 "general_operand" "rmi"))]
368: ""
369: "*
370: {
371: return \"mov.w %2,@(%0:b,%1*4)\";
372: }")
373:
374: (define_insn ""
375: [(set (mem:SI (plus:SI
376: (mult:SI
377: (match_operand:SI 0 "register_operand" "r")
378: (const_int 4))
379: (match_operand:SI 1 "register_operand" "r")))
380: (match_operand:SI 2 "general_operand" "rmi"))]
381: ""
382: "*
383: {
384: return \"mov.w %2,@(%1:b,%0*4)\";
385: }")
386:
387:
388: (define_insn ""
389: [(set (mem:SI (plus:SI
390: (match_operand:SI 0 "general_operand" "r")
391: (plus:SI
392: (match_operand:SI 1 "register_operand" "r")
393: (match_operand:SI 2 "register_operand" "i"))))
394: (match_operand:SI 3 "general_operand" "rmi"))]
395: ""
396: "*
397: {
398: return \"mov.w %3,@(%c2,%0,%1)\";
399: }")
400:
401: (define_insn ""
402: [(set (mem:SI (plus:SI
403: (plus:SI
404: (match_operand:SI 0 "register_operand" "r")
405: (match_operand:SI 1 "register_operand" "r"))
406: (match_operand:SI 2 "general_operand" "i")))
407: (match_operand:SI 3 "general_operand" "rmi"))]
408: ""
409: "*
410: {
411: return \"mov.w %3,@(%c2,%0,%1)\";
412: }")
413:
414:
415: (define_insn ""
416: [(set (mem:SI (plus:SI
417: (match_operand:SI 0 "general_operand" "i")
418: (plus:SI
419: (match_operand:SI 1 "register_operand" "r")
420: (mult:SI
421: (match_operand:SI 2 "register_operand" "r")
422: (const_int 4)))))
423: (match_operand:SI 3 "general_operand" "rmi"))]
424: ""
425: "*
426: {
427: return \"mov.w %3,@(%1:b,%0,%2*4)\";
428: }")
429:
430: ;; 89.08.28 1.35.04 modification end
431:
432: ;; Should add "!" to op2 ??
433:
434: ;; General move-address-to-operand should handle these.
435: ;; If that does not work, please figure out why.
436:
437: ;(define_insn ""
438: ; [(set (match_operand:SI 0 "push_operand" "=m")
439: ; (plus:SI
440: ; (match_operand:SI 1 "immediate_operand" "i")
441: ; (match_operand:SI 2 "general_operand" "r")))]
442: ; ""
443: ; "mova.w @(%c1,%2),%-")
444:
445: ;(define_insn ""
446: ; [(set (match_operand:SI 0 "push_operand" "=m")
447: ; (plus:SI
448: ; (match_operand:SI 1 "general_operand" "r")
449: ; (match_operand:SI 2 "immediate_operand" "i")))]
450: ; ""
451: ; "mova.w @(%c2,%1),%-")
452:
453:
454: (define_insn ""
455: [(set (match_operand:SI 0 "push_operand" "=m")
456: (minus:SI
457: (match_operand:SI 1 "general_operand" "r")
458: (match_operand:SI 2 "immediate_operand" "i")))]
459: ""
460: "mova.w @(%n2,%1),%-")
461:
462:
463:
464: ;; General case of fullword move.
465:
466: (define_insn "movsi"
467: [(set (match_operand:SI 0 "general_operand" "=rm")
468: (match_operand:SI 1 "general_operand" "rmi"))]
469: ""
470: "*
471: {
472: if (GET_CODE (operands[1]) == CONST_INT)
473: return mov_imm_word (INTVAL (operands[1]), operands[0]);
474: /* if (address_operand (operands[1], SImode))
475: return \"mova.w %1,%0\"; */
476: if (push_operand (operands[0], SImode))
477: return \"mov.w %1,%-\";
478: return \"mov.w %1,%0\";
479: }")
480:
481: /* pushsi 89.08.10 for test M.Yuhara */
482: /*
483: (define_insn ""
484: [(set (match_operand:SI 0 "push_operand" "=m")
485: (match_operand:SI 1 "general_operand" "rmi"))]
486: ""
487: "*
488: {
489: if (GET_CODE (operands[1]) == CONST_INT)
490: return mov_imm_word (INTVAL (operands[1]), operands[0]);
491: if (push_operand (operands[0], SImode))
492: return \"mov.w %1,%-\";
493: return \"mov.w %1,%0\";
494: }")
495: */
496:
497:
498: (define_insn "movhi"
499: [(set (match_operand:HI 0 "general_operand" "=rm")
500: (match_operand:HI 1 "general_operand" "rmi"))]
501: ""
502: "*
503: {
504: if (push_operand (operands[0], SImode))
505: return \"mov.h %1,%-\";
506: return \"mov.h %1,%0\";
507: }")
508:
509: ;; Is the operand constraint "+" necessary ????
510: ;; Should I check push_operand ????
511:
512: (define_insn "movstricthi"
513: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm"))
514: (match_operand:HI 1 "general_operand" "rmi"))]
515: ""
516: "mov.h %1,%0");
517:
518: (define_insn "movqi"
519: [(set (match_operand:QI 0 "general_operand" "=rm")
520: (match_operand:QI 1 "general_operand" "rmi"))]
521: ""
522: "*
523: {
524: if (GREG_P (operands[0]))
525: {
526: if (CONSTANT_P (operands[1]))
527: return \"mov:l %1,%0.w\";
528: else
529: return \"mov:l %1.b,%0.w\";
530: }
531: if (GREG_P (operands[1]))
532: return \"mov:s %1.w,%0.b\";
533: return \"mov.b %1,%0\";
534: }")
535:
536: (define_insn "movstrictqi"
537: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm"))
538: (match_operand:QI 1 "general_operand" "rmi"))]
539: ""
540: "mov.b %1,%0")
541:
542:
543: (define_insn "movsf"
544: [(set (match_operand:SF 0 "general_operand" "=f,mf,rm,fr")
545: (match_operand:SF 1 "general_operand" "mfF,f,rmF,fr"))]
546: ""
547: "*
548: {
549: switch (which_alternative)
550: {
551: case 0:
552: if (GET_CODE (operands[1]) == CONST_DOUBLE)
553: return output_move_const_single (operands);
554: return \"fmov.s %1,%0\";
555: case 1:
556: return \"fmov.s %1,%0\";
557: case 2:
558: if (GET_CODE (operands[1]) == CONST_DOUBLE)
559: return output_move_const_single (operands);
560: return \"mov.w %1,%0\";
561: case 3:
562: if (FPU_REG_P (operands[0]))
563: return \"mov.w %1,%-\\n\\tfmov.s %+,%0\";
564: return \"fmov.s %1,%-\\n\\tmov.w %+,%0\";
565: }
566: }")
567:
568: (define_insn "movdf"
569: [(set (match_operand:DF 0 "general_operand" "=f,mf,rm,fr")
570: (match_operand:DF 1 "general_operand" "mfF,f,rmF,fr"))]
571: ""
572: "*
573: {
574: switch (which_alternative)
575: {
576: case 0:
577: if (GET_CODE (operands[1]) == CONST_DOUBLE)
578: return output_move_const_double (operands);
579: return \"fmov.d %1,%0\";
580: case 1:
581: return \"fmov.d %1,%0\";
582: case 2:
583: if (GET_CODE (operands[1]) == CONST_DOUBLE)
584: return output_move_const_double (operands);
585: return output_move_double (operands);
586: case 3:
587: if (FPU_REG_P (operands[0]))
588: {
589: rtx xoperands[2];
590: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
591: output_asm_insn (\"mov.w %1,%-\", xoperands);
592: output_asm_insn (\"mov.w %1,%-\", operands);
593: return \"fmov.d %+,%0\";
594: }
595: else
596: {
597: output_asm_insn (\"fmov.d %f1,%-\", operands);
598: output_asm_insn (\"mov.w %+,%0\", operands);
599: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
600: return \"mov.w %+,%0\";
601: }
602: }
603: }")
604:
605:
606: ;; movdi can apply to fp regs in some cases
607: ;; Must check again. you can use fsti/fldi, etc.
608: ;; FPU reg should be included ??
609: ;; 89.12.13 for test
610:
611: (define_insn "movdi"
612: ;; Let's see if it really still needs to handle fp regs, and, if so, why.
613: [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro")
614: (match_operand:DI 1 "general_operand" "rF,m,roiF"))]
615: ""
616: "*
617: {
618: if (FPU_REG_P (operands[0]))
619: {
620: if (FPU_REG_P (operands[1]))
621: return \"fmov.d %1,%0\";
622: if (REG_P (operands[1]))
623: {
624: rtx xoperands[2];
625: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
626: output_asm_insn (\"mov.w %1,%-\", xoperands);
627: output_asm_insn (\"mov.w %1,%-\", operands);
628: return \"fmov.d %+,%0\";
629: }
630: if (GET_CODE (operands[1]) == CONST_DOUBLE)
631: return output_move_const_double (operands);
632: return \"fmov.d %f1,%0\";
633: }
634: else if (FPU_REG_P (operands[1]))
635: {
636: if (REG_P (operands[0]))
637: {
638: output_asm_insn (\"fmov.d %f1,%-\;mov.w %+,%0\", operands);
639: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
640: return \"mov.w %+,%0\";
641: }
642: else
643: return \"fmov.d %f1,%0\";
644: }
645: return output_move_double (operands);
646: }
647: ")
648:
649:
650: ;; The definition of this insn does not really explain what it does,
651: ;; but it should suffice
652: ;; that anything generated as this insn will be recognized as one
653: ;; and that it won't successfully combine with anything.
654:
655: ;; This is dangerous when %0 and %1 overlapped !!!!!
656: ;; Ugly code...
657:
658: (define_insn "movstrhi"
659: [(set (match_operand:BLK 0 "general_operand" "=m")
660: (match_operand:BLK 1 "general_operand" "m"))
661: (use (match_operand:HI 2 "general_operand" "rmi"))
662: (clobber (reg:SI 0))
663: (clobber (reg:SI 1))
664: (clobber (reg:SI 2))]
665: ""
666: "*
667: {
668: int op2const;
669: rtx tmpx;
670:
671: if (CONSTANT_P (operands[1]))
672: {
673: fprintf (stderr, \"smov 1 const err \");
674: abort ();
675: }
676: else if (GET_CODE (operands[1]) == REG)
677: {
678: fprintf (stderr, \"smov 1 reg err \");
679: abort ();
680: }
681: else if (GET_CODE (operands[1]) == MEM)
682: {
683: tmpx = XEXP (operands[1], 0);
684: if (CONSTANT_ADDRESS_P (tmpx) || GREG_P (tmpx))
685: {
686: operands[1] = tmpx;
687: output_asm_insn (\"mov.w %1,r0\", operands);
688: }
689: else
690: {
691: output_asm_insn (\"mova %1,r0\", operands);
692: }
693: }
694: else
695: {
696: fprintf (stderr, \"smov 1 else err \");
697: abort ();
698: output_asm_insn (\"mova.w %p1,r0\", operands);
699: }
700:
701: if (CONSTANT_P (operands[0]))
702: {
703: fprintf (stderr, \"smov 0 const err \");
704: abort ();
705: }
706: else if (GET_CODE (operands[0]) == REG)
707: {
708: fprintf (stderr, \"smov 0 reg err \");
709: abort ();
710: }
711: else if (GET_CODE (operands[0]) == MEM)
712: {
713: tmpx = XEXP (operands[0], 0);
714: if (CONSTANT_ADDRESS_P (tmpx) || GREG_P (tmpx))
715: {
716: operands[0] = tmpx;
717: output_asm_insn (\"mov.w %0,r1\", operands);
718: }
719: else
720: {
721: output_asm_insn (\"mova %0,r1\", operands);
722: }
723: }
724: else
725: {
726: fprintf (stderr, \"smov 0 else err \");
727: abort ();
728: }
729:
730: if (GET_CODE (operands[2]) == CONST_INT)
731: {
732: op2const = INTVAL (operands[2]);
733: if (op2const % 4 != 0)
734: {
735: output_asm_insn (\"mov.w %2,r2\", operands);
736: return \"smov/n/f.b\";
737: }
738: op2const = op2const / 4;
739: if (op2const <= 4)
740: {
741: if (op2const == 0)
742: abort (0);
743: if (op2const == 1)
744: return \"mov.w @r0,@r1\";
745: output_asm_insn (\"mov.w @r0,@r1\", operands);
746: if (op2const == 2)
747: return \"mov.w @(4,r0),@(4,r1)\";
748: output_asm_insn (\"mov.w @(4,r0),@(4,r1)\", operands);
749: if (op2const == 3)
750: return \"mov.w @(8,r0),@(8,r1)\";
751: output_asm_insn (\"mov.w @(8,r0),@(8,r1)\", operands);
752: return \"mov.w @(12,r0),@(12,r1)\";
753: }
754:
755: operands[2] =
756: gen_rtx (CONST_INT, VOIDmode, op2const);
757: output_asm_insn (\"mov.w %2,r2\", operands);
758: return \"smov/n/f.w\";
759: }
760: else
761: {
762: fprintf (stderr, \"smov 0 else err \");
763: abort ();
764: output_asm_insn (\"mov %2.h,r2.w\", operands);
765: return \"smov/n/f.b\";
766: }
767:
768: }")
769:
770: ;; M.Yuhara 89.08.24
771: ;; experiment on the built-in strcpy (__builtin_smov)
772: ;;
773: ;; len = 0 means unknown string length.
774: ;;
775: ;; mem:SI is dummy. Necessary so as not to be deleted by optimization.
776: ;; Use of BLKmode would be better...
777: ;;
778: ;;
779: (define_insn "smovsi"
780: [(set (mem:SI (match_operand:SI 0 "general_operand" "=rm"))
781: (mem:SI (match_operand:SI 1 "general_operand" "rm")))
782: (use (match_operand:SI 2 "general_operand" "i"))
783: (clobber (reg:SI 0))
784: (clobber (reg:SI 1))
785: (clobber (reg:SI 2))
786: (clobber (reg:SI 3))]
787: ""
788: "*
789: {
790: int len, wlen, blen, offset;
791: char tmpstr[128];
792: rtx xoperands[1];
793:
794: len = INTVAL (operands[2]);
795: output_asm_insn (\"mov.w %1,r0\\t; begin built-in strcpy\", operands);
796: output_asm_insn (\"mov.w %0,r1\", operands);
797:
798: if (len == 0)
799: {
800: output_asm_insn (\"mov:z.w #0,r2\", operands);
801: output_asm_insn (\"mov:z.w #0,r3\", operands);
802: return \"smov/eq/f.b\\t; end built-in strcpy\";
803: }
804:
805: wlen = len / 4;
806: blen = len - wlen * 4;
807:
808: if (wlen > 0)
809: {
810: if (len <= 40 && !TARGET_FORCE_SMOV)
811: {
812: output_asm_insn (\"mov.w @r0,@r1\", operands);
813: offset = 4;
814: while ( (blen = len - offset) > 0)
815: {
816: if (blen >= 4)
817: {
818: sprintf (tmpstr, \"mov.w @(%d,r0),@(%d,r1)\",
819: offset, offset);
820: output_asm_insn (tmpstr, operands);
821: offset += 4;
822: }
823: else if (blen >= 2)
824: {
825: sprintf (tmpstr, \"mov.h @(%d,r0),@(%d,r1)\",
826: offset, offset);
827: output_asm_insn (tmpstr, operands);
828: offset += 2;
829: }
830: else
831: {
832: sprintf (tmpstr, \"mov.b @(%d,r0),@(%d,r1)\",
833: offset, offset);
834: output_asm_insn (tmpstr, operands);
835: offset++;
836: }
837: }
838: return \"\\t\\t; end built-in strcpy\";
839: }
840: else
841: {
842: xoperands[0] = gen_rtx (CONST_INT, VOIDmode, wlen);
843: output_asm_insn (\"mov.w %0,r2\", xoperands);
844: output_asm_insn (\"smov/n/f.w\", operands);
845: }
846: }
847:
848: if (blen >= 2)
849: {
850: output_asm_insn (\"mov.h @r0,@r1\", operands);
851: if (blen == 3)
852: output_asm_insn (\"mov.b @(2,r0),@(2,r1)\", operands);
853: }
854: else if (blen == 1)
855: {
856: output_asm_insn (\"mov.b @r0,@r1\", operands);
857: }
858:
859: return \"\\t\\t; end built-in strcpy\";
860: }")
861:
862: ;; truncation instructions
863: (define_insn "truncsiqi2"
864: [(set (match_operand:QI 0 "general_operand" "=rm")
865: (truncate:QI
866: (match_operand:SI 1 "general_operand" "rmi")))]
867: ""
868: "mov %1.w,%0.b")
869: ; "*
870: ;{
871: ; if (GET_CODE (operands[0]) == REG)
872: ; return \"mov.w %1,%0\";
873: ; if (GET_CODE (operands[1]) == MEM)
874: ; operands[1] = adj_offsettable_operand (operands[1], 3);
875: ; return \"mov.b %1,%0\";
876: ;}")
877:
878: (define_insn "trunchiqi2"
879: [(set (match_operand:QI 0 "general_operand" "=rm")
880: (truncate:QI
881: (match_operand:HI 1 "general_operand" "rmi")))]
882: ""
883: "mov %1.h,%0.b")
884: ; "*
885: ;{
886: ; if (GET_CODE (operands[0]) == REG)
887: ; return \"mov.h %1,%0\";
888: ; if (GET_CODE (operands[1]) == MEM)
889: ; operands[1] = adj_offsettable_operand (operands[1], 1);
890: ; return \"mov.b %1,%0\";
891: ;}")
892:
893: (define_insn "truncsihi2"
894: [(set (match_operand:HI 0 "general_operand" "=rm")
895: (truncate:HI
896: (match_operand:SI 1 "general_operand" "rmi")))]
897: ""
898: "mov %1.w,%0.h")
899: ; "*
900: ;{
901: ; if (GET_CODE (operands[0]) == REG)
902: ; return \"mov.w %1,%0\";
903: ; if (GET_CODE (operands[1]) == MEM)
904: ; operands[1] = adj_offsettable_operand (operands[1], 2);
905: ; return \"mov.h %1,%0\";
906: ;}")
907:
908: ;; zero extension instructions
909: ;; define_expand (68k) -> define_insn (Gmicro)
910:
911: (define_insn "zero_extendhisi2"
912: [(set (match_operand:SI 0 "general_operand" "=rm")
913: (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
914: ""
915: "movu %1.h,%0.w")
916:
917:
918: (define_insn "zero_extendqihi2"
919: [(set (match_operand:HI 0 "general_operand" "=rm")
920: (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
921: ""
922: "movu %1.b,%0.h")
923:
924: (define_insn "zero_extendqisi2"
925: [(set (match_operand:SI 0 "general_operand" "=rm")
926: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
927: ""
928: "movu %1.b,%0.w")
929:
930:
931: ;; sign extension instructions
932:
933: (define_insn "extendhisi2"
934: [(set (match_operand:SI 0 "general_operand" "=rm")
935: (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
936: ""
937: "mov %1.h,%0.w")
938:
939:
940: (define_insn "extendqihi2"
941: [(set (match_operand:HI 0 "general_operand" "=rm")
942: (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
943: ""
944: "mov %1.b,%0.h")
945:
946: (define_insn "extendqisi2"
947: [(set (match_operand:SI 0 "general_operand" "=rm")
948: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
949: ""
950: "mov %1.b,%0.w")
951:
952:
953:
954: ;; Conversions between float and double.
955:
956: (define_insn "extendsfdf2"
957: [(set (match_operand:DF 0 "general_operand" "=*frm,f")
958: (float_extend:DF
959: (match_operand:SF 1 "general_operand" "f,rmF")))]
960: "TARGET_FPU"
961: "*
962: {
963: if (FPU_REG_P (operands[0]))
964: {
965: if (GET_CODE (operands[1]) == CONST_DOUBLE)
966: return output_move_const_double (operands);
967: if (GREG_P (operands[1]))
968: {
969: output_asm_insn (\"mov.w %1,%-\", operands);
970: return \"fmov %+.s,%0.d\";
971: }
972: return \"fmov %1.s,%0.d\";
973: }
974: else
975: {
976: if (GREG_P (operands[0]))
977: {
978: output_asm_insn (\"fmov %1.s,%-.d\", operands);
979: output_asm_insn (\"mov.w %+,%0\", operands);
980: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
981: return \"mov.w %+,%0\";
982: }
983: return \"fmov %1.s,%0.d\";
984: }
985: }")
986:
987:
988: (define_insn "truncdfsf2"
989: [(set (match_operand:SF 0 "general_operand" "=rfm")
990: (float_truncate:SF
991: (match_operand:DF 1 "general_operand" "f")))]
992: "TARGET_FPU"
993: "*
994: {
995: if (GREG_P (operands[0]))
996: {
997: output_asm_insn (\"fmov %1.d,%-.s\", operands);
998: return \"mov.w %+,%0\";
999: }
1000: return \"fmov %1.d,%0.s\";
1001: }")
1002:
1003: ;; Conversion between fixed point and floating point.
1004: ;; Note that among the fix-to-float insns
1005: ;; the ones that start with SImode come first.
1006: ;; That is so that an operand that is a CONST_INT
1007: ;; (and therefore lacks a specific machine mode).
1008: ;; will be recognized as SImode (which is always valid)
1009: ;; rather than as QImode or HImode.
1010:
1011:
1012: (define_insn "floatsisf2"
1013: [(set (match_operand:SF 0 "general_operand" "=f")
1014: (float:SF (match_operand:SI 1 "general_operand" "rmi")))]
1015: "TARGET_FPU"
1016: "fldi %1.w,%0.s")
1017:
1018: (define_insn "floatsidf2"
1019: [(set (match_operand:DF 0 "general_operand" "=f")
1020: (float:DF (match_operand:SI 1 "general_operand" "rmi")))]
1021: "TARGET_FPU"
1022: "fldi %1.w,%0.d")
1023:
1024: (define_insn "floathisf2"
1025: [(set (match_operand:SF 0 "general_operand" "=f")
1026: (float:SF (match_operand:HI 1 "general_operand" "rmi")))]
1027: "TARGET_FPU"
1028: "fldi %1.h,%0.s")
1029:
1030: (define_insn "floathidf2"
1031: [(set (match_operand:DF 0 "general_operand" "=f")
1032: (float:DF (match_operand:HI 1 "general_operand" "rmi")))]
1033: "TARGET_FPU"
1034: "fldi %1.h,%0.d")
1035:
1036: (define_insn "floatqisf2"
1037: [(set (match_operand:SF 0 "general_operand" "=f")
1038: (float:SF (match_operand:QI 1 "general_operand" "rmi")))]
1039: "TARGET_FPU"
1040: "fldi %1.b,%0.s")
1041:
1042: (define_insn "floatqidf2"
1043: [(set (match_operand:DF 0 "general_operand" "=f")
1044: (float:DF (match_operand:QI 1 "general_operand" "rmi")))]
1045: "TARGET_FPU"
1046: "fldi %1.b,%0.d")
1047:
1048: ;;; Convert a float to a float whose value is an integer.
1049: ;;; This is the first stage of converting it to an integer type.
1050: ;
1051: ;(define_insn "ftruncdf2"
1052: ; [(set (match_operand:DF 0 "general_operand" "=f")
1053: ; (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1054: ; "TARGET_FPU"
1055: ; "*
1056: ;{
1057: ; return \"fintrz.d %f1,%0\";
1058: ;}")
1059: ;
1060: ;(define_insn "ftruncsf2"
1061: ; [(set (match_operand:SF 0 "general_operand" "=f")
1062: ; (fix:SF (match_operand:SF 1 "general_operand" "fFm")))]
1063: ; "TARGET_FPU"
1064: ; "*
1065: ;{
1066: ; return \"fintrz.s %f1,%0\";
1067: ;}")
1068:
1069: ;; Convert a float to an integer.
1070:
1071: (define_insn "fix_truncsfqi2"
1072: [(set (match_operand:QI 0 "general_operand" "=rm")
1073: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "f"))))]
1074: "TARGET_FPU"
1075: "fsti %1.s,%0.b")
1076:
1077: (define_insn "fix_truncsfhi2"
1078: [(set (match_operand:HI 0 "general_operand" "=rm")
1079: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "f"))))]
1080: "TARGET_FPU"
1081: "fsti %1.s,%0.h")
1082:
1083: (define_insn "fix_truncsfsi2"
1084: [(set (match_operand:SI 0 "general_operand" "=rm")
1085: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "f"))))]
1086: "TARGET_FPU"
1087: "fsti %1.s,%0.w")
1088:
1089: (define_insn "fix_truncdfqi2"
1090: [(set (match_operand:QI 0 "general_operand" "=rm")
1091: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "f"))))]
1092: "TARGET_FPU"
1093: "fsti %1.d,%0.b")
1094:
1095: (define_insn "fix_truncdfhi2"
1096: [(set (match_operand:HI 0 "general_operand" "=rm")
1097: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "f"))))]
1098: "TARGET_FPU"
1099: "fsti %1.d,%0.h")
1100:
1101: (define_insn "fix_truncdfsi2"
1102: [(set (match_operand:SI 0 "general_operand" "=rm")
1103: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "f"))))]
1104: "TARGET_FPU"
1105: "fsti %1.d,%0.w")
1106:
1107:
1108: ;;; Special add patterns
1109: ;;; 89.09.28
1110:
1111: ;; This should be redundant; please find out why regular addsi3
1112: ;; fails to match this case.
1113:
1114: ;(define_insn ""
1115: ; [(set (mem:SI (plus:SI
1116: ; (plus:SI (match_operand 0 "general_operand" "r")
1117: ; (match_operand 1 "general_operand" "r"))
1118: ; (match_operand 2 "general_operand" "i")))
1119: ; (plus:SI
1120: ; (mem:SI (plus:SI
1121: ; (plus:SI (match_dup 0)
1122: ; (match_dup 1))
1123: ; (match_dup 2)))
1124: ; (match_operand 3 "general_operand" "rmi")))]
1125: ; ""
1126: ; "add.w %3,@(%c2,%0,%1)")
1127:
1128:
1129: ;; add instructions
1130:
1131: ;; Note that the last two alternatives are near-duplicates
1132: ;; in order to handle insns generated by reload.
1133: ;; This is needed since they are not themselves reloaded,
1134: ;; so commutativity won't apply to them.
1135:
1136: (define_insn "addsi3"
1137: [(set (match_operand:SI 0 "general_operand" "=rm,!r,!r")
1138: (plus:SI (match_operand:SI 1 "general_operand" "%0,r,ri")
1139: (match_operand:SI 2 "general_operand" "rmi,ri,r")))]
1140: ""
1141: "*
1142: {
1143: if (which_alternative == 0)
1144: {
1145: if (GET_CODE (operands[2]) == CONST_INT)
1146: {
1147: operands[1] = operands[2];
1148: return add_imm_word (INTVAL (operands[1]), operands[0], &operands[1]);
1149: }
1150: else
1151: return \"add.w %2,%0\";
1152: }
1153: else
1154: {
1155: if (GET_CODE (operands[1]) == REG
1156: && REGNO (operands[0]) == REGNO (operands[1]))
1157: return \"add.w %2,%0\";
1158: if (GET_CODE (operands[2]) == REG
1159: && REGNO (operands[0]) == REGNO (operands[2]))
1160: return \"add.w %1,%0\";
1161:
1162: if (GET_CODE (operands[1]) == REG)
1163: {
1164: if (GET_CODE (operands[2]) == REG)
1165: return \"mova.w @(%1,%2),%0\";
1166: else
1167: return \"mova.w @(%c2,%1),%0\";
1168: }
1169: else
1170: return \"mova.w @(%c1,%2),%0\";
1171: }
1172: }")
1173:
1174: (define_insn ""
1175: [(set (match_operand:SI 0 "general_operand" "=rm")
1176: (plus:SI (match_operand:SI 1 "general_operand" "0")
1177: (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmi"))))]
1178: ""
1179: "*
1180: {
1181: if (CONSTANT_P (operands[2]))
1182: {
1183: operands[1] = operands[2];
1184: return add_imm_word (INTVAL (operands[1]), operands[0], &operands[1]);
1185: }
1186: else
1187: return \"add %2.h,%0.w\";
1188: }")
1189:
1190: (define_insn "addhi3"
1191: [(set (match_operand:HI 0 "general_operand" "=rm")
1192: (plus:HI (match_operand:HI 1 "general_operand" "%0")
1193: (match_operand:HI 2 "general_operand" "rmi")))]
1194: ""
1195: "*
1196: {
1197: if (GET_CODE (operands[2]) == CONST_INT
1198: && INTVAL (operands[2]) < 0)
1199: return \"sub.h #%n2,%0\";
1200: if (GREG_P (operands[0]))
1201: {
1202: if (CONSTANT_P (operands[2]))
1203: return \"add:l %2,%0.w\";
1204: else
1205: return \"add:l %2.h,%0.w\";
1206: }
1207: return \"add.h %2,%0\";
1208: }")
1209:
1210: (define_insn ""
1211: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm"))
1212: (plus:HI (match_dup 0)
1213: (match_operand:HI 1 "general_operand" "rmi")))]
1214: ""
1215: "add.h %1,%0")
1216:
1217: (define_insn "addqi3"
1218: [(set (match_operand:QI 0 "general_operand" "=rm")
1219: (plus:QI (match_operand:QI 1 "general_operand" "%0")
1220: (match_operand:QI 2 "general_operand" "rmi")))]
1221: ""
1222: "*
1223: {
1224: if (GET_CODE (operands[2]) == CONST_INT
1225: && INTVAL (operands[2]) < 0)
1226: return \"sub.b #%n2,%0\";
1227: if (GREG_P (operands[0]))
1228: {
1229: if (CONSTANT_P (operands[2]))
1230: return \"add:l %2,%0.w\";
1231: else
1232: return \"add:l %2.b,%0.w\";
1233: }
1234: return \"add.b %2,%0\";
1235: }")
1236:
1237: (define_insn ""
1238: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm"))
1239: (plus:QI (match_dup 0)
1240: (match_operand:QI 1 "general_operand" "rmi")))]
1241: ""
1242: "add.b %1,%0")
1243:
1244: (define_insn "adddf3"
1245: [(set (match_operand:DF 0 "general_operand" "=f")
1246: (plus:DF (match_operand:DF 1 "general_operand" "%0")
1247: (match_operand:DF 2 "general_operand" "fmG")))]
1248: "TARGET_FPU"
1249: "fadd.d %f2,%0")
1250:
1251: (define_insn "addsf3"
1252: [(set (match_operand:SF 0 "general_operand" "=f")
1253: (plus:SF (match_operand:SF 1 "general_operand" "%0")
1254: (match_operand:SF 2 "general_operand" "fmG")))]
1255: "TARGET_FPU"
1256: "fadd.s %f2,%0")
1257:
1258: ;; subtract instructions
1259:
1260: (define_insn "subsi3"
1261: [(set (match_operand:SI 0 "general_operand" "=rm,!r")
1262: (minus:SI (match_operand:SI 1 "general_operand" "0,r")
1263: (match_operand:SI 2 "general_operand" "rmi,i")))]
1264: ""
1265: "*
1266: {
1267: if (which_alternative == 0
1268: || (GET_CODE (operands[1]) == REG
1269: && REGNO (operands[0]) == REGNO (operands[1])))
1270: {
1271: if (GET_CODE (operands[2]) == CONST_INT)
1272: {
1273: operands[1] = operands[2];
1274: return sub_imm_word (INTVAL (operands[1]),
1275: operands[0], &operands[1]);
1276: }
1277: else
1278: return \"sub.w %2,%0\";
1279: }
1280: else
1281: return \"mova.w @(%n2,%1),%0\";
1282: }")
1283:
1284: (define_insn ""
1285: [(set (match_operand:SI 0 "general_operand" "=rm")
1286: (minus:SI (match_operand:SI 1 "general_operand" "0")
1287: (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmi"))))]
1288: ""
1289: "sub %2.h,%0.w")
1290:
1291: (define_insn "subhi3"
1292: [(set (match_operand:HI 0 "general_operand" "=rm")
1293: (minus:HI (match_operand:HI 1 "general_operand" "0")
1294: (match_operand:HI 2 "general_operand" "rmi")))]
1295: ""
1296: "*
1297: {
1298: if (GET_CODE (operands[2]) == CONST_INT
1299: && INTVAL (operands[2]) < 0
1300: && INTVAL (operands[2]) != 0x8000)
1301: return \"add.h #%n2,%0\";
1302: return \"sub.h %2,%0\";
1303: }")
1304:
1305: (define_insn ""
1306: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm"))
1307: (minus:HI (match_dup 0)
1308: (match_operand:HI 1 "general_operand" "rmi")))]
1309: ""
1310: "sub.h %1,%0")
1311:
1312: (define_insn "subqi3"
1313: [(set (match_operand:QI 0 "general_operand" "=rm")
1314: (minus:QI (match_operand:QI 1 "general_operand" "0")
1315: (match_operand:QI 2 "general_operand" "rmi")))]
1316: ""
1317: "*
1318: {
1319: if (GET_CODE (operands[2]) == CONST_INT
1320: && INTVAL (operands[2]) < 0
1321: && INTVAL (operands[2]) != 0x80)
1322: return \"add.b #%n2,%0\";
1323: return \"sub.b %2,%0\";
1324: }")
1325:
1326: (define_insn ""
1327: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm"))
1328: (minus:QI (match_dup 0)
1329: (match_operand:QI 1 "general_operand" "rmi")))]
1330: ""
1331: "sub.b %1,%0")
1332:
1333: (define_insn "subdf3"
1334: [(set (match_operand:DF 0 "general_operand" "=f")
1335: (minus:DF (match_operand:DF 1 "general_operand" "0")
1336: (match_operand:DF 2 "general_operand" "fmG")))]
1337: "TARGET_FPU"
1338: "fsub.d %f2,%0")
1339:
1340: (define_insn "subsf3"
1341: [(set (match_operand:SF 0 "general_operand" "=f")
1342: (minus:SF (match_operand:SF 1 "general_operand" "0")
1343: (match_operand:SF 2 "general_operand" "fmG")))]
1344: "TARGET_FPU"
1345: "fsub.s %f2,%0")
1346:
1347:
1348: ;; multiply instructions
1349:
1350: (define_insn "mulqi3"
1351: [(set (match_operand:QI 0 "general_operand" "=rm")
1352: (mult:QI (match_operand:QI 1 "general_operand" "%0")
1353: (match_operand:QI 2 "general_operand" "rmi")))]
1354: ""
1355: "mul.b %2,%0")
1356:
1357:
1358: (define_insn "mulhi3"
1359: [(set (match_operand:HI 0 "general_operand" "=rm")
1360: (mult:HI (match_operand:HI 1 "general_operand" "%0")
1361: (match_operand:HI 2 "general_operand" "rmi")))]
1362: ""
1363: "mul.h %2,%0")
1364:
1365: ;; define_insn "mulhisi3"
1366:
1367: (define_insn "mulsi3"
1368: [(set (match_operand:SI 0 "general_operand" "=rm")
1369: (mult:SI (match_operand:SI 1 "general_operand" "%0")
1370: (match_operand:SI 2 "general_operand" "rmi")))]
1371: ""
1372: "mul.w %2,%0")
1373:
1374: (define_insn "muldf3"
1375: [(set (match_operand:DF 0 "general_operand" "=f")
1376: (mult:DF (match_operand:DF 1 "general_operand" "%0")
1377: (match_operand:DF 2 "general_operand" "fmG")))]
1378: "TARGET_FPU"
1379: "fmul.d %f2,%0")
1380:
1381: (define_insn "mulsf3"
1382: [(set (match_operand:SF 0 "general_operand" "=f")
1383: (mult:SF (match_operand:SF 1 "general_operand" "%0")
1384: (match_operand:SF 2 "general_operand" "fmG")))]
1385: "TARGET_FPU"
1386: "fmul.s %f2,%0")
1387:
1388:
1389: ;; divide instructions
1390:
1391: (define_insn "divqi3"
1392: [(set (match_operand:QI 0 "general_operand" "=rm")
1393: (div:QI (match_operand:QI 1 "general_operand" "0")
1394: (match_operand:QI 2 "general_operand" "rmi")))]
1395: ""
1396: "div.b %2,%0")
1397:
1398: (define_insn "divhi3"
1399: [(set (match_operand:HI 0 "general_operand" "=rm")
1400: (div:HI (match_operand:HI 1 "general_operand" "0")
1401: (match_operand:HI 2 "general_operand" "rmi")))]
1402: ""
1403: "div.h %2,%0")
1404:
1405: (define_insn "divhisi3"
1406: [(set (match_operand:HI 0 "general_operand" "=r")
1407: (div:HI (match_operand:SI 1 "general_operand" "0")
1408: (match_operand:HI 2 "general_operand" "rmi")))]
1409: ""
1410: "div %2.h,%0.w")
1411:
1412: (define_insn "divsi3"
1413: [(set (match_operand:SI 0 "general_operand" "=rm")
1414: (div:SI (match_operand:SI 1 "general_operand" "0")
1415: (match_operand:SI 2 "general_operand" "rmi")))]
1416: ""
1417: "div.w %2,%0")
1418:
1419: (define_insn "udivqi3"
1420: [(set (match_operand:QI 0 "general_operand" "=rm")
1421: (udiv:QI (match_operand:QI 1 "general_operand" "0")
1422: (match_operand:QI 2 "general_operand" "rmi")))]
1423: ""
1424: "divu.b %2,%0")
1425:
1426: (define_insn "udivhi3"
1427: [(set (match_operand:HI 0 "general_operand" "=rm")
1428: (udiv:HI (match_operand:HI 1 "general_operand" "0")
1429: (match_operand:HI 2 "general_operand" "rmi")))]
1430: ""
1431: "divu.h %2,%0")
1432:
1433: (define_insn "udivhisi3"
1434: [(set (match_operand:HI 0 "general_operand" "=r")
1435: (udiv:HI (match_operand:SI 1 "general_operand" "0")
1436: (match_operand:HI 2 "general_operand" "rmi")))]
1437: ""
1438: "divu %2.h,%0.w")
1439:
1440: (define_insn "udivsi3"
1441: [(set (match_operand:SI 0 "general_operand" "=rm")
1442: (udiv:SI (match_operand:SI 1 "general_operand" "0")
1443: (match_operand:SI 2 "general_operand" "rmi")))]
1444: ""
1445: "divu.w %2,%0")
1446:
1447: (define_insn "divdf3"
1448: [(set (match_operand:DF 0 "general_operand" "=f")
1449: (div:DF (match_operand:DF 1 "general_operand" "0")
1450: (match_operand:DF 2 "general_operand" "fmG")))]
1451: "TARGET_FPU"
1452: "fdiv.d %f2,%0")
1453:
1454: (define_insn "divsf3"
1455: [(set (match_operand:SF 0 "general_operand" "=f")
1456: (div:SF (match_operand:SF 1 "general_operand" "0")
1457: (match_operand:SF 2 "general_operand" "fmG")))]
1458: "TARGET_FPU"
1459: "fdiv.s %f2,%0")
1460:
1461: ;; Remainder instructions.
1462:
1463: (define_insn "modqi3"
1464: [(set (match_operand:QI 0 "general_operand" "=rm")
1465: (mod:QI (match_operand:QI 1 "general_operand" "0")
1466: (match_operand:QI 2 "general_operand" "rmi")))]
1467: ""
1468: "rem.b %2,%0")
1469:
1470: (define_insn "modhisi3"
1471: [(set (match_operand:HI 0 "general_operand" "=r")
1472: (mod:HI (match_operand:SI 1 "general_operand" "0")
1473: (match_operand:HI 2 "general_operand" "rmi")))]
1474: ""
1475: "rem.h %2,%0")
1476:
1477: (define_insn "umodqi3"
1478: [(set (match_operand:QI 0 "general_operand" "=rm")
1479: (umod:QI (match_operand:QI 1 "general_operand" "0")
1480: (match_operand:QI 2 "general_operand" "rmi")))]
1481: ""
1482: "remu.b %2,%0")
1483:
1484: (define_insn "umodhi3"
1485: [(set (match_operand:HI 0 "general_operand" "=rm")
1486: (umod:HI (match_operand:HI 1 "general_operand" "0")
1487: (match_operand:HI 2 "general_operand" "rmi")))]
1488: ""
1489: "remu.h %2,%0")
1490:
1491: (define_insn "umodhisi3"
1492: [(set (match_operand:HI 0 "general_operand" "=r")
1493: (umod:HI (match_operand:SI 1 "general_operand" "0")
1494: (match_operand:HI 2 "general_operand" "rmi")))]
1495: ""
1496: "remu %2.h,%0.w")
1497:
1498: ;; define_insn "divmodsi4"
1499:
1500: (define_insn "udivmodsi4"
1501: [(set (match_operand:SI 0 "general_operand" "=rm")
1502: (udiv:SI (match_operand:SI 1 "general_operand" "0")
1503: (match_operand:SI 2 "general_operand" "rmi")))
1504: (set (match_operand:SI 3 "general_operand" "=r")
1505: (umod:SI (match_dup 1) (match_dup 2)))]
1506: ""
1507: "mov.w #0,%3;divx.w %2,%0,%3")
1508:
1509: ;; logical-and instructions
1510:
1511: (define_insn "andsi3"
1512: [(set (match_operand:SI 0 "general_operand" "=rm")
1513: (and:SI (match_operand:SI 1 "general_operand" "%0")
1514: (match_operand:SI 2 "general_operand" "rmi")))]
1515: ""
1516: "*
1517: {
1518: if (GET_CODE (operands[2]) == CONST_INT
1519: && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
1520: && (GREG_P (operands[0])
1521: || offsettable_memref_p (operands[0])))
1522:
1523: {
1524: if (GET_CODE (operands[0]) != REG)
1525: operands[0] = adj_offsettable_operand (operands[0], 2);
1526: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1527: INTVAL (operands[2]) & 0xffff);
1528: /* Do not delete a following tstl %0 insn; that would be incorrect. */
1529: CC_STATUS_INIT;
1530: return \"and.h %2,%0\";
1531: }
1532: return \"and.w %2,%0\";
1533: }")
1534:
1535: (define_insn "andhi3"
1536: [(set (match_operand:HI 0 "general_operand" "=rm")
1537: (and:HI (match_operand:HI 1 "general_operand" "%0")
1538: (match_operand:HI 2 "general_operand" "rmi")))]
1539: ""
1540: "and.h %2,%0")
1541:
1542: (define_insn "andqi3"
1543: [(set (match_operand:QI 0 "general_operand" "=rm")
1544: (and:QI (match_operand:QI 1 "general_operand" "%0")
1545: (match_operand:QI 2 "general_operand" "rmi")))]
1546: ""
1547: "and.b %2,%0")
1548:
1549: (define_insn ""
1550: [(set (match_operand:SI 0 "general_operand" "=r")
1551: (and:SI (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm"))
1552: (match_operand:SI 2 "general_operand" "0")))]
1553: ""
1554: "*
1555: {
1556: if (GET_CODE (operands[1]) == CONST_INT)
1557: return \"and %1,%0.w\";
1558: return \"and %1.h,%0.w\";
1559: }")
1560:
1561:
1562: (define_insn ""
1563: [(set (match_operand:SI 0 "general_operand" "=r")
1564: (and:SI (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm"))
1565: (match_operand:SI 2 "general_operand" "0")))]
1566: ""
1567: "*
1568: {
1569: if (GET_CODE (operands[1]) == CONST_INT)
1570: return \"and %1,%0.w\";
1571: return \"and %1.b,%0.w\";
1572: }")
1573:
1574: ;; inclusive-or instructions
1575:
1576: (define_insn "iorsi3"
1577: [(set (match_operand:SI 0 "general_operand" "=rm")
1578: (ior:SI (match_operand:SI 1 "general_operand" "%0")
1579: (match_operand:SI 2 "general_operand" "rmi")))]
1580: ""
1581: "*
1582: {
1583: register int logval;
1584: if (GET_CODE (operands[2]) == CONST_INT
1585: && INTVAL (operands[2]) >> 16 == 0
1586: && (GREG_P (operands[0])
1587: || offsettable_memref_p (operands[0])))
1588: {
1589: if (GET_CODE (operands[0]) != REG)
1590: operands[0] = adj_offsettable_operand (operands[0], 2);
1591: /* Do not delete a following tstl %0 insn; that would be incorrect. */
1592: CC_STATUS_INIT;
1593: return \"or.h %2,%0\";
1594: }
1595: if (GET_CODE (operands[2]) == CONST_INT
1596: && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
1597: && (GREG_P (operands[0])
1598: || offsettable_memref_p (operands[0])))
1599: {
1600: if (GREG_P (operands[0]))
1601: {
1602: if (logval < 7)
1603: {
1604: operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - logval);
1605: return \"bset.b %1,%0\";
1606: }
1607: operands[1] = gen_rtx (CONST_INT, VOIDmode, 31 - logval);
1608: return \"bset.w %1,%0\";
1609: }
1610: else
1611: {
1612: operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
1613: operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - (logval % 8));
1614: }
1615: return \"bset.b %1,%0\";
1616: }
1617: return \"or.w %2,%0\";
1618: }")
1619:
1620: (define_insn "iorhi3"
1621: [(set (match_operand:HI 0 "general_operand" "=rm")
1622: (ior:HI (match_operand:HI 1 "general_operand" "%0")
1623: (match_operand:HI 2 "general_operand" "rmi")))]
1624: ""
1625: "or.h %2,%0")
1626:
1627: (define_insn "iorqi3"
1628: [(set (match_operand:QI 0 "general_operand" "=rm")
1629: (ior:QI (match_operand:QI 1 "general_operand" "%0")
1630: (match_operand:QI 2 "general_operand" "rmi")))]
1631: ""
1632: "or.b %2,%0")
1633:
1634: ;; xor instructions
1635:
1636: (define_insn "xorsi3"
1637: [(set (match_operand:SI 0 "general_operand" "=rm")
1638: (xor:SI (match_operand:SI 1 "general_operand" "%0")
1639: (match_operand:SI 2 "general_operand" "rmi")))]
1640: ""
1641: "*
1642: {
1643: if (GET_CODE (operands[2]) == CONST_INT
1644: && INTVAL (operands[2]) >> 16 == 0
1645: && (offsettable_memref_p (operands[0]) || GREG_P (operands[0])))
1646: {
1647: if (! GREG_P (operands[0]))
1648: operands[0] = adj_offsettable_operand (operands[0], 2);
1649: /* Do not delete a following tstl %0 insn; that would be incorrect. */
1650: CC_STATUS_INIT;
1651: return \"xor.h %2,%0\";
1652: }
1653: return \"xor.w %2,%0\";
1654: }")
1655:
1656: (define_insn "xorhi3"
1657: [(set (match_operand:HI 0 "general_operand" "=rm")
1658: (xor:HI (match_operand:HI 1 "general_operand" "%0")
1659: (match_operand:HI 2 "general_operand" "rmi")))]
1660: ""
1661: "xor.h %2,%0")
1662:
1663: (define_insn "xorqi3"
1664: [(set (match_operand:QI 0 "general_operand" "=rm")
1665: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1666: (match_operand:QI 2 "general_operand" "rmi")))]
1667: ""
1668: "xor.b %2,%0")
1669:
1670: ;; negation instructions
1671:
1672: (define_insn "negsi2"
1673: [(set (match_operand:SI 0 "general_operand" "=rm")
1674: (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1675: ""
1676: "neg.w %0")
1677:
1678: (define_insn "neghi2"
1679: [(set (match_operand:HI 0 "general_operand" "=rm")
1680: (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1681: ""
1682: "neg.h %0")
1683:
1684: (define_insn "negqi2"
1685: [(set (match_operand:QI 0 "general_operand" "=rm")
1686: (neg:QI (match_operand:QI 1 "general_operand" "0")))]
1687: ""
1688: "neg.b %0")
1689:
1690: (define_insn "negsf2"
1691: [(set (match_operand:SF 0 "general_operand" "=f")
1692: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1693: "TARGET_FPU"
1694: "fneg.s %f1,%0")
1695:
1696:
1697: (define_insn "negdf2"
1698: [(set (match_operand:DF 0 "general_operand" "=f")
1699: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1700: "TARGET_FPU"
1701: "fneg.d %f1,%0")
1702:
1703:
1704: ;; Absolute value instructions
1705:
1706: (define_insn "abssf2"
1707: [(set (match_operand:SF 0 "general_operand" "=f")
1708: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
1709: "TARGET_FPU"
1710: "fabs.s %f1,%0")
1711:
1712: (define_insn "absdf2"
1713: [(set (match_operand:DF 0 "general_operand" "=f")
1714: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
1715: "TARGET_FPU"
1716: "fabs.d %f1,%0")
1717:
1718:
1719: ;; one complement instructions
1720:
1721: (define_insn "one_cmplsi2"
1722: [(set (match_operand:SI 0 "general_operand" "=rm")
1723: (not:SI (match_operand:SI 1 "general_operand" "0")))]
1724: ""
1725: "not.w %0")
1726:
1727: (define_insn "one_cmplhi2"
1728: [(set (match_operand:HI 0 "general_operand" "=rm")
1729: (not:HI (match_operand:HI 1 "general_operand" "0")))]
1730: ""
1731: "not.h %0")
1732:
1733: (define_insn "one_cmplqi2"
1734: [(set (match_operand:QI 0 "general_operand" "=rm")
1735: (not:QI (match_operand:QI 1 "general_operand" "0")))]
1736: ""
1737: "not.b %0")
1738:
1739: ;; Optimized special case of shifting.
1740: ;; Must precede the general case.
1741:
1742: (define_insn ""
1743: [(set (match_operand:SI 0 "general_operand" "=r")
1744: (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
1745: (const_int 24)))]
1746: "GET_CODE (XEXP (operands[1], 0)) != POST_INC
1747: && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC"
1748: "mov:l %1.b,%0.w")
1749:
1750: (define_insn ""
1751: [(set (match_operand:SI 0 "general_operand" "=r")
1752: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
1753: (const_int 24)))]
1754: "GET_CODE (XEXP (operands[1], 0)) != POST_INC
1755: && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC"
1756: "movu %1.b,%0.w")
1757:
1758: (define_insn ""
1759: [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i")
1760: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
1761: (const_int 24))))]
1762: "(GET_CODE (operands[0]) == CONST_INT
1763: && (INTVAL (operands[0]) & ~0xff) == 0)"
1764: "*
1765: {
1766: cc_status.flags |= CC_REVERSED;
1767: if (my_signed_comp (insn))
1768: return \"cmp.b %0,%1\";
1769: return \"cmpu.b %0,%1\";
1770: }")
1771:
1772: (define_insn ""
1773: [(set (cc0) (compare (lshiftrt:SI (match_operand:SI 0 "memory_operand" "m")
1774: (const_int 24))
1775: (match_operand:QI 1 "general_operand" "i")))]
1776: "(GET_CODE (operands[1]) == CONST_INT
1777: && (INTVAL (operands[1]) & ~0xff) == 0)"
1778: "*
1779: if (my_signed_comp (insn))
1780: return \"cmp.b %1,%0\";
1781: return \"cmpu.b %1,%0\";
1782: ")
1783:
1784: (define_insn ""
1785: [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i")
1786: (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
1787: (const_int 24))))]
1788: "(GET_CODE (operands[0]) == CONST_INT
1789: && ((INTVAL (operands[0]) + 0x80) & ~0xff) == 0)"
1790: "*
1791: cc_status.flags |= CC_REVERSED;
1792: if (my_signed_comp (insn))
1793: return \"cmp.b %0,%1\";
1794: return \"cmpu.b %0,%1\";
1795: ")
1796:
1797: (define_insn ""
1798: [(set (cc0) (compare (ashiftrt:SI (match_operand:SI 0 "memory_operand" "m")
1799: (const_int 24))
1800: (match_operand:QI 1 "general_operand" "i")))]
1801: "(GET_CODE (operands[1]) == CONST_INT
1802: && ((INTVAL (operands[1]) + 0x80) & ~0xff) == 0)"
1803: "*
1804: if (my_signed_comp (insn))
1805: return \"cmp.b %1,%0\";
1806: return \"cmpu.b %1,%0\";
1807: ")
1808:
1809: ;; arithmetic shift instructions
1810: ;; We don't need the shift memory by 1 bit instruction
1811:
1812: (define_insn "ashlsi3"
1813: [(set (match_operand:SI 0 "general_operand" "=rm")
1814: (ashift:SI (match_operand:SI 1 "general_operand" "0")
1815: (match_operand:SI 2 "general_operand" "rmi")))]
1816: ""
1817: "sha.w %2,%0")
1818:
1819: (define_insn "ashlhi3"
1820: [(set (match_operand:HI 0 "general_operand" "=rm")
1821: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1822: (match_operand:HI 2 "general_operand" "rmi")))]
1823: ""
1824: "sha.h %2,%0")
1825:
1826: (define_insn "ashlqi3"
1827: [(set (match_operand:QI 0 "general_operand" "=rm")
1828: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1829: (match_operand:QI 2 "general_operand" "rmi")))]
1830: ""
1831: "sha.b %2,%0")
1832:
1833: ;; Arithmetic right shift on the Gmicro works by negating the shift count
1834:
1835: ;; ashiftrt -> ashift
1836: (define_expand "ashrsi3"
1837: [(set (match_operand:SI 0 "general_operand" "=rm")
1838: (ashift:SI (match_operand:SI 1 "general_operand" "0")
1839: (match_operand:SI 2 "general_operand" "rmi")))]
1840: ""
1841: "{ operands[2] = negate_rtx (SImode, operands[2]); }")
1842:
1843: ;; ashiftrt -> ashift
1844: (define_expand "ashrhi3"
1845: [(set (match_operand:HI 0 "general_operand" "=rm")
1846: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1847: (match_operand:HI 2 "general_operand" "rmi")))]
1848: ""
1849: " { operands[2] = negate_rtx (HImode, operands[2]); }")
1850:
1851: ;; ashiftrt -> ashift
1852: (define_expand "ashrqi3"
1853: [(set (match_operand:QI 0 "general_operand" "=rm")
1854: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1855: (match_operand:QI 2 "general_operand" "rmi")))]
1856: ""
1857: " { operands[2] = negate_rtx (QImode, operands[2]); }")
1858:
1859: ;; logical shift instructions
1860:
1861: (define_insn "lshlsi3"
1862: [(set (match_operand:SI 0 "general_operand" "=rm")
1863: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1864: (match_operand:SI 2 "general_operand" "rmi")))]
1865: ""
1866: "shl.w %2,%0")
1867:
1868: (define_insn "lshlhi3"
1869: [(set (match_operand:HI 0 "general_operand" "=rm")
1870: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1871: (match_operand:HI 2 "general_operand" "rmi")))]
1872: ""
1873: "shl.h %2,%0")
1874:
1875: (define_insn "lshlqi3"
1876: [(set (match_operand:QI 0 "general_operand" "=rm")
1877: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1878: (match_operand:QI 2 "general_operand" "rmi")))]
1879: ""
1880: "shl.b %2,%0")
1881:
1882: ;; lshiftrt -> lshift
1883: (define_expand "lshrsi3"
1884: [(set (match_operand:SI 0 "general_operand" "=rm")
1885: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1886: (match_operand:SI 2 "general_operand" "rmi")))]
1887: ""
1888: " { operands[2] = negate_rtx (SImode, operands[2]); }")
1889:
1890: ;; lshiftrt -> lshift
1891: (define_expand "lshrhi3"
1892: [(set (match_operand:HI 0 "general_operand" "=rm")
1893: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1894: (match_operand:HI 2 "general_operand" "rmi")))]
1895: ""
1896: " { operands[2] = negate_rtx (HImode, operands[2]); }")
1897:
1898: ;; lshiftrt -> lshift
1899: (define_expand "lshrqi3"
1900: [(set (match_operand:QI 0 "general_operand" "=rm")
1901: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1902: (match_operand:QI 2 "general_operand" "rmi")))]
1903: ""
1904: " { operands[2] = negate_rtx (QImode, operands[2]); }")
1905:
1906: ;; rotate instructions
1907:
1908: (define_insn "rotlsi3"
1909: [(set (match_operand:SI 0 "general_operand" "=rm")
1910: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1911: (match_operand:SI 2 "general_operand" "rmi")))]
1912: ""
1913: "rol.w %2,%0")
1914:
1915: (define_insn "rotlhi3"
1916: [(set (match_operand:HI 0 "general_operand" "=rm")
1917: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1918: (match_operand:HI 2 "general_operand" "rmi")))]
1919: ""
1920: "rol.h %2,%0")
1921:
1922: (define_insn "rotlqi3"
1923: [(set (match_operand:QI 0 "general_operand" "=rm")
1924: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1925: (match_operand:QI 2 "general_operand" "rmi")))]
1926: ""
1927: "rol.b %2,%0")
1928:
1929: (define_expand "rotrsi3"
1930: [(set (match_operand:SI 0 "general_operand" "=rm")
1931: (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1932: (match_operand:SI 2 "general_operand" "rmi")))]
1933: ""
1934: " { operands[2] = negate_rtx (SImode, operands[2]); }")
1935:
1936: (define_expand "rotrhi3"
1937: [(set (match_operand:HI 0 "general_operand" "=rm")
1938: (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1939: (match_operand:HI 2 "general_operand" "rmi")))]
1940: ""
1941: " { operands[2] = negate_rtx (HImode, operands[2]); }")
1942:
1943: (define_expand "rotrqi3"
1944: [(set (match_operand:QI 0 "general_operand" "=rm")
1945: (rotatert:QI (match_operand:QI 1 "general_operand" "0")
1946: (match_operand:QI 2 "general_operand" "rmi")))]
1947: ""
1948: " { operands[2] = negate_rtx (QImode, operands[2]); }")
1949:
1950: ;; Special cases of bit-field insns which we should
1951: ;; recognize in preference to the general case.
1952: ;; These handle aligned 8-bit and 16-bit fields,
1953: ;; which can usually be done with move instructions.
1954:
1955: ;; Should I add mode_dependent_address_p ????
1956:
1957: (define_insn ""
1958: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+rm")
1959: (match_operand:SI 1 "immediate_operand" "i")
1960: (match_operand:SI 2 "immediate_operand" "i"))
1961: (match_operand:SI 3 "general_operand" "rm"))]
1962: "TARGET_BITFIELD
1963: && GET_CODE (operands[1]) == CONST_INT
1964: && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1965: && GET_CODE (operands[2]) == CONST_INT
1966: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1967: && (GET_CODE (operands[0]) != REG
1968: || ( INTVAL (operands[1]) + INTVAL (operands[2]) == 32))"
1969: "*
1970: {
1971: if (GET_CODE (operands[3]) == MEM)
1972: operands[3] = adj_offsettable_operand (operands[3],
1973: (32 - INTVAL (operands[1])) / 8);
1974:
1975: if (GET_CODE (operands[0]) == REG)
1976: {
1977: if (INTVAL (operands[1]) == 8)
1978: return \"movu %3.b,%0.w\";
1979: return \"movu %3.h,%0.w\";
1980: }
1981: else
1982: {
1983: operands[0]
1984: = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
1985: if (INTVAL (operands[1]) == 8)
1986: return \"mov.b %3,%0\";
1987: return \"mov.h %3,%0\";
1988: }
1989: }")
1990:
1991: (define_insn ""
1992: [(set (match_operand:SI 0 "general_operand" "=&r")
1993: (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "rm")
1994: (match_operand:SI 2 "immediate_operand" "i")
1995: (match_operand:SI 3 "immediate_operand" "i")))]
1996: "TARGET_BITFIELD
1997: && GET_CODE (operands[2]) == CONST_INT
1998: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1999: && GET_CODE (operands[3]) == CONST_INT
2000: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
2001: "*
2002: {
2003: if (!REG_P (operands[1]))
2004: operands[1]
2005: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
2006:
2007: if (REG_P (operands[0]))
2008: {
2009: if (REG_P (operands[1]))
2010: {
2011: if (INTVAL (operands[2]) == 8)
2012: { /* width == 8 */
2013: switch (INTVAL (operands[3]))
2014: {
2015: case 0:
2016: return \"mov.w %1,%0;shl.w #-24,%0\";
2017: break;
2018: case 8:
2019: return \"mov.w %1,%0;shl.w #8,%0;shl.w #-24,%0\";
2020: break;
2021: case 16:
2022: return \"mov.w %1,%0;shl.w #16,%0;shl.w #-24,%0\";
2023: break;
2024: case 24:
2025: return \"movu %1.b,%0.w\";
2026: break;
2027: default:
2028: myabort (2);
2029: }
2030: }
2031: else
2032: {
2033: switch (INTVAL (operands[3]))
2034: {
2035: case 0:
2036: return \"mov.w %1,%0;shl.w #-16,%0\";
2037: break;
2038: case 16:
2039: return \"movu %1.h,%0.w\";
2040: break;
2041: default:
2042: myabort (3);
2043: }
2044: }
2045: }
2046: else
2047: {
2048: if (INTVAL (operands[2]) == 8)
2049: return \"movu %1.h,%0.w\";
2050: else
2051: return \"movu %1.b,%0.w\";
2052: }
2053: }
2054: else
2055: { /* op[0] == MEM */
2056: if (INTVAL (operands[2]) == 8)
2057: return \"movu %1.b,%0.w\";
2058: return \"movu %1.h,%0.w\";
2059: }
2060: }")
2061:
2062: (define_insn ""
2063: [(set (match_operand:SI 0 "general_operand" "=r")
2064: (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
2065: (match_operand:SI 2 "immediate_operand" "i")
2066: (match_operand:SI 3 "immediate_operand" "i")))]
2067: "TARGET_BITFIELD
2068: && GET_CODE (operands[2]) == CONST_INT
2069: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
2070: && GET_CODE (operands[3]) == CONST_INT
2071: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
2072: "*
2073: {
2074: if (!REG_P (operands[1]))
2075: operands[1]
2076: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
2077:
2078: if (REG_P (operands[0]))
2079: {
2080: if (REG_P (operands[1]))
2081: {
2082: if (INTVAL (operands[2]) == 8)
2083: { /* width == 8 */
2084: switch (INTVAL (operands[3]))
2085: {
2086: case 0:
2087: return \"mov.w %1,%0;sha.w #-24,%0\";
2088: break;
2089: case 8:
2090: return \"mov.w %1,%0;shl.w #8,%0;sha.w #-24,%0\";
2091: break;
2092: case 16:
2093: return \"mov.w %1,%0;shl.w #16,%0;sha.w #-24,%0\";
2094: break;
2095: case 24:
2096: return \"mov %1.b,%0.w\";
2097: break;
2098: default:
2099: myabort (4);
2100: }
2101: }
2102: else
2103: {
2104: switch (INTVAL (operands[3]))
2105: {
2106: case 0:
2107: return \"mov.w %1,%0;sha.w #-16,%0\";
2108: break;
2109: case 16:
2110: return \"mov %1.h,%0.w\";
2111: break;
2112: default:
2113: myabort (5);
2114: }
2115: }
2116: }
2117: else
2118: {
2119: if (INTVAL (operands[2]) == 8)
2120: return \"mov %1.h,%0.w\";
2121: else
2122: return \"mov %1.b,%0.w\";
2123: }
2124: }
2125: else
2126: { /* op[0] == MEM */
2127: if (INTVAL (operands[2]) == 8)
2128: return \"mov %1.b,%0.w\";
2129: return \"mov %1.h,%0.w\";
2130: }
2131: }")
2132:
2133: ;; Bit field instructions, general cases.
2134: ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
2135: ;; so that its address is reloaded.
2136:
2137: ;; extv dest:SI src(:QI/:SI) width:SI pos:SI
2138: ;; r.w m r.w/# rmi
2139: ;; %0 %1 %2 %3
2140:
2141: (define_insn "extv"
2142: [(set (match_operand:SI 0 "general_operand" "=r")
2143: (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "m")
2144: (match_operand:SI 2 "general_operand" "ri")
2145: (match_operand:SI 3 "general_operand" "rmi")))]
2146: "TARGET_BITFIELD"
2147: "bfext %3,%2,%1,%0")
2148:
2149:
2150: (define_insn "extzv"
2151: [(set (match_operand:SI 0 "general_operand" "=r")
2152: (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "m")
2153: (match_operand:SI 2 "general_operand" "ri")
2154: (match_operand:SI 3 "general_operand" "rmi")))]
2155: "TARGET_BITFIELD"
2156: "bfextu %3,%2,%1,%0")
2157:
2158: ;; There is no insn on the Gmicro to NOT/SET/CLR bitfield.
2159:
2160:
2161: ;; insv dest(BF):QI/SI width:SI pos:SI src:SI
2162: ;; m r.w rmi r.w/i
2163: ;; 0 1 2 3
2164:
2165:
2166: (define_insn "insv"
2167: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+m,m")
2168: (match_operand:SI 1 "general_operand" "r,i")
2169: (match_operand:SI 2 "general_operand" "rmi,i"))
2170: (match_operand:SI 3 "general_operand" "ri,ri"))]
2171: "TARGET_BITFIELD"
2172: "bfinsu %3,%2,%1,%0")
2173: ;;; bfins/bfinsu ????????
2174:
2175: ;; == == == == == == == == == == == == ==
2176:
2177: ;; Now recognize bit field insns that operate on registers
2178: ;; (or at least were intended to do so).
2179:
2180: ;; On the Gmicro/300,
2181: ;; bitfield instructions are not applicable to registers ;-<
2182: ;; But I write the register cases, because without them the gcc
2183: ;; seems to use "and" instruction with some other instructions
2184: ;; instead of using a shift instruction.
2185: ;; It is because on many processors shift instructions are slower.
2186: ;; On the Gmicro/300 which has a barrel shifter,
2187: ;; it is faster to use a shift instruction.
2188: ;;
2189: ;; Restricts width and offset to be immediates.
2190: ;;
2191: (define_insn ""
2192: [(set (match_operand:SI 0 "general_operand" "=r")
2193: (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "r")
2194: (match_operand:SI 2 "immediate_operand" "i")
2195: (match_operand:SI 3 "immediate_operand" "i")))]
2196: "TARGET_BITFIELD"
2197: "*
2198: {
2199: if (REGNO (operands[0]) != REGNO (operands[1]))
2200: output_asm_insn (\"mov.w %1,%0\", operands);
2201: if (INTVAL (operands[3]) != 0)
2202: output_asm_insn (\"shl.w %3,%0\", operands);
2203: operands[2] = gen_rtx (CONST_INT, VOIDmode, -(32 - INTVAL (operands[2])));
2204: return \"sha.w %3,%0\";
2205: }")
2206:
2207:
2208: (define_insn ""
2209: [(set (match_operand:SI 0 "general_operand" "=r")
2210: (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "r")
2211: (match_operand:SI 2 "immediate_operand" "i")
2212: (match_operand:SI 3 "immediate_operand" "i")))]
2213: "TARGET_BITFIELD"
2214: "*
2215: {
2216: if (REGNO (operands[0]) != REGNO (operands[1]))
2217: output_asm_insn (\"mov.w %1,%0\", operands);
2218: if (INTVAL (operands[3]) != 0)
2219: output_asm_insn (\"shl.w %3,%0\", operands);
2220: operands[2] = gen_rtx (CONST_INT, VOIDmode, -(32 - INTVAL (operands[2])));
2221: return \"shl.w %3,%0\";
2222: }")
2223:
2224:
2225: ;; There are more descriptions for m68k, but not yet for the Gmicro.
2226: ;;
2227:
2228: ;; Basic conditional jump instructions.
2229:
2230:
2231: (define_insn "beq"
2232: [(set (pc)
2233: (if_then_else (eq (cc0)
2234: (const_int 0))
2235: (label_ref (match_operand 0 "" ""))
2236: (pc)))]
2237: ""
2238: "*
2239: {
2240: OUTPUT_JUMP (\"beq %b0\", \"fbeq %b0\", \"beq %b0\");
2241: }")
2242:
2243: (define_insn "bne"
2244: [(set (pc)
2245: (if_then_else (ne (cc0)
2246: (const_int 0))
2247: (label_ref (match_operand 0 "" ""))
2248: (pc)))]
2249: ""
2250: "*
2251: {
2252: OUTPUT_JUMP (\"bne %b0\", \"fbne %b0\", \"bne %b0\");
2253: }")
2254:
2255: (define_insn "bgt"
2256: [(set (pc)
2257: (if_then_else (gt (cc0)
2258: (const_int 0))
2259: (label_ref (match_operand 0 "" ""))
2260: (pc)))]
2261: ""
2262: "*
2263: OUTPUT_JUMP (\"bgt %b0\", \"fbgt %b0\", 0);
2264: ")
2265:
2266: (define_insn "bgtu"
2267: [(set (pc)
2268: (if_then_else (gtu (cc0)
2269: (const_int 0))
2270: (label_ref (match_operand 0 "" ""))
2271: (pc)))]
2272: ""
2273: "bgt %b0")
2274:
2275: (define_insn "blt"
2276: [(set (pc)
2277: (if_then_else (lt (cc0)
2278: (const_int 0))
2279: (label_ref (match_operand 0 "" ""))
2280: (pc)))]
2281: ""
2282: "*
2283: OUTPUT_JUMP (\"blt %b0\", \"fblt %b0\", \"bms %b0\");
2284: ")
2285:
2286: ;; bms ?????
2287: ;;
2288:
2289: (define_insn "bltu"
2290: [(set (pc)
2291: (if_then_else (ltu (cc0)
2292: (const_int 0))
2293: (label_ref (match_operand 0 "" ""))
2294: (pc)))]
2295: ""
2296: "blt %b0")
2297:
2298: (define_insn "bge"
2299: [(set (pc)
2300: (if_then_else (ge (cc0)
2301: (const_int 0))
2302: (label_ref (match_operand 0 "" ""))
2303: (pc)))]
2304: ""
2305: "*
2306: OUTPUT_JUMP (\"bge %b0\", \"fbge %b0\", \"bmc %b0\");
2307: ")
2308:
2309: ;; bmc ??
2310:
2311: (define_insn "bgeu"
2312: [(set (pc)
2313: (if_then_else (geu (cc0)
2314: (const_int 0))
2315: (label_ref (match_operand 0 "" ""))
2316: (pc)))]
2317: ""
2318: "bge %b0")
2319:
2320: (define_insn "ble"
2321: [(set (pc)
2322: (if_then_else (le (cc0)
2323: (const_int 0))
2324: (label_ref (match_operand 0 "" ""))
2325: (pc)))]
2326: ""
2327: "ble %b0")
2328:
2329: (define_insn "bleu"
2330: [(set (pc)
2331: (if_then_else (leu (cc0)
2332: (const_int 0))
2333: (label_ref (match_operand 0 "" ""))
2334: (pc)))]
2335: ""
2336: "ble %b0")
2337:
2338: ;; Negated conditional jump instructions.
2339:
2340: (define_insn ""
2341: [(set (pc)
2342: (if_then_else (eq (cc0)
2343: (const_int 0))
2344: (pc)
2345: (label_ref (match_operand 0 "" ""))))]
2346: ""
2347: "*
2348: {
2349: OUTPUT_JUMP (\"bne %b0\", \"fbne %b0\", \"bne %b0\");
2350: }")
2351:
2352: (define_insn ""
2353: [(set (pc)
2354: (if_then_else (ne (cc0)
2355: (const_int 0))
2356: (pc)
2357: (label_ref (match_operand 0 "" ""))))]
2358: ""
2359: "*
2360: {
2361: OUTPUT_JUMP (\"beq %b0\", \"fbeq %b0\", \"beq %b0\");
2362: }")
2363:
2364: (define_insn ""
2365: [(set (pc)
2366: (if_then_else (gt (cc0)
2367: (const_int 0))
2368: (pc)
2369: (label_ref (match_operand 0 "" ""))))]
2370: ""
2371: "*
2372: OUTPUT_JUMP (\"ble %b0\", \"fbngt %b0\", 0);
2373: ")
2374: ;; fbngt ???
2375:
2376: (define_insn ""
2377: [(set (pc)
2378: (if_then_else (gtu (cc0)
2379: (const_int 0))
2380: (pc)
2381: (label_ref (match_operand 0 "" ""))))]
2382: ""
2383: "ble %b0")
2384:
2385: (define_insn ""
2386: [(set (pc)
2387: (if_then_else (lt (cc0)
2388: (const_int 0))
2389: (pc)
2390: (label_ref (match_operand 0 "" ""))))]
2391: ""
2392: "*
2393: OUTPUT_JUMP (\"bge %b0\", \"fbnlt %b0\", \"jbmc %b0\");
2394: ")
2395:
2396: (define_insn ""
2397: [(set (pc)
2398: (if_then_else (ltu (cc0)
2399: (const_int 0))
2400: (pc)
2401: (label_ref (match_operand 0 "" ""))))]
2402: ""
2403: "blt %b0")
2404:
2405: (define_insn ""
2406: [(set (pc)
2407: (if_then_else (ge (cc0)
2408: (const_int 0))
2409: (pc)
2410: (label_ref (match_operand 0 "" ""))))]
2411: ""
2412: "*
2413: OUTPUT_JUMP (\"blt %b0\", \"fbnge %b0\", \"jbms %b0\");
2414: ")
2415:
2416: (define_insn ""
2417: [(set (pc)
2418: (if_then_else (geu (cc0)
2419: (const_int 0))
2420: (pc)
2421: (label_ref (match_operand 0 "" ""))))]
2422: ""
2423: "blt %b0")
2424: ;; ????
2425:
2426: (define_insn ""
2427: [(set (pc)
2428: (if_then_else (le (cc0)
2429: (const_int 0))
2430: (pc)
2431: (label_ref (match_operand 0 "" ""))))]
2432: ""
2433: "*
2434: OUTPUT_JUMP (\"bgt %b0\", \"fbnle %b0\", 0);
2435: ")
2436:
2437: (define_insn ""
2438: [(set (pc)
2439: (if_then_else (leu (cc0)
2440: (const_int 0))
2441: (pc)
2442: (label_ref (match_operand 0 "" ""))))]
2443: ""
2444: "bgt %b0")
2445:
2446: ;; Unconditional and other jump instructions
2447: (define_insn "jump"
2448: [(set (pc)
2449: (label_ref (match_operand 0 "" "")))]
2450: ""
2451: "bra %b0")
2452:
2453: (define_insn "tablejump"
2454: [(set (pc)
2455: (plus:SI (pc) (match_operand:SI 0 "general_operand" "r")))
2456: (use (label_ref (match_operand 1 "" "")))]
2457: ""
2458: "jmp @(pc:b,4:4,%0)")
2459:
2460: ;;
2461: ;; Should Add code for "ACB", "SCB". !!! ????
2462: ;; See m68k.h (dbra)
2463: ;;
2464:
2465: ;; Call subroutine with no return value.
2466: (define_insn "call"
2467: [(call (match_operand:QI 0 "general_operand" "m")
2468: (match_operand:SI 1 "general_operand" "rmi"))]
2469: ;; Operand 1 not really used on the Gmicro.
2470:
2471: ""
2472: "*
2473: {
2474: if (GET_CODE (operands[0]) == MEM
2475: && GET_CODE (XEXP (operands[0],0)) == SYMBOL_REF)
2476: return \"bsr %b0\";
2477: return \"jsr %0\";
2478: }")
2479:
2480: ;; Call subroutine, returning value in operand 0
2481: ;; (which must be a hard register).
2482: (define_insn "call_value"
2483: [(set (match_operand 0 "" "=rf")
2484: (call (match_operand:QI 1 "general_operand" "m")
2485: (match_operand:SI 2 "general_operand" "rmi")))]
2486: ;; Operand 2 not really used on the Gmicro.
2487: ""
2488: "*
2489: {
2490: if (GET_CODE (operands[1]) == MEM
2491: && GET_CODE (XEXP (operands[1],0)) == SYMBOL_REF)
2492: return \"bsr %b1\";
2493: return \"jsr %1\";
2494: }")
2495:
2496: ;; Call subroutine returning any type.
2497:
2498: (define_expand "untyped_call"
2499: [(parallel [(call (match_operand 0 "" "")
2500: (const_int 0))
2501: (match_operand 1 "" "")
2502: (match_operand 2 "" "")])]
2503: ""
2504: "
2505: {
2506: int i;
2507:
2508: emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
2509:
2510: for (i = 0; i < XVECLEN (operands[2], 0); i++)
2511: {
2512: rtx set = XVECEXP (operands[2], 0, i);
2513: emit_move_insn (SET_DEST (set), SET_SRC (set));
2514: }
2515:
2516: /* The optimizer does not know that the call sets the function value
2517: registers we stored in the result block. We avoid problems by
2518: claiming that all hard registers are used and clobbered at this
2519: point. */
2520: emit_insn (gen_blockage ());
2521:
2522: DONE;
2523: }")
2524:
2525: ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2526: ;; all of memory. This blocks insns from being moved across this point.
2527:
2528: (define_insn "blockage"
2529: [(unspec_volatile [(const_int 0)] 0)]
2530: ""
2531: "")
2532:
2533: (define_insn "nop"
2534: [(const_int 0)]
2535: ""
2536: "nop")
2537:
2538: ;; Turned off because the general move-an-address pattern handles it.
2539: ;;
2540: ;; Thus goes after the move instructions
2541: ;; because the move instructions are better (require no spilling)
2542: ;; when they can apply.
2543: ;; After add/sub now !!
2544:
2545: ;(define_insn "pushasi"
2546: ; [(set (match_operand:SI 0 "push_operand" "=m")
2547: ; (match_operand:SI 1 "address_operand" "p"))]
2548: ; ""
2549: ; "*
2550: ;{
2551: ; if (GET_CODE (operands[1]) == CONST_INT)
2552: ; return push_imm_word (INTVAL (operands[1]), operands[0]);
2553: ; if (CONSTANT_P (operands[1]))
2554: ; return \"mov.w %1,%-\";
2555: ; if (GET_CODE (operands[1]) == REG)
2556: ; return \"mov.w %1,%-\";
2557: ; else if (GET_CODE (operands[1]) == MEM)
2558: ; {
2559: ; return \"mov.w %1,%-\";
2560: ; }
2561: ; else
2562: ; return \"mova.w %p1,%-\";
2563: ;}")
2564:
2565: ;; This should not be used unless the add/sub insns can't be.
2566:
2567: /* mova.[whq] 89.08.11 for test M.Yuhara */
2568: ;(define_insn ""
2569: ; [(set (match_operand:SI 0 "general_operand" "=rm")
2570: ; (address (match_operand:SI 1 "address_operand" "p")))]
2571: ; ""
2572: ; "*
2573: ;{
2574: ; if (GET_CODE (operands[1]) == CONST_INT)
2575: ; return mov_imm_word (INTVAL (operands[1]), operands[0]);
2576: ; if (CONSTANT_P (operands[1]))
2577: ; return \"mov.w %1,%0\";
2578: ; if (GET_CODE (operands[1]) == REG)
2579: ; return \"mov.w %1,%0\";
2580: ; else if (GET_CODE (operands[1]) == MEM) {
2581: ; operands[1] = XEXP (operands[1],0);
2582: ; return \"mov.w %1,%0\";
2583: ; }
2584: ; else
2585: ; return \"mova.w %p1,%0\";
2586: ;}")
2587:
2588:
2589: (define_insn ""
2590: [(set (match_operand:SI 0 "general_operand" "=rm")
2591: (address (match_operand:HI 1 "address_operand" "")))]
2592: ""
2593: "*
2594: {
2595: if (GET_CODE (operands[1]) == CONST_INT)
2596: return mov_imm_word (INTVAL (operands[1]), operands[0]);
2597: if (CONSTANT_P (operands[1]))
2598: return \"mov.w %1,%0\";
2599: if (GET_CODE (operands[1]) == REG)
2600: return \"mov.w %1,%0\";
2601: else if (GET_CODE (operands[1]) == MEM)
2602: {
2603: operands[1] = XEXP (operands[1],0);
2604: return \"mov.w %1,%0\"; /* OK ? */
2605: }
2606: else
2607: return \"mova.w %p1,%0\";
2608: }")
2609:
2610: ;(define_insn ""
2611: ; [(set (match_operand:SI 0 "general_operand" "=rm")
2612: ; (match_operand:QI 1 "address_operand" "p"))]
2613: ; ""
2614: ; "*
2615: ;{
2616: ; if (push_operand (operands[0], SImode))
2617: ; return \"mova %1,%-\";
2618: ; return \"mova %1,%0\";
2619: ;}")
2620:
2621: ;(define_insn ""
2622: ; [(set (match_operand:SI 0 "general_operand" "=rm")
2623: ; (match_operand:QI 1 "address_operand" "p"))]
2624: ; ""
2625: ; "*
2626: ;{
2627: ; if (CONSTANT_P (operands[1]))
2628: ; return \"mov.w %1,%0\";
2629: ; else if (GET_CODE (operands[1]) == REG)
2630: ; return \"mov.w %1,%0\";
2631: ; else if (GET_CODE (operands[1]) == MEM)
2632: ; {
2633: ; operands[1] = XEXP (operands[1],0);
2634: ; return \"mov.w %1,%0 ; OK?\";
2635: ; }
2636: ; else if (GET_CODE (operands[0]) == REG
2637: ; && GET_CODE (operands[1]) == PLUS)
2638: ; {
2639: ; rtx xreg, xdisp;
2640: ;
2641: ; if (GET_CODE (XEXP (operands[1], 0)) == REG
2642: ; && REGNO (XEXP (operands[1], 0)) == REGNO (operands[0]))
2643: ; {
2644: ; xreg = XEXP (operands[1], 0);
2645: ; xdisp = XEXP (operands[1],1);
2646: ; }
2647: ; else
2648: ; {
2649: ; xreg = XEXP (operands[1], 1);
2650: ; xdisp = XEXP (operands[1],0);
2651: ; }
2652: ;
2653: ; if (GET_CODE (xreg) == REG
2654: ; && REGNO (xreg) == REGNO (operands[0])
2655: ; && (CONSTANT_P (xdisp) || GET_CODE (xdisp) == REG))
2656: ; {
2657: ; operands[1] = xdisp;
2658: ; if (CONSTANT_P (xdisp))
2659: ; return add_imm_word (INTVAL (xdisp), xreg, &operands[1]);
2660: ; else
2661: ; return \"add.w %1,%0\";
2662: ; }
2663: ; }
2664: ; return \"mova.w %p1,%0\";
2665: ;}")
2666:
2667: ;; This is the first machine-dependent peephole optimization.
2668: ;; It is useful when a floating value is returned from a function call
2669: ;; and then is moved into an FP register.
2670: ;; But it is mainly intended to test the support for these optimizations.
2671:
2672: (define_peephole
2673: [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
2674: (set (match_operand:DF 0 "register_operand" "=f")
2675: (match_operand:DF 1 "register_operand" "r"))]
2676: "FPU_REG_P (operands[0]) && ! FPU_REG_P (operands[1])"
2677: "*
2678: {
2679: rtx xoperands[2];
2680: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2681: output_asm_insn (\"mov.w %1,@sp\", xoperands);
2682: output_asm_insn (\"mov.w %1,%-\", operands);
2683: return \"fmov.d %+,%0\";
2684: }
2685: ")
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