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1.1 ! root 1: ;;- Machine description for the Hitachi H8/300 for the GNU C compiler ! 2: ;; Copyright (C) 1992, 1993 Free Software Foundation, Inc. ! 3: ! 4: ;; This file is part of GNU CC. ! 5: ! 6: ;; GNU CC is free software; you can redistribute it and/or modify ! 7: ;; it under the terms of the GNU General Public License as published by ! 8: ;; the Free Software Foundation; either version 2, or (at your option) ! 9: ;; any later version. ! 10: ! 11: ;; GNU CC is distributed in the hope that it will be useful, ! 12: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ! 13: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 14: ;; GNU General Public License for more details. ! 15: ! 16: ;; You should have received a copy of the GNU General Public License ! 17: ;; along with GNU CC; see the file COPYING. If not, write to ! 18: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! 19: ! 20: ! 21: ;; The original PO technology requires these to be ordered by speed, ! 22: ;; so that assigner will pick the fastest. ! 23: ! 24: ;; See file "rtl.def" for documentation on define_insn, match_*, et. al. ! 25: ! 26: (define_attr "type" "branch,return,call,arith,move,float,multi" ! 27: (const_string "arith")) ! 28: ! 29: ;; The size of instructions in bytes. ! 30: ! 31: (define_attr "length" "" ! 32: (cond [(eq_attr "type" "branch") ! 33: (if_then_else (and (ge (minus (pc) (match_dup 0)) ! 34: (const_int -128)) ! 35: (le (minus (pc) (match_dup 0)) ! 36: (const_int 128))) ! 37: (const_int 2) ! 38: (const_int 6)) ! 39: (eq_attr "type" "move") (const_int 4) ! 40: (eq_attr "type" "return") (const_int 2) ! 41: (eq_attr "type" "float") (const_int 12) ! 42: (eq_attr "type" "call") (const_int 4)] ! 43: (const_int 200))) ! 44: ! 45: ! 46: (define_attr "cc" "none,clobber,none_0hit,set,compare,whoops" ! 47: (const_string "whoops")) ! 48: ! 49: ;; ---------------------------------------------------------------------- ! 50: ;; move instructions ! 51: ;; ---------------------------------------------------------------------- ! 52: ! 53: ;; movhi ! 54: ! 55: (define_insn "" ! 56: [(set (match_operand:HI 0 "push_operand" "=<") ! 57: (match_operand:HI 1 "register_operand" "ra"))] ! 58: "" ! 59: "mov.w %T1,%T0" ! 60: [(set_attr "type" "move") ! 61: (set_attr "length" "2") ! 62: (set_attr "cc" "set")]) ! 63: ! 64: (define_insn "movstricthi" ! 65: [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "=r,r,r,o,<")) ! 66: (match_operand:HI 1 "general_operand_src" "I,r,io,r,r"))] ! 67: "" ! 68: "@ ! 69: sub.w %T0,%T0 ! 70: mov.w %T1,%T0 ! 71: mov.w %T1,%T0 ! 72: mov.w %T1,%T0 ! 73: mov.w %T1,%T0" ! 74: [(set_attr "type" "move") ! 75: (set_attr "length" "2,2,4,4,2") ! 76: (set_attr "cc" "set")]) ! 77: ! 78: (define_insn "" ! 79: [(set (match_operand:HI 0 "general_operand_dst" "=ra,ra,ra,o,<") ! 80: (match_operand:HI 1 "general_operand_src" "I,ra,ion,ra,ra"))] ! 81: "" ! 82: "@ ! 83: sub.w %T0,%T0 ! 84: mov.w %T1,%T0 ! 85: mov.w %T1,%T0 ! 86: mov.w %T1,%T0 ! 87: mov.w %T1,%T0" ! 88: [(set_attr "type" "move") ! 89: (set_attr "length" "2,2,4,4,2") ! 90: (set_attr "cc" "set")]) ! 91: ! 92: (define_expand "movhi" ! 93: [(set (match_operand:HI 0 "general_operand_dst" "") ! 94: (match_operand:HI 1 "general_operand_src" ""))] ! 95: "" ! 96: " ! 97: { ! 98: /* One of the ops has to be in a register. */ ! 99: if (! register_operand (operand1, HImode) ! 100: && ! register_operand (operand0, HImode)) ! 101: operands[1] = copy_to_mode_reg (HImode, operand1); ! 102: }") ! 103: ! 104: (define_insn "" ! 105: [(set (match_operand:HI 0 "register_operand" "=&ra") ! 106: (plus:HI (match_operand:HI 1 "general_operand_src" "g") ! 107: (match_operand:HI 2 "register_operand" "ra")))] ! 108: "" ! 109: "mov.w %T1,%T0\;add.w %T2,%T0" ! 110: [(set_attr "type" "arith") ! 111: (set_attr "length" "6") ! 112: (set_attr "cc" "set")]) ! 113: ! 114: ;; movqi ! 115: ! 116: (define_insn "" ! 117: [(set (match_operand:QI 0 "push_operand" "=<") ! 118: (match_operand:QI 1 "register_operand" "r"))] ! 119: "" ! 120: "mov.w %T1,%T0" ! 121: [(set_attr "type" "move") ! 122: (set_attr "length" "2") ! 123: (set_attr "cc" "set")]) ! 124: ! 125: (define_insn "movstrictqi" ! 126: [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "=r,r,r,o,<")) ! 127: (match_operand:QI 1 "general_operand_src" "I,r,io,r,r"))] ! 128: "" ! 129: "@ ! 130: sub.b %X0,%X0 ! 131: mov.b %X1,%X0 ! 132: mov.b %X1,%X0 ! 133: mov.b %X1,%X0 ! 134: mov.b %X1,%X0" ! 135: [(set_attr "type" "move") ! 136: (set_attr "length" "2,2,4,4,2") ! 137: (set_attr "cc" "set")]) ! 138: ! 139: (define_insn "" ! 140: [(set (match_operand:QI 0 "general_operand_dst" "=r,r,r,o,<") ! 141: (match_operand:QI 1 "general_operand_src" "I,r,io,r,r"))] ! 142: "" ! 143: "@ ! 144: sub.b %X0,%X0 ! 145: mov.b %X1,%X0 ! 146: mov.b %X1,%X0 ! 147: mov.b %X1,%X0 ! 148: mov.b %X1,%X0" ! 149: [(set_attr "type" "move") ! 150: (set_attr "length" "2,2,4,4,2") ! 151: (set_attr "cc" "set")]) ! 152: ! 153: (define_expand "movqi" ! 154: [(set (match_operand:QI 0 "general_operand_dst" "") ! 155: (match_operand:QI 1 "general_operand_src" ""))] ! 156: "" ! 157: " ! 158: { ! 159: /* One of the ops has to be in a register. */ ! 160: if (! register_operand (operand0, QImode) ! 161: && ! register_operand (operand1, QImode)) ! 162: operands[1] = copy_to_mode_reg (QImode, operand1); ! 163: }") ! 164: ! 165: ;; movsi ! 166: ! 167: (define_insn "" ! 168: [(set (match_operand:SI 0 "general_operand_dst" "=l,l,l,o,<") ! 169: (match_operand:SI 1 "general_operand_src" "I,l,ion,l,l"))] ! 170: "" ! 171: "* ! 172: { ! 173: int rn = -1; ! 174: switch (which_alternative) ! 175: { ! 176: case 0: ! 177: return \"sub.w %e0,%e0\;sub.w %f0,%f0\"; ! 178: case 1: ! 179: return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; ! 180: case 2: ! 181: /* Make sure we don't trample the register we index with. */ ! 182: ! 183: if (GET_CODE (operands[1]) == MEM) ! 184: { ! 185: rtx inside = XEXP (operands[1], 0); ! 186: if (REG_P (inside)) ! 187: rn = REGNO (inside); ! 188: else if (GET_CODE (inside) == PLUS) ! 189: { ! 190: rtx lhs = XEXP (inside, 0); ! 191: rtx rhs = XEXP (inside, 1); ! 192: if (REG_P (lhs)) ! 193: rn = REGNO (lhs); ! 194: if (REG_P (rhs)) ! 195: rn = REGNO (rhs); ! 196: } ! 197: } ! 198: if (rn == REGNO (operands[0])) ! 199: /* Move the second word first. */ ! 200: return \"mov.w %f1,%f0\;mov.w %e1,%e0\"; ! 201: else ! 202: return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; ! 203: ! 204: case 3: ! 205: return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; ! 206: case 4: ! 207: return \"mov.w %f1,%T0\;mov.w %e1,%T0\"; ! 208: } ! 209: }" ! 210: [(set_attr "type" "move") ! 211: (set_attr "length" "4,4,8,8,4") ! 212: (set_attr "cc" "clobber")]) ! 213: ! 214: (define_insn "" ! 215: [(set (match_operand:SI 0 "push_operand" "=<") ! 216: (match_operand:SI 1 "register_operand" "l"))] ! 217: "" ! 218: "mov.w %f1,%T0\;mov.w %e1,%T0" ! 219: [(set_attr "type" "move") ! 220: (set_attr "length" "4") ! 221: (set_attr "cc" "clobber")]) ! 222: ! 223: (define_expand "movsi" ! 224: [(set (match_operand:SI 0 "general_operand_dst" "") ! 225: (match_operand:SI 1 "general_operand_src" ""))] ! 226: "" ! 227: "if (domovsi (operands)) DONE;") ! 228: ! 229: (define_insn "" ! 230: [(set (match_operand:SF 0 "general_operand_dst" "=l,l,l,o,<") ! 231: (match_operand:SF 1 "general_operand_src" "I,l,ion,l,l"))] ! 232: "" ! 233: "* ! 234: { ! 235: /* This is a copy of the movsi stuff. */ ! 236: int rn = -1; ! 237: switch (which_alternative) ! 238: { ! 239: case 0: ! 240: return \"sub.w %e0,%e0\;sub.w %f0,%f0\"; ! 241: case 1: ! 242: return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; ! 243: case 2: ! 244: /* Make sure we don't trample the register we index with. */ ! 245: ! 246: if (GET_CODE (operands[1]) == MEM) ! 247: { ! 248: rtx inside = XEXP (operands[1], 0); ! 249: if (REG_P (inside)) ! 250: rn = REGNO (inside); ! 251: else if (GET_CODE (inside) == PLUS) ! 252: { ! 253: rtx lhs = XEXP (inside, 0); ! 254: rtx rhs = XEXP (inside, 1); ! 255: if (REG_P (lhs)) ! 256: rn = REGNO (lhs); ! 257: if (REG_P (rhs)) ! 258: rn = REGNO (rhs); ! 259: } ! 260: } ! 261: if (rn == REGNO (operands[0])) ! 262: /* Move the second word first. */ ! 263: return \"mov.w %f1,%f0\;mov.w %e1,%e0\"; ! 264: else ! 265: return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; ! 266: ! 267: case 3: ! 268: return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; ! 269: case 4: ! 270: return \"mov.w %f1,%T0\;mov.w %e1,%T0\"; ! 271: } ! 272: }" ! 273: [(set_attr "type" "move") ! 274: (set_attr "length" "4,4,8,8,4") ! 275: (set_attr "cc" "clobber")]) ! 276: ! 277: (define_insn "" ! 278: [(set (match_operand:SF 0 "push_operand" "=<") ! 279: (match_operand:SF 1 "register_operand" "l"))] ! 280: "" ! 281: "mov.w %f1,%T0\;mov.w %e1,%T0" ! 282: [(set_attr "type" "move") ! 283: (set_attr "length" "4") ! 284: (set_attr "cc" "clobber")]) ! 285: ! 286: (define_expand "movsf" ! 287: [(set (match_operand:SF 0 "general_operand_dst" "") ! 288: (match_operand:SF 1 "general_operand_src" ""))] ! 289: "" ! 290: "if (domovsi (operands)) DONE;") ! 291: ! 292: ;; Block move ! 293: ! 294: (define_expand "movstrhi" ! 295: [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" "")) ! 296: (mem:BLK (match_operand:BLK 1 "general_operand" ""))) ! 297: (use (match_operand:HI 2 "general_operand" "")) ! 298: (use (match_operand:HI 3 "immediate_operand" "")) ! 299: (clobber (match_dup 3)) ! 300: ])] ! 301: "" ! 302: " ! 303: { ! 304: rtx src_ptr = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); ! 305: rtx dst_ptr = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); ! 306: ! 307: enum machine_mode mode = INTVAL (operands[3]) >=2 ? HImode : QImode; ! 308: rtx tmpreg = gen_reg_rtx (mode); ! 309: rtx increment = mode == QImode ? const1_rtx : const2_rtx; ! 310: rtx length = operands[2]; ! 311: rtx label = gen_label_rtx (); ! 312: rtx end_src_ptr = gen_reg_rtx (Pmode); ! 313: ! 314: emit_insn (gen_rtx (SET, VOIDmode, end_src_ptr, ! 315: gen_rtx (PLUS, Pmode, src_ptr, length))); ! 316: ! 317: emit_label (label); ! 318: emit_move_insn (tmpreg, gen_rtx (MEM, mode, src_ptr)); ! 319: emit_move_insn (gen_rtx (MEM, mode, dst_ptr), tmpreg); ! 320: emit_insn (gen_rtx (SET, VOIDmode, src_ptr, ! 321: gen_rtx (PLUS, Pmode, src_ptr, increment))); ! 322: emit_insn (gen_rtx (SET, VOIDmode, dst_ptr, ! 323: gen_rtx (PLUS, Pmode, dst_ptr, increment))); ! 324: ! 325: emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, ! 326: gen_rtx (COMPARE, HImode, src_ptr, end_src_ptr))); ! 327: emit_jump_insn (gen_bne (label)); ! 328: ! 329: DONE; ! 330: } ! 331: ") ! 332: ! 333: ;; ---------------------------------------------------------------------- ! 334: ;; Test instructions ! 335: ;; ---------------------------------------------------------------------- ! 336: ! 337: (define_insn "tstqi" ! 338: [(set (cc0) ! 339: (match_operand:QI 0 "register_operand" "ra"))] ! 340: "" ! 341: "cmp.b #0,%X0" ! 342: [(set_attr "type" "arith") ! 343: (set_attr "length" "2") ! 344: (set_attr "cc" "set")]) ! 345: ! 346: (define_insn "tsthi" ! 347: [(set (cc0) ! 348: (match_operand:HI 0 "register_operand" "ra"))] ! 349: "" ! 350: "mov.w %T0,%T0" ! 351: [(set_attr "type" "arith") ! 352: (set_attr "length" "2") ! 353: (set_attr "cc" "set")]) ! 354: ! 355: (define_insn "cmphi" ! 356: [(set (cc0) ! 357: (compare:HI (match_operand:HI 0 "register_operand" "ra") ! 358: (match_operand:HI 1 "register_operand" "ra")))] ! 359: "" ! 360: "cmp.w %T1,%T0" ! 361: [(set_attr "type" "arith") ! 362: (set_attr "length" "2") ! 363: (set_attr "cc" "compare")]) ! 364: ! 365: (define_insn "cmpqi" ! 366: [(set (cc0) ! 367: (compare:QI (match_operand:QI 0 "register_operand" "ra") ! 368: (match_operand:QI 1 "nonmemory_operand" "rai")))] ! 369: "" ! 370: "cmp.b %X1,%X0" ! 371: [(set_attr "type" "arith") ! 372: (set_attr "length" "2") ! 373: (set_attr "cc" "compare")]) ! 374: ! 375: ;; ---------------------------------------------------------------------- ! 376: ;; Add instructions ! 377: ;; ---------------------------------------------------------------------- ! 378: ! 379: (define_insn "" ! 380: [(set (match_operand:HI 0 "register_operand" "=ra,ra,ra,ra,r,ra") ! 381: (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0") ! 382: (match_operand:HI 2 "nonmemory_operand" "K,M,L,N,n,ra")))] ! 383: "" ! 384: "@ ! 385: adds %T2,%T0 ! 386: adds #2,%T0\;adds %C2,%T0 ! 387: subs %M2,%T0 ! 388: subs #2,%T0\;subs %M2,%T0 ! 389: add.b %s2,%s0\;addx %t2,%t0 ! 390: add.w %T2,%T0" ! 391: [(set_attr "type" "multi,multi,multi,multi,multi,arith") ! 392: (set_attr "length" "2,4,2,4,4,2") ! 393: (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,clobber,set")]) ! 394: ! 395: (define_expand "addhi3" ! 396: [(set (match_operand:HI 0 "register_operand" "") ! 397: (plus:HI (match_operand:HI 1 "register_operand" "") ! 398: (match_operand:HI 2 "nonmemory_operand" "")))] ! 399: "" ! 400: " ! 401: { ! 402: if (operands[0] != operands[1]) ! 403: emit_move_insn (operands[0], operands[1]); ! 404: }") ! 405: ! 406: (define_insn "addqi3" ! 407: [(set (match_operand:QI 0 "register_operand" "=r") ! 408: (plus:QI (match_operand:QI 1 "register_operand" "%0") ! 409: (match_operand:QI 2 "nonmemory_operand" "ri")))] ! 410: "" ! 411: "add.b %X2,%X0" ! 412: [(set_attr "type" "arith") ! 413: (set_attr "length" "2") ! 414: (set_attr "cc" "set")]) ! 415: ! 416: (define_insn "" ! 417: [(set (match_operand:SI 0 "register_operand" "=l,l") ! 418: (plus:SI (match_operand:SI 1 "register_operand" "%0,0") ! 419: (match_operand:SI 2 "nonmemory_operand" "l,n"))) ! 420: (clobber (match_operand:HI 3 "register_operand" "=&l,l"))] ! 421: "" ! 422: "@ ! 423: add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0 ! 424: add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0" ! 425: [(set_attr "type" "multi") ! 426: (set_attr "length" "8,6") ! 427: (set_attr "cc" "clobber")]) ! 428: ! 429: (define_insn "" ! 430: [(set (match_operand:SI 0 "register_operand" "=l,l") ! 431: (plus:SI (match_operand:SI 1 "register_operand" "%0,0") ! 432: (match_operand:SI 2 "nonmemory_operand" "n,r")))] ! 433: "" ! 434: "@ ! 435: add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0 ! 436: add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0" ! 437: [(set_attr "type" "arith") ! 438: (set_attr "length" "8,6") ! 439: (set_attr "cc" "clobber")]) ! 440: ! 441: (define_expand "addsi3" ! 442: [(set (match_dup 3) (match_operand:SI 1 "register_operand" "")) ! 443: (set (match_dup 3) ! 444: (plus:SI (match_dup 3) ! 445: (match_operand:SI 2 "nonmemory_operand" ""))) ! 446: (set (match_operand:SI 0 "register_operand" "") (match_dup 3))] ! 447: "" ! 448: " ! 449: { ! 450: operands[3] = gen_rtx (REG, SImode, 0); ! 451: }") ! 452: ! 453: ;; ----------------------------------------------------------------------; ! 454: ;; Subtract instructions ! 455: ;; ---------------------------------------------------------------------- ! 456: ! 457: (define_insn "" ! 458: [(set (match_operand:HI 0 "register_operand" "=ra,ra,ra,r") ! 459: (minus:HI (match_operand:HI 1 "general_operand" "0,0,0,0") ! 460: (match_operand:HI 2 "nonmemory_operand" "K,M,ra,n")))] ! 461: "" ! 462: "@ ! 463: subs %T2,%T0 ! 464: subs #2,%T0\;subs %E2,%T0 ! 465: sub.w %T2,%T0 ! 466: add.b %E2,%s0\;addx %F2,%t0 ; -%0" ! 467: [(set_attr "type" "multi") ! 468: (set_attr "length" "2,4,2,4") ! 469: (set_attr "cc" "none_0hit,none_0hit,set,clobber")]) ! 470: ! 471: (define_insn "subqi3" ! 472: [(set (match_operand:QI 0 "register_operand" "=r,r") ! 473: (minus:QI (match_operand:QI 1 "register_operand" "0,0") ! 474: (match_operand:QI 2 "nonmemory_operand" "r,i")))] ! 475: "" ! 476: "@ ! 477: sub.b %X2,%X0 ! 478: add.b %G2,%X0" ! 479: [(set_attr "type" "arith") ! 480: (set_attr "length" "2") ! 481: (set_attr "cc" "set")]) ! 482: ! 483: (define_expand "subhi3" ! 484: [(set (match_operand:HI 0 "register_operand" "") ! 485: (minus:HI (match_operand:HI 1 "register_operand" "") ! 486: (match_operand:HI 2 "nonmemory_operand" "")))] ! 487: "" ! 488: " ! 489: { ! 490: if (operands[0] != operands[1]) ! 491: emit_move_insn (operands[0], operands[1]); ! 492: }") ! 493: ! 494: (define_insn "" ! 495: [(set (match_operand:SI 0 "register_operand" "=l") ! 496: (minus:SI (match_operand:SI 1 "register_operand" "%0") ! 497: (match_operand:SI 2 "register_operand" "l")))] ! 498: "" ! 499: "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0" ! 500: [(set_attr "type" "arith") ! 501: (set_attr "length" "6") ! 502: (set_attr "cc" "clobber")]) ! 503: ! 504: (define_expand "subsi3" ! 505: [(set (match_dup 3) (match_operand:SI 1 "register_operand" "")) ! 506: (set (match_dup 3) ! 507: (minus:SI (match_dup 3) ! 508: (match_operand:SI 2 "nonmemory_operand" ""))) ! 509: (set (match_operand:SI 0 "register_operand" "") (match_dup 3))] ! 510: "" ! 511: "operands[3] = gen_rtx (REG, SImode, 0);") ! 512: ! 513: ;; ---------------------------------------------------------------------- ! 514: ;; Multiply instruction ! 515: ;; ---------------------------------------------------------------------- ! 516: ! 517: (define_insn "umulqihi3" ! 518: [(set (match_operand:HI 0 "register_operand" "=r") ! 519: (mult:HI (match_operand:QI 1 "general_operand" "%0") ! 520: (match_operand:QI 2 "register_operand" "r")))] ! 521: "" ! 522: "mulxu %X2,%T0" ! 523: [(set_attr "type" "multi") ! 524: (set_attr "length" "2") ! 525: (set_attr "cc" "none_0hit")]) ! 526: ! 527: ;; ---------------------------------------------------------------------- ! 528: ;; Divide instructions ! 529: ;; ---------------------------------------------------------------------- ! 530: ! 531: (define_insn "udivqi3" ! 532: [(set (match_operand:QI 0 "register_operand" "=r") ! 533: (udiv:QI (match_operand:HI 1 "general_operand" "0") ! 534: (match_operand:QI 2 "register_operand" "r")))] ! 535: "" ! 536: "divxu %X2,%T0" ! 537: [(set_attr "type" "multi") ! 538: (set_attr "length" "2") ! 539: (set_attr "cc" "clobber")]) ! 540: ! 541: (define_insn "divqi3" ! 542: [(set (match_operand:QI 0 "register_operand" "=r") ! 543: (div:QI (match_operand:HI 1 "general_operand" "0") ! 544: (match_operand:QI 2 "register_operand" "r")))] ! 545: "" ! 546: "divxu %X2,%T0" ! 547: [(set_attr "type" "multi") ! 548: (set_attr "length" "2") ! 549: (set_attr "cc" "clobber")]) ! 550: ! 551: ;; ---------------------------------------------------------------------- ! 552: ;; And instructions ! 553: ;; ---------------------------------------------------------------------- ! 554: ! 555: (define_insn "andqi3" ! 556: [(set (match_operand:QI 0 "general_operand" "=r") ! 557: (and:QI (match_operand:QI 1 "general_operand" "%0") ! 558: (match_operand:QI 2 "general_operand" "rn")))] ! 559: "" ! 560: "and %X2,%X0" ! 561: [(set_attr "type" "arith") ! 562: (set_attr "length" "2") ! 563: (set_attr "cc" "set")]) ! 564: ! 565: (define_insn "andhi3" ! 566: [(set (match_operand:HI 0 "register_operand" "=r") ! 567: (and:HI (match_operand:HI 1 "register_operand" "%0") ! 568: (match_operand:HI 2 "general_operand" "ri")))] ! 569: "" ! 570: "and %s2,%s0\;and %t2,%t0" ! 571: [(set_attr "type" "multi") ! 572: (set_attr "length" "4") ! 573: (set_attr "cc" "clobber")]) ! 574: ! 575: ;; ---------------------------------------------------------------------- ! 576: ;; Or instructions ! 577: ;; ---------------------------------------------------------------------- ! 578: ! 579: (define_insn "iorqi3" ! 580: [(set (match_operand:QI 0 "general_operand" "=r,U") ! 581: (ior:QI (match_operand:QI 1 "general_operand" "%0,0") ! 582: (match_operand:QI 2 "general_operand" "rn,P")))] ! 583: "" ! 584: "@ ! 585: or %X2,%X0 ! 586: bset %V2,%X0" ! 587: [(set_attr "type" "arith") ! 588: (set_attr "length" "2,4") ! 589: (set_attr "cc" "set,none_0hit")]) ! 590: ! 591: (define_insn "iorhi3" ! 592: [(set (match_operand:HI 0 "general_operand" "=r,r") ! 593: (ior:HI (match_operand:HI 1 "general_operand" "%0,0") ! 594: (match_operand:HI 2 "general_operand" "J,ri")))] ! 595: "" ! 596: "@ ! 597: or %s2,%s0 ! 598: or %s2,%s0\;or %t2,%t0" ! 599: [(set_attr "type" "multi") ! 600: (set_attr "length" "2,4") ! 601: (set_attr "cc" "clobber,clobber")]) ! 602: ! 603: ;; ---------------------------------------------------------------------- ! 604: ;; Xor instructions ! 605: ;; ---------------------------------------------------------------------- ! 606: ! 607: (define_insn "xorqi3" ! 608: [(set (match_operand:QI 0 "general_operand" "=r") ! 609: (xor:QI (match_operand:QI 1 "general_operand" "%0") ! 610: (match_operand:QI 2 "nonmemory_operand" "ri")))] ! 611: "" ! 612: "xor %X2,%X0" ! 613: [(set_attr "type" "arith") ! 614: (set_attr "length" "2") ! 615: (set_attr "cc" "set")]) ! 616: ! 617: (define_insn "xorhi3" ! 618: [(set (match_operand:HI 0 "general_operand" "=r") ! 619: (xor:HI (match_operand:HI 1 "general_operand" "%0") ! 620: (match_operand:HI 2 "nonmemory_operand" "ri")))] ! 621: "" ! 622: "xor %s2,%s0\;xor %t2,%t0" ! 623: [(set_attr "type" "multi") ! 624: (set_attr "length" "4") ! 625: (set_attr "cc" "clobber")]) ! 626: ! 627: ;; ---------------------------------------------------------------------- ! 628: ;; Negation instructions ! 629: ;; ---------------------------------------------------------------------- ! 630: ! 631: (define_insn "negqi2" ! 632: [(set (match_operand:QI 0 "register_operand" "=r") ! 633: (neg:QI (match_operand:QI 1 "general_operand" "0")))] ! 634: "" ! 635: "neg %X0" ! 636: [(set_attr "type" "arith") ! 637: (set_attr "length" "2") ! 638: (set_attr "cc" "set")]) ! 639: ! 640: (define_expand "neghi2" ! 641: [(set (match_dup 2) ! 642: (not:HI (match_operand:HI 1 "register_operand" "r"))) ! 643: (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1))) ! 644: (set (match_operand:HI 0 "register_operand" "=r") ! 645: (match_dup 2))] ! 646: "" ! 647: "operands[2] = gen_reg_rtx (HImode);") ! 648: ! 649: (define_expand "negsi2" ! 650: [(set (match_dup 2) ! 651: (not:SI (match_operand:SI 1 "register_operand" "r"))) ! 652: (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1))) ! 653: (set (match_operand:SI 0 "register_operand" "=r") ! 654: (match_dup 2))] ! 655: "" ! 656: "operands[2] = gen_reg_rtx (SImode);") ! 657: ! 658: ;; ---------------------------------------------------------------------- ! 659: ;; Not instructions ! 660: ;; ---------------------------------------------------------------------- ! 661: ! 662: (define_insn "one_cmplqi2" ! 663: [(set (match_operand:QI 0 "register_operand" "=r") ! 664: (not:QI (match_operand:QI 1 "general_operand" "0")))] ! 665: "" ! 666: "not %X0" ! 667: [(set_attr "type" "arith") ! 668: (set_attr "length" "2") ! 669: (set_attr "cc" "set")]) ! 670: ! 671: (define_insn "one_cmplhi2" ! 672: [(set (match_operand:HI 0 "register_operand" "=r") ! 673: (not:HI (match_operand:HI 1 "general_operand" "0")))] ! 674: "" ! 675: "not %s0\;not %t0" ! 676: [(set_attr "type" "arith") ! 677: (set_attr "length" "4") ! 678: (set_attr "cc" "clobber")]) ! 679: ! 680: (define_insn "one_cmplsi2" ! 681: [(set (match_operand:SI 0 "register_operand" "=r") ! 682: (not:SI (match_operand:SI 1 "general_operand" "0")))] ! 683: "" ! 684: "not %w0\;not %x0\;not %y0\;not %z0" ! 685: [(set_attr "type" "arith") ! 686: (set_attr "length" "8") ! 687: (set_attr "cc" "clobber")]) ! 688: ! 689: ;; ---------------------------------------------------------------------- ! 690: ;; Conditional branches ! 691: ;; ---------------------------------------------------------------------- ! 692: ! 693: (define_expand "ble" ! 694: [(set (pc) ! 695: (if_then_else (le (cc0) ! 696: (const_int 0)) ! 697: (label_ref (match_operand 0 "" "")) ! 698: (pc)))] ! 699: "" ! 700: "") ! 701: ! 702: (define_expand "bleu" ! 703: [(set (pc) ! 704: (if_then_else (leu (cc0) ! 705: (const_int 0)) ! 706: (label_ref (match_operand 0 "" "")) ! 707: (pc)))] ! 708: "" ! 709: "") ! 710: ! 711: (define_expand "bge" ! 712: [(set (pc) ! 713: (if_then_else (ge (cc0) ! 714: (const_int 0)) ! 715: (label_ref (match_operand 0 "" "")) ! 716: (pc)))] ! 717: "" ! 718: "") ! 719: ! 720: (define_expand "bgeu" ! 721: [(set (pc) ! 722: (if_then_else (geu (cc0) ! 723: (const_int 0)) ! 724: (label_ref (match_operand 0 "" "")) ! 725: (pc)))] ! 726: "" ! 727: "") ! 728: ! 729: (define_expand "blt" ! 730: [(set (pc) ! 731: (if_then_else (lt (cc0) ! 732: (const_int 0)) ! 733: (label_ref (match_operand 0 "" "")) ! 734: (pc)))] ! 735: "" ! 736: "") ! 737: ! 738: (define_expand "bltu" ! 739: [(set (pc) ! 740: (if_then_else (ltu (cc0) ! 741: (const_int 0)) ! 742: (label_ref (match_operand 0 "" "")) ! 743: (pc)))] ! 744: "" ! 745: "") ! 746: ! 747: (define_expand "bgt" ! 748: [(set (pc) ! 749: (if_then_else (gt (cc0) ! 750: (const_int 0)) ! 751: (label_ref (match_operand 0 "" "")) ! 752: (pc)))] ! 753: "" ! 754: "") ! 755: ! 756: (define_expand "bgtu" ! 757: [(set (pc) ! 758: (if_then_else (gtu (cc0) ! 759: (const_int 0)) ! 760: (label_ref (match_operand 0 "" "")) ! 761: (pc)))] ! 762: "" ! 763: "") ! 764: ! 765: (define_expand "beq" ! 766: [(set (pc) ! 767: (if_then_else (eq (cc0) ! 768: (const_int 0)) ! 769: (label_ref (match_operand 0 "" "")) ! 770: (pc)))] ! 771: "" ! 772: "") ! 773: ! 774: (define_expand "bne" ! 775: [(set (pc) ! 776: (if_then_else (ne (cc0) ! 777: (const_int 0)) ! 778: (label_ref (match_operand 0 "" "")) ! 779: (pc)))] ! 780: "" ! 781: "") ! 782: ! 783: (define_insn "" ! 784: [(set (pc) ! 785: (if_then_else ! 786: (match_operator 1 "comparison_operator" [(cc0) (const_int 0)]) ! 787: (label_ref (match_operand 0 "" "")) ! 788: (pc)))] ! 789: "" ! 790: "* ! 791: { ! 792: if (get_attr_length (insn) == 2) ! 793: return \"b%j1 %l0\"; ! 794: else ! 795: return \"b%k1 %L0\;jmp @%l0\;%L0:\"; ! 796: }" ! 797: [(set_attr "type" "branch") ! 798: (set_attr "cc" "none")]) ! 799: ! 800: (define_insn "" ! 801: [(set (pc) ! 802: (if_then_else ! 803: (match_operator 1 "comparison_operator" [(cc0) (const_int 0)]) ! 804: (pc) ! 805: (label_ref (match_operand 0 "" ""))))] ! 806: "" ! 807: "* ! 808: { ! 809: if (get_attr_length (insn) == 2) ! 810: return \"b%k1 %l0\"; ! 811: else ! 812: return \"b%j1 %L0\;jmp @%l0\;%L0:\"; ! 813: }" ! 814: [(set_attr "type" "branch") ! 815: (set_attr "cc" "none")]) ! 816: ! 817: ;; ---------------------------------------------------------------------- ! 818: ;; Unconditional branches ! 819: ;; ---------------------------------------------------------------------- ! 820: ! 821: (define_insn "jump" ! 822: [(set (pc) ! 823: (label_ref (match_operand 0 "" "")))] ! 824: "" ! 825: "* ! 826: { ! 827: if (get_attr_length (insn) == 2) ! 828: return \"bra %l0\"; ! 829: else ! 830: return \"jmp @%l0\"; ! 831: }" ! 832: [(set_attr "type" "branch") ! 833: (set_attr "cc" "none")]) ! 834: ! 835: (define_insn "tablejump" ! 836: [(set (pc) (match_operand:HI 0 "register_operand" "")) ! 837: (use (label_ref (match_operand 1 "" "")))] ! 838: "" ! 839: "jmp @%0" ! 840: [(set_attr "type" "branch") ! 841: (set_attr "cc" "none") ! 842: (set_attr "length" "2")]) ! 843: ! 844: ;; Call subroutine with no return value. ! 845: ! 846: (define_insn "call" ! 847: [(call (match_operand:QI 0 "memory_operand" "o") ! 848: (match_operand:HI 1 "general_operand" "g"))] ! 849: "" ! 850: "jsr %0" ! 851: [(set_attr "type" "call") ! 852: (set_attr "cc" "clobber") ! 853: (set_attr "length" "4")]) ! 854: ! 855: ;; Call subroutine, returning value in operand 0 ! 856: ;; (which must be a hard register). ! 857: ! 858: (define_insn "call_value" ! 859: [(set (match_operand 0 "" "=r") ! 860: (call (match_operand:QI 1 "memory_operand" "o") ! 861: (match_operand:HI 2 "general_operand" "g")))] ! 862: "" ! 863: "jsr %1" ! 864: [(set_attr "type" "call") ! 865: (set_attr "cc" "clobber") ! 866: (set_attr "length" "4")]) ! 867: ! 868: (define_insn "nop" ! 869: [(const_int 0)] ! 870: "" ! 871: "nop" ! 872: [(set_attr "type" "multi") ! 873: (set_attr "cc" "none") ! 874: (set_attr "length" "2")]) ! 875: ! 876: (define_insn "indirect_jump" ! 877: [(set (pc) (match_operand:HI 0 "register_operand" "r"))] ! 878: "" ! 879: "jmp @%0" ! 880: [(set_attr "type" "branch") ! 881: (set_attr "cc" "none") ! 882: (set_attr "length" "2")]) ! 883: ! 884: ;; ----------------------------------------------------------------- ! 885: ;; Shifts ! 886: ;; ----------------------------------------------------------------- ! 887: ! 888: ;; All H8 shifts go one bit at a time, here they are defined with names ! 889: ;; so can use them in the expands.. ! 890: ! 891: ;; QI BIT SHIFTS ! 892: ! 893: (define_insn "ashlqi3_one" ! 894: [(set (match_operand:QI 0 "register_operand" "=r") ! 895: (ashift:QI (match_operand:QI 1 "register_operand" "0") ! 896: (const_int 1)))] ! 897: "" ! 898: "shal %X0" ! 899: [(set_attr "type" "arith") ! 900: (set_attr "length" "2") ! 901: (set_attr "cc" "set")]) ! 902: ! 903: (define_insn "ashrqi3_one" ! 904: [(set (match_operand:QI 0 "register_operand" "=r") ! 905: (ashiftrt:QI (match_operand:QI 1 "register_operand" "0") ! 906: (const_int 1)))] ! 907: "" ! 908: "shar %X0" ! 909: [(set_attr "type" "arith") ! 910: (set_attr "length" "2") ! 911: (set_attr "cc" "set")]) ! 912: ! 913: (define_insn "lshrqi3_one" ! 914: [(set (match_operand:QI 0 "register_operand" "=r") ! 915: (lshiftrt:QI (match_operand:QI 1 "register_operand" "0") ! 916: (const_int 1)))] ! 917: "" ! 918: "shlr %X0" ! 919: [(set_attr "type" "arith") ! 920: (set_attr "length" "2") ! 921: (set_attr "cc" "set")]) ! 922: ! 923: (define_expand "ashlqi3" ! 924: [(set (match_operand:QI 0 "register_operand" "=r") ! 925: (ashift:QI (match_operand:QI 1 "register_operand" "0") ! 926: (match_operand:QI 2 "nonmemory_operand" "rn")))] ! 927: "" ! 928: " ! 929: { ! 930: if (can_shift (ASHIFT, operands, gen_ashlqi3_one, 4, 0)) ! 931: DONE; ! 932: else ! 933: FAIL; ! 934: }") ! 935: ! 936: (define_expand "ashrqi3" ! 937: [(set (match_operand:QI 0 "register_operand" "=r") ! 938: (ashiftrt:QI (match_operand:QI 1 "register_operand" "0") ! 939: (match_operand:QI 2 "nonmemory_operand" "rn")))] ! 940: "" ! 941: " ! 942: { ! 943: if (can_shift (ASHIFTRT, operands, gen_ashrqi3_one, 4, 0)) ! 944: DONE; ! 945: else ! 946: FAIL; ! 947: }") ! 948: ! 949: (define_expand "lshrqi3" ! 950: [(set (match_operand:QI 0 "register_operand" "=r") ! 951: (lshiftrt:QI (match_operand:QI 1 "register_operand" "0") ! 952: (match_operand:QI 2 "nonmemory_operand" "rn")))] ! 953: "" ! 954: " ! 955: { ! 956: if (can_shift (LSHIFTRT, operands, gen_lshrqi3_one, 4, 0)) ! 957: DONE; ! 958: else ! 959: FAIL; ! 960: }") ! 961: ! 962: ;; HI BIT SHIFTS ! 963: ! 964: (define_insn "ashlhi3_one" ! 965: [(set (match_operand:HI 0 "register_operand" "=r") ! 966: (ashift:HI (match_operand:HI 1 "register_operand" "0") ! 967: (const_int 1)))] ! 968: "" ! 969: "add.w %T1,%T0" ! 970: [(set_attr "type" "multi") ! 971: (set_attr "length" "4") ! 972: (set_attr "cc" "set")]) ! 973: ! 974: (define_insn "ashlhi3_eight" ! 975: [(set (match_operand:HI 0 "register_operand" "=r") ! 976: (ashift:HI (match_operand:HI 1 "register_operand" "0") ! 977: (const_int 8)))] ! 978: "" ! 979: "mov.b %s1,%t0\;mov.b #0,%s0" ! 980: [(set_attr "type" "multi") ! 981: (set_attr "length" "4") ! 982: (set_attr "cc" "clobber")]) ! 983: ! 984: (define_expand "ashlhi3" ! 985: [(set (match_operand:HI 0 "register_operand" "") ! 986: (ashift:HI ! 987: (match_operand:HI 1 "general_operand_src" "") ! 988: (match_operand:HI 2 "nonmemory_operand" "")))] ! 989: "" ! 990: " ! 991: { ! 992: if (can_shift (ASHIFT, operands, gen_ashlhi3_one, 4, gen_ashlhi3_eight)) ! 993: DONE; ! 994: else ! 995: FAIL; ! 996: }") ! 997: ! 998: (define_insn "lshrhi3_one" ! 999: [(set (match_operand:HI 0 "register_operand" "=r") ! 1000: (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") ! 1001: (const_int 1)))] ! 1002: "" ! 1003: "shlr %t0\;rotxr %s0" ! 1004: [(set_attr "type" "multi") ! 1005: (set_attr "length" "4") ! 1006: (set_attr "cc" "clobber")]) ! 1007: ! 1008: (define_insn "lshlhi3_eight" ! 1009: [(set (match_operand:HI 0 "register_operand" "=r") ! 1010: (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") ! 1011: (const_int 8)))] ! 1012: "" ! 1013: "mov.b %t1,%s0\;mov.b #0,%t0" ! 1014: [(set_attr "type" "multi") ! 1015: (set_attr "length" "4") ! 1016: (set_attr "cc" "clobber")]) ! 1017: ! 1018: (define_expand "lshrhi3" ! 1019: [(set (match_operand:HI 0 "register_operand" "") ! 1020: (lshiftrt:HI ! 1021: (match_operand:HI 1 "general_operand_src" "") ! 1022: (match_operand:HI 2 "nonmemory_operand" "")))] ! 1023: "" ! 1024: " ! 1025: { ! 1026: if (can_shift (LSHIFTRT, operands, gen_lshrhi3_one, 4, gen_lshlhi3_eight)) ! 1027: DONE; ! 1028: else ! 1029: FAIL; ! 1030: }") ! 1031: ! 1032: (define_insn "ashrhi3_one" ! 1033: [(set (match_operand:HI 0 "register_operand" "=r") ! 1034: (ashiftrt:HI (match_operand:HI 1 "register_operand" "0") ! 1035: (const_int 1)))] ! 1036: "" ! 1037: "shar %t0\;rotxr %s0" ! 1038: [(set_attr "type" "multi") ! 1039: (set_attr "length" "4") ! 1040: (set_attr "cc" "clobber")]) ! 1041: ! 1042: ; signed shift right by 8 bits ! 1043: ; fetch the carry bit from the top, copy the byte right, subtract the ! 1044: ; top byte from itself - carry. ! 1045: ! 1046: (define_insn "ashrhi3_eight" ! 1047: [(set (match_operand:HI 0 "register_operand" "=r") ! 1048: (ashiftrt:HI (match_operand:HI 1 "register_operand" "0") ! 1049: (const_int 8)))] ! 1050: "" ! 1051: "bld #7,%t0\;mov.b %t0,%s0\;subx %t0,%t0" ! 1052: [(set_attr "type" "multi") ! 1053: (set_attr "length" "6") ! 1054: (set_attr "cc" "clobber")]) ! 1055: ! 1056: (define_expand "ashrhi3" ! 1057: [(set (match_operand:HI 0 "register_operand" "") ! 1058: (ashiftrt:HI ! 1059: (match_operand:HI 1 "general_operand_src" "") ! 1060: (match_operand:HI 2 "nonmemory_operand" "")))] ! 1061: "" ! 1062: " ! 1063: { ! 1064: if (can_shift (ASHIFTRT, operands, gen_ashrhi3_one, 4, gen_ashrhi3_eight)) ! 1065: DONE; ! 1066: else ! 1067: FAIL; ! 1068: }") ! 1069: ! 1070: ;; SI BIT SHIFTS ! 1071: ! 1072: (define_insn "ashlsi3_one" ! 1073: [(set (match_operand:SI 0 "register_operand" "=r") ! 1074: (ashift:SI (match_operand:SI 1 "register_operand" "0") ! 1075: (const_int 1)))] ! 1076: "" ! 1077: "add.w %f1,%f0\;addx %y1,%y0\;addx %z1,%z0" ! 1078: [(set_attr "type" "multi") ! 1079: (set_attr "length" "6") ! 1080: (set_attr "cc" "clobber")]) ! 1081: ! 1082: (define_expand "ashlsi3" ! 1083: [(set (match_operand:SI 0 "register_operand" "") ! 1084: (ashift:SI ! 1085: (match_operand:SI 1 "general_operand_src" "") ! 1086: (match_operand:SI 2 "nonmemory_operand" "")))] ! 1087: "" ! 1088: " ! 1089: { ! 1090: if (can_shift (ASHIFT, operands, gen_ashlsi3_one, 1, 0)) ! 1091: DONE; ! 1092: else ! 1093: FAIL; ! 1094: }") ! 1095: ! 1096: (define_insn "lshrsi3_one" ! 1097: [(set (match_operand:SI 0 "register_operand" "=r") ! 1098: (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") ! 1099: (const_int 1)))] ! 1100: "" ! 1101: "shlr %z0\;rotxr %y0\;rotxr %x0\;rotxr %w0" ! 1102: [(set_attr "type" "multi") ! 1103: (set_attr "length" "8") ! 1104: (set_attr "cc" "clobber")]) ! 1105: ! 1106: (define_expand "lshrsi3" ! 1107: [(set (match_operand:SI 0 "register_operand" "") ! 1108: (lshiftrt:SI ! 1109: (match_operand:SI 1 "general_operand_src" "") ! 1110: (match_operand:SI 2 "nonmemory_operand" "")))] ! 1111: "" ! 1112: " ! 1113: { ! 1114: if (can_shift (LSHIFTRT, operands, gen_lshrsi3_one, 1, 0)) ! 1115: DONE; ! 1116: else ! 1117: FAIL; ! 1118: }") ! 1119: ! 1120: (define_insn "ashrsi3_one" ! 1121: [(set (match_operand:SI 0 "register_operand" "=r") ! 1122: (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") ! 1123: (const_int 1)))] ! 1124: "" ! 1125: "shar %z0\;rotxr %y0\;rotxr %x0\;rotxr %w0" ! 1126: [(set_attr "type" "multi") ! 1127: (set_attr "length" "16") ! 1128: (set_attr "cc" "clobber")]) ! 1129: ! 1130: (define_expand "ashrsi3" ! 1131: [(set (match_operand:SI 0 "register_operand" "") ! 1132: (ashiftrt:SI ! 1133: (match_operand:SI 1 "general_operand_src" "") ! 1134: (match_operand:SI 2 "nonmemory_operand" "")))] ! 1135: "" ! 1136: " ! 1137: { ! 1138: if (can_shift (ASHIFTRT, operands, gen_ashrsi3_one, 1, 0)) ! 1139: DONE; ! 1140: else ! 1141: FAIL; ! 1142: }") ! 1143: ! 1144: ;; ---------------------------------------------------------------------- ! 1145: ;; BIT FIELDS ! 1146: ;; ---------------------------------------------------------------------- ! 1147: ! 1148: (define_insn "" ! 1149: [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r") ! 1150: (const_int 1) ! 1151: (match_operand:HI 2 "general_operand" "g")) ! 1152: (match_operand:HI 3 "general_operand" "r"))] ! 1153: "" ! 1154: "bld #0,%3l\;bst %Z2,%0%Y1" ! 1155: [(set_attr "type" "multi") ! 1156: (set_attr "length" "4") ! 1157: (set_attr "cc" "clobber")]) ! 1158: ! 1159: (define_expand "insv" ! 1160: [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r") ! 1161: (match_operand:HI 1 "general_operand" "g") ! 1162: (match_operand:HI 2 "general_operand" "g")) ! 1163: (match_operand:HI 3 "general_operand" "r"))] ! 1164: "" ! 1165: "if (INTVAL (operands[1]) != 1) FAIL;") ! 1166: ! 1167: (define_insn "" ! 1168: [(set (match_operand:HI 0 "register_operand" "=&r") ! 1169: (zero_extract:HI (match_operand:HI 1 "register_operand" "r") ! 1170: (const_int 1) ! 1171: (match_operand:HI 3 "general_operand" "g")))] ! 1172: "" ! 1173: "sub.w %T0,%T0\;bld %Z3,%T1%Y1\;rotxl %T0l" ! 1174: [(set_attr "type" "multi") ! 1175: (set_attr "length" "6") ! 1176: (set_attr "cc" "clobber")]) ! 1177: ! 1178: (define_insn "" ! 1179: [(set (match_operand:HI 0 "register_operand" "=r") ! 1180: (sign_extract:HI (match_operand:HI 1 "register_operand" "r") ! 1181: (const_int 1) ! 1182: (match_operand:HI 3 "general_operand" "g")))] ! 1183: "" ! 1184: "bld %Z3,%1%Y1\;sub.x %0l,%0l\;mov.b %0l,%0h" ! 1185: [(set_attr "type" "multi") ! 1186: (set_attr "length" "6") ! 1187: (set_attr "cc" "clobber")]) ! 1188: ! 1189: (define_expand "extzv" ! 1190: [(set (match_operand:HI 0 "register_operand" "") ! 1191: (zero_extract:HI (match_operand:HI 1 "register_operand" "") ! 1192: (match_operand:HI 2 "general_operand" "") ! 1193: (match_operand:HI 3 "general_operand" "")))] ! 1194: "" ! 1195: "if (INTVAL (operands[2]) != 1) FAIL;") ! 1196: ! 1197: (define_expand "extv" ! 1198: [(set (match_operand:HI 0 "register_operand" "") ! 1199: (sign_extract:HI (match_operand:HI 1 "register_operand" "") ! 1200: (match_operand:HI 2 "general_operand" "") ! 1201: (match_operand:HI 3 "immediate_operand" "")))] ! 1202: "" ! 1203: "if (INTVAL (operands[2]) != 1) FAIL;") ! 1204: ! 1205: ;; ---------------------------------------------------------------------- ! 1206: ;; Conversions ! 1207: ;; ---------------------------------------------------------------------- ! 1208: ! 1209: (define_insn "zero_extendqihi2" ! 1210: [(set (match_operand:HI 0 "register_operand" "=r") ! 1211: (zero_extend:HI ! 1212: (match_operand:QI 1 "general_operand" "g")))] ! 1213: "" ! 1214: "mov.b %X1,%s0\;mov.b #0,%t0" ! 1215: [(set_attr "type" "multi") ! 1216: (set_attr "length" "4") ! 1217: (set_attr "cc" "clobber")]) ! 1218: ! 1219: (define_insn "extendqihi2" ! 1220: [(set (match_operand:HI 0 "register_operand" "=r") ! 1221: (sign_extend:HI ! 1222: (match_operand:QI 1 "register_operand" "r")))] ! 1223: "" ! 1224: "* ! 1225: { ! 1226: if (REGNO (operands[1]) != REGNO (operands[0])) ! 1227: return \"mov.b %X1,%s0\;bld #7,%s0\;subx %t0,%t0\"; ! 1228: else ! 1229: return \"bld #7,%s0\;subx %t0,%t0\"; ! 1230: }" ! 1231: [(set_attr "type" "multi") ! 1232: (set_attr "length" "6") ! 1233: (set_attr "cc" "clobber")]) ! 1234: ! 1235: (define_insn "extendhisi2_one" ! 1236: [(set (match_operand:SI 0 "register_operand" "=l") ! 1237: (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))] ! 1238: "" ! 1239: "mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0" ! 1240: [(set_attr "length" "10") ! 1241: (set_attr "cc" "clobber")]) ! 1242: ! 1243: (define_expand "extendhisi2" ! 1244: [(set (reg:HI 1) (match_operand:HI 1 "general_operand" "")) ! 1245: (set (reg:SI 0) (sign_extend:SI (reg:HI 1))) ! 1246: (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))] ! 1247: "" ! 1248: "") ! 1249: ! 1250: ;; ---------------------------------------------------------------------- ! 1251: ;; peepholes ! 1252: ;; ---------------------------------------------------------------------- ! 1253: ! 1254: ;; notice a move which could be predecremented ! 1255: ! 1256: (define_peephole ! 1257: [(set (match_operand:HI 1 "register_operand" "") ! 1258: (plus:HI (match_dup 1) (const_int -1))) ! 1259: (set (mem:HI (match_dup 1)) ! 1260: (match_operand:HI 0 "register_operand" ""))] ! 1261: "REGNO (operands[1]) != REGNO (operands[0])" ! 1262: "mov.w %T0,@-%T1" ! 1263: [(set_attr "length" "2") ! 1264: (set_attr "cc" "set")]) ! 1265: ! 1266: (define_peephole ! 1267: [(set (match_operand:HI 1 "register_operand" "") ! 1268: (plus:HI (match_dup 1) (const_int -1))) ! 1269: (set (mem:QI (match_dup 1)) ! 1270: (match_operand:QI 0 "register_operand" ""))] ! 1271: "REGNO (operands[1]) != REGNO (operands[0])" ! 1272: "mov.b %X0,@-%T1" ! 1273: [(set_attr "length" "2") ! 1274: (set_attr "cc" "set")]) ! 1275: ! 1276: ;; notice a move which could be post incremented ! 1277: ! 1278: (define_peephole ! 1279: [(set (match_operand:HI 0 "register_operand" "") ! 1280: (mem:HI (match_operand:HI 1 "register_operand" ""))) ! 1281: (set (match_dup 1) (plus:HI (match_dup 1) (const_int 2)))] ! 1282: "REGNO (operands[1]) != REGNO (operands[0])" ! 1283: "mov.w @%T1+,%T0" ! 1284: [(set_attr "length" "2") ! 1285: (set_attr "cc" "set")]) ! 1286: ! 1287: (define_peephole ! 1288: [(set (match_operand:QI 0 "register_operand" "") ! 1289: (mem:QI (match_operand:HI 1 "register_operand" ""))) ! 1290: (set (match_dup 1) (plus:HI (match_dup 1) (const_int 1)))] ! 1291: "REGNO (operands[1]) != REGNO (operands[0])" ! 1292: "mov.b @%T1+,%X0" ! 1293: [(set_attr "length" "2") ! 1294: (set_attr "cc" "set")]) ! 1295: ! 1296: ;; notice when two byte moves in a row could be a word move ! 1297: ! 1298: (define_peephole ! 1299: [(set (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "ra") ! 1300: (match_operand:HI 2 "immediate_operand" "n"))) ! 1301: (match_operand:QI 0 "register_operand" "r")) ! 1302: (set (mem:QI (plus:HI (match_dup 1) ! 1303: (match_operand:HI 4 "immediate_operand" "n"))) ! 1304: (match_operand:QI 3 "register_operand" "r"))] ! 1305: "(INTVAL (operands[2]) == INTVAL (operands[4]) + 1) ! 1306: && (REGNO (operands[0]) + 1 == REGNO (operands[3]))" ! 1307: "mov.w %T0,@(%u4,%T1)" ! 1308: [(set_attr "length" "6") ! 1309: (set_attr "cc" "set")]) ! 1310: ! 1311: (define_peephole ! 1312: [(set (match_operand:QI 0 "register_operand" "=r") ! 1313: (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "ra") ! 1314: (match_operand:HI 2 "immediate_operand" "n")))) ! 1315: (set (match_operand:QI 3 "register_operand" "=r") ! 1316: (mem:QI (plus:HI (match_dup 1) ! 1317: (match_operand:HI 4 "immediate_operand" "n"))))] ! 1318: "(INTVAL (operands[2]) == INTVAL (operands[4]) + 1) ! 1319: && (REGNO (operands[0]) + 1 == REGNO (operands[3]))" ! 1320: "mov.w @(%u4,%T1),%T0" ! 1321: [(set_attr "length" "6") ! 1322: (set_attr "cc" "set")])
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