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1.1 ! root 1: ;;- Machine description for GNU compiler -- System/370 version. ! 2: ;; Copyright (C) 1989, 1993 Free Software Foundation, Inc. ! 3: ;; Contributed by Jan Stein ([email protected]). ! 4: ;; Modifed for MVS C/370 by Dave Pitts ([email protected]) ! 5: ! 6: ;; This file is part of GNU CC. ! 7: ! 8: ;; GNU CC is free software; you can redistribute it and/or modify ! 9: ;; it under the terms of the GNU General Public License as published by ! 10: ;; the Free Software Foundation; either version 2, or (at your option) ! 11: ;; any later version. ! 12: ! 13: ;; GNU CC is distributed in the hope that it will be useful, ! 14: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ! 15: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 16: ;; GNU General Public License for more details. ! 17: ! 18: ;; You should have received a copy of the GNU General Public License ! 19: ;; along with GNU CC; see the file COPYING. If not, write to ! 20: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! 21: ! 22: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code ! 23: ;;- updates for most instructions. ! 24: ! 25: ;; ! 26: ;; Special constraints for 370 machine description: ! 27: ;; ! 28: ;; a -- Any address register from 1 to 15. ! 29: ;; d -- Any register from 0 to 15. ! 30: ;; I -- An 8-bit constant (0..255). ! 31: ;; J -- A 12-bit constant (0..4095). ! 32: ;; K -- A 16-bit constant (-32768..32767). ! 33: ;; ! 34: ;; Special formats used for outputting 370 instructions. ! 35: ;; ! 36: ;; %B -- Print a constant byte integer. ! 37: ;; %H -- Print a signed 16-bit constant. ! 38: ;; %L -- Print least significant word of a CONST_DOUBLE. ! 39: ;; %M -- Print most significant word of a CONST_DOUBLE. ! 40: ;; %N -- Print next register (second word of a DImode reg). ! 41: ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)). ! 42: ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)). ! 43: ;; %X -- Print a constant byte integer in hex. ! 44: ;; ! 45: ;; We have a special contraint for pattern matching. ! 46: ;; ! 47: ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. ! 48: ;; ! 49: ;; r_or_s_operand -- Matches a register or a valid S operand in a RS, SI ! 50: ;; or SS type instruction or a register ! 51: ;; ! 52: ;; For MVS C/370 we use the following stack locations for: ! 53: ;; ! 54: ;; 136 - internal function result buffer ! 55: ;; 140 - numeric conversion buffer ! 56: ;; 144 - pointer to internal function result buffer ! 57: ;; 148 - start of automatic variables and function arguments ! 58: ;; ! 59: ;; To support programs larger than a page, 4096 bytes, PAGE_REGISTER points ! 60: ;; to a page origin table, all internal labels are generated to reload the ! 61: ;; BASE_REGISTER knowing what page it is on and all branch instructions go ! 62: ;; directly to the target if it is known that the target is on the current ! 63: ;; page (essentially backward references). All forward references and off ! 64: ;; page references are handled by loading the address of target into a ! 65: ;; register and branching indirectly. ! 66: ;; ! 67: ;; Some *di patterns have been commented out per advice from RMS, as gcc ! 68: ;; will generate the right things to do. ! 69: ;; ! 70: ! 71: ;; ! 72: ;;- Test instructions. ! 73: ;; ! 74: ! 75: ; ! 76: ; tstdi instruction pattern(s). ! 77: ; ! 78: ! 79: (define_insn "tstdi" ! 80: [(set (cc0) ! 81: (match_operand:DI 0 "register_operand" "d"))] ! 82: "" ! 83: "* ! 84: { ! 85: check_label_emit (); ! 86: mvs_check_page (0, 4, 0); ! 87: return \"SRDA %0,0\"; ! 88: }") ! 89: ! 90: ; ! 91: ; tstsi instruction pattern(s). ! 92: ; ! 93: ! 94: (define_insn "tstsi" ! 95: [(set (cc0) ! 96: (match_operand:SI 0 "register_operand" "d"))] ! 97: "" ! 98: "* ! 99: { ! 100: check_label_emit (); ! 101: mvs_check_page (0, 2, 0); ! 102: return \"LTR %0,%0\"; ! 103: }") ! 104: ! 105: ; ! 106: ; tsthi instruction pattern(s). ! 107: ; ! 108: ! 109: (define_insn "tsthi" ! 110: [(set (cc0) ! 111: (match_operand:HI 0 "register_operand" "d"))] ! 112: "" ! 113: "* ! 114: { ! 115: check_label_emit (); ! 116: mvs_check_page (0, 4, 2); ! 117: return \"CH %0,=H'0'\"; ! 118: }") ! 119: ! 120: ; ! 121: ; tstqi instruction pattern(s). ! 122: ; ! 123: ! 124: (define_insn "" ! 125: [(set (cc0) ! 126: (match_operand:QI 0 "r_or_s_operand" "dm"))] ! 127: "unsigned_jump_follows_p (insn)" ! 128: "* ! 129: { ! 130: check_label_emit (); ! 131: if (REG_P (operands[0])) ! 132: { ! 133: mvs_check_page (0, 4, 4); ! 134: return \"N %0,=X'000000FF'\"; ! 135: } ! 136: mvs_check_page (0, 4, 0); ! 137: return \"CLI %0,0\"; ! 138: }") ! 139: ! 140: (define_insn "tstqi" ! 141: [(set (cc0) ! 142: (match_operand:QI 0 "register_operand" "d"))] ! 143: "" ! 144: "* ! 145: { ! 146: check_label_emit (); ! 147: if (unsigned_jump_follows_p (insn)) ! 148: { ! 149: mvs_check_page (0, 4, 4); ! 150: return \"N %0,=X'000000FF'\"; ! 151: } ! 152: mvs_check_page (0, 8, 0); ! 153: return \"SLL %0,24\;SRA %0,24\"; ! 154: }") ! 155: ! 156: ; ! 157: ; tstdf instruction pattern(s). ! 158: ; ! 159: ! 160: (define_insn "tstdf" ! 161: [(set (cc0) ! 162: (match_operand:DF 0 "general_operand" "f"))] ! 163: "" ! 164: "* ! 165: { ! 166: check_label_emit (); ! 167: mvs_check_page (0, 2, 0); ! 168: return \"LTDR %0,%0\"; ! 169: }") ! 170: ! 171: ; ! 172: ; tstsf instruction pattern(s). ! 173: ; ! 174: ! 175: (define_insn "tstsf" ! 176: [(set (cc0) ! 177: (match_operand:SF 0 "general_operand" "f"))] ! 178: "" ! 179: "* ! 180: { ! 181: check_label_emit (); ! 182: mvs_check_page (0, 2, 0); ! 183: return \"LTER %0,%0\"; ! 184: }") ! 185: ! 186: ;; ! 187: ;;- Compare instructions. ! 188: ;; ! 189: ! 190: ; ! 191: ; cmpdi instruction pattern(s). ! 192: ; ! 193: ! 194: ;(define_insn "cmpdi" ! 195: ; [(set (cc0) ! 196: ; (compare (match_operand:DI 0 "register_operand" "d") ! 197: ; (match_operand:DI 1 "general_operand" "")))] ! 198: ; "" ! 199: ; "* ! 200: ;{ ! 201: ; check_label_emit (); ! 202: ; if (REG_P (operands[1])) ! 203: ; { ! 204: ; mvs_check_page (0, 8, 0); ! 205: ; if (unsigned_jump_follows_p (insn)) ! 206: ; return \"CLR %0,%1\;BNE *+6\;CLR %N0,%N1\"; ! 207: ; return \"CR %0,%1\;BNE *+6\;CLR %N0,%N1\"; ! 208: ; } ! 209: ; mvs_check_page (0, 12, 0); ! 210: ; if (unsigned_jump_follows_p (insn)) ! 211: ; return \"CL %0,%M1\;BNE *+8\;CL %N0,%L1\"; ! 212: ; return \"C %0,%M1\;BNE *+8\;CL %N0,%L1\"; ! 213: ;}") ! 214: ! 215: ; ! 216: ; cmpsi instruction pattern(s). ! 217: ; ! 218: ! 219: (define_insn "cmpsi" ! 220: [(set (cc0) ! 221: (compare (match_operand:SI 0 "register_operand" "d") ! 222: (match_operand:SI 1 "general_operand" "")))] ! 223: "" ! 224: "* ! 225: { ! 226: check_label_emit (); ! 227: if (REG_P (operands[1])) ! 228: { ! 229: mvs_check_page (0, 2, 0); ! 230: if (unsigned_jump_follows_p (insn)) ! 231: return \"CLR %0,%1\"; ! 232: return \"CR %0,%1\"; ! 233: } ! 234: if (GET_CODE (operands[1]) == CONST_INT) ! 235: { ! 236: mvs_check_page (0, 4, 4); ! 237: if (unsigned_jump_follows_p (insn)) ! 238: return \"CL %0,=F'%c1'\"; ! 239: return \"C %0,=F'%c1'\"; ! 240: } ! 241: mvs_check_page (0, 4, 0); ! 242: if (unsigned_jump_follows_p (insn)) ! 243: return \"CL %0,%1\"; ! 244: return \"C %0,%1\"; ! 245: }") ! 246: ! 247: ; ! 248: ; cmphi instruction pattern(s). ! 249: ; ! 250: ! 251: (define_insn "cmphi" ! 252: [(set (cc0) ! 253: (compare (match_operand:HI 0 "register_operand" "d") ! 254: (match_operand:HI 1 "general_operand" "")))] ! 255: "" ! 256: "* ! 257: { ! 258: check_label_emit (); ! 259: if (REG_P (operands[1])) ! 260: { ! 261: mvs_check_page (0, 8, 0); ! 262: if (unsigned_jump_follows_p (insn)) ! 263: return \"STH %1,140(,13)\;CLM %0,3,140(13)\"; ! 264: return \"STH %1,140(,13)\;CH %0,140(,13)\"; ! 265: } ! 266: if (GET_CODE (operands[1]) == CONST_INT) ! 267: { ! 268: mvs_check_page (0, 4, 2); ! 269: return \"CH %0,=H'%h1'\"; ! 270: } ! 271: mvs_check_page (0, 4, 0); ! 272: return \"CH %0,%1\"; ! 273: }") ! 274: ! 275: ; ! 276: ; cmpqi instruction pattern(s). ! 277: ; ! 278: ! 279: (define_insn "" ! 280: [(set (cc0) ! 281: (compare (match_operand:QI 0 "r_or_s_operand" "g") ! 282: (match_operand:QI 1 "r_or_s_operand" "g")))] ! 283: "unsigned_jump_follows_p (insn)" ! 284: "* ! 285: { ! 286: check_label_emit (); ! 287: if (REG_P (operands[0])) ! 288: { ! 289: if (REG_P (operands[1])) ! 290: { ! 291: mvs_check_page (0, 8, 0); ! 292: return \"STC %1,140(,13)\;CLM %0,1,140(13)\"; ! 293: } ! 294: if (GET_CODE (operands[1]) == CONST_INT) ! 295: { ! 296: mvs_check_page (0, 4, 1); ! 297: return \"CLM %0,1,=X'%X1'\"; ! 298: } ! 299: mvs_check_page (0, 4, 0); ! 300: return \"CLM %0,1,%1\"; ! 301: } ! 302: else if (GET_CODE (operands[0]) == CONST_INT) ! 303: { ! 304: cc_status.flags |= CC_REVERSED; ! 305: if (REG_P (operands[1])) ! 306: { ! 307: mvs_check_page (0, 4, 1); ! 308: return \"CLM %1,1,=X'%X0'\"; ! 309: } ! 310: mvs_check_page (0, 4, 0); ! 311: return \"CLI %1,%B0\"; ! 312: } ! 313: if (GET_CODE (operands[1]) == CONST_INT) ! 314: { ! 315: mvs_check_page (0, 4, 0); ! 316: return \"CLI %0,%B1\"; ! 317: } ! 318: if (GET_CODE (operands[1]) == MEM) ! 319: { ! 320: mvs_check_page (0, 6, 0); ! 321: return \"CLC %O0(1,%R0),%1\"; ! 322: } ! 323: cc_status.flags |= CC_REVERSED; ! 324: mvs_check_page (0, 4, 0); ! 325: return \"CLM %1,1,%0\"; ! 326: }") ! 327: ! 328: (define_insn "cmpqi" ! 329: [(set (cc0) ! 330: (compare (match_operand:QI 0 "register_operand" "d") ! 331: (match_operand:QI 1 "general_operand" "di")))] ! 332: "" ! 333: "* ! 334: { ! 335: check_label_emit (); ! 336: if (unsigned_jump_follows_p (insn)) ! 337: { ! 338: if (REG_P (operands[1])) ! 339: { ! 340: mvs_check_page (0, 4, 0); ! 341: return \"CLM %0,1,%1\"; ! 342: } ! 343: if (GET_CODE (operands[1]) == CONST_INT) ! 344: { ! 345: mvs_check_page (0, 4, 1); ! 346: return \"CLM %0,1,=X'%X1'\"; ! 347: } ! 348: mvs_check_page (0, 8, 0); ! 349: return \"STC %1,140(,13)\;CLM %0,1,140(13)\"; ! 350: } ! 351: if (REG_P (operands[1])) ! 352: { ! 353: mvs_check_page (0, 18, 0); ! 354: return \"SLL %0,24\;SRA %0,24\;SLL %1,24\;SRA %1,24\;CR %0,%1\"; ! 355: } ! 356: mvs_check_page (0, 12, 0); ! 357: return \"SLL %0,24\;SRA %0,24\;C %0,%1\"; ! 358: }") ! 359: ! 360: ; ! 361: ; cmpdf instruction pattern(s). ! 362: ; ! 363: ! 364: (define_insn "cmpdf" ! 365: [(set (cc0) ! 366: (compare (match_operand:DF 0 "general_operand" "f,mF") ! 367: (match_operand:DF 1 "general_operand" "fmF,f")))] ! 368: "" ! 369: "* ! 370: { ! 371: check_label_emit (); ! 372: if (FP_REG_P (operands[0])) ! 373: { ! 374: if (FP_REG_P (operands[1])) ! 375: { ! 376: mvs_check_page (0, 2, 0); ! 377: return \"CDR %0,%1\"; ! 378: } ! 379: mvs_check_page (0, 4, 0); ! 380: return \"CD %0,%1\"; ! 381: } ! 382: cc_status.flags |= CC_REVERSED; ! 383: mvs_check_page (0, 4, 0); ! 384: return \"CD %1,%0\"; ! 385: }") ! 386: ! 387: ; ! 388: ; cmpsf instruction pattern(s). ! 389: ; ! 390: ! 391: (define_insn "cmpsf" ! 392: [(set (cc0) ! 393: (compare (match_operand:SF 0 "general_operand" "f,mF") ! 394: (match_operand:SF 1 "general_operand" "fmF,f")))] ! 395: "" ! 396: "* ! 397: { ! 398: check_label_emit (); ! 399: if (FP_REG_P (operands[0])) ! 400: { ! 401: if (FP_REG_P (operands[1])) ! 402: { ! 403: mvs_check_page (0, 2, 0); ! 404: return \"CER %0,%1\"; ! 405: } ! 406: mvs_check_page (0, 4, 0); ! 407: return \"CE %0,%1\"; ! 408: } ! 409: cc_status.flags |= CC_REVERSED; ! 410: mvs_check_page (0, 4, 0); ! 411: return \"CE %1,%0\"; ! 412: }") ! 413: ! 414: ; ! 415: ; cmpstrsi instruction pattern(s). ! 416: ; ! 417: ! 418: (define_expand "cmpstrsi" ! 419: [(set (match_operand:SI 0 "general_operand" "") ! 420: (compare (match_operand:BLK 1 "general_operand" "") ! 421: (match_operand:BLK 2 "general_operand" ""))) ! 422: (use (match_operand:SI 3 "general_operand" "")) ! 423: (use (match_operand:SI 4 "" ""))] ! 424: "" ! 425: " ! 426: { ! 427: rtx op1, op2; ! 428: ! 429: op1 = XEXP (operands[1], 0); ! 430: if (GET_CODE (op1) == REG ! 431: || (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1, 0)) == REG ! 432: && GET_CODE (XEXP (op1, 1)) == CONST_INT ! 433: && (unsigned) INTVAL (XEXP (op1, 1)) < 4096)) ! 434: { ! 435: op1 = operands[1]; ! 436: } ! 437: else ! 438: { ! 439: op1 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op1)); ! 440: } ! 441: ! 442: op2 = XEXP (operands[2], 0); ! 443: if (GET_CODE (op2) == REG ! 444: || (GET_CODE (op2) == PLUS && GET_CODE (XEXP (op2, 0)) == REG ! 445: && GET_CODE (XEXP (op2, 1)) == CONST_INT ! 446: && (unsigned) INTVAL (XEXP (op2, 1)) < 4096)) ! 447: { ! 448: op2 = operands[2]; ! 449: } ! 450: else ! 451: { ! 452: op2 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op2)); ! 453: } ! 454: ! 455: if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256) ! 456: { ! 457: emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, ! 458: gen_rtx (SET, VOIDmode, operands[0], ! 459: gen_rtx (COMPARE, VOIDmode, op1, op2)), ! 460: gen_rtx (USE, VOIDmode, operands[3])))); ! 461: } ! 462: else ! 463: { ! 464: rtx reg1 = gen_reg_rtx (DImode); ! 465: rtx reg2 = gen_reg_rtx (DImode); ! 466: rtx subreg = gen_rtx (SUBREG, SImode, reg1, 1); ! 467: ! 468: emit_insn (gen_rtx (SET, VOIDmode, subreg, operands[3])); ! 469: emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode, reg2, 1), ! 470: subreg)); ! 471: emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5, ! 472: gen_rtx (SET, VOIDmode, operands[0], ! 473: gen_rtx (COMPARE, VOIDmode, op1, op2)), ! 474: gen_rtx (USE, VOIDmode, reg1), ! 475: gen_rtx (USE, VOIDmode, reg2), ! 476: gen_rtx (CLOBBER, VOIDmode, reg1), ! 477: gen_rtx (CLOBBER, VOIDmode, reg2)))); ! 478: } ! 479: DONE; ! 480: }") ! 481: ! 482: ; Compare a block that is less than 256 bytes in length. ! 483: ! 484: (define_insn "" ! 485: [(set (match_operand:SI 0 "register_operand" "d") ! 486: (compare (match_operand:BLK 1 "s_operand" "m") ! 487: (match_operand:BLK 2 "s_operand" "m"))) ! 488: (use (match_operand:QI 3 "immediate_operand" "I"))] ! 489: "((unsigned) INTVAL (operands[3]) < 256)" ! 490: "* ! 491: { ! 492: check_label_emit (); ! 493: mvs_check_page (0, 22, 0); ! 494: return \"LA %0,1\;CLC %O1(%c3,%R1),%2\;BH *+12\;BL *+6\;SLR %0,%0\;LNR %0,%0\"; ! 495: }") ! 496: ! 497: ; Compare a block that is larger than 255 bytes in length. ! 498: ! 499: (define_insn "" ! 500: [(set (match_operand:SI 0 "register_operand" "d") ! 501: (compare (match_operand:BLK 1 "general_operand" "m") ! 502: (match_operand:BLK 2 "general_operand" "m"))) ! 503: (use (match_operand:DI 3 "register_operand" "d")) ! 504: (use (match_operand:DI 4 "register_operand" "d")) ! 505: (clobber (match_dup 3)) ! 506: (clobber (match_dup 4))] ! 507: "" ! 508: "* ! 509: { ! 510: check_label_emit (); ! 511: mvs_check_page (0, 26, 0); ! 512: return \"LA %3,%1\;LA %4,%2\;LA %0,1\;CLCL %3,%4\;BH *+12\;BL *+6\;SLR %0,%0\;LNR %0,%0\"; ! 513: }") ! 514: ! 515: ;; ! 516: ;;- Move instructions. ! 517: ;; ! 518: ! 519: ; ! 520: ; movdi instruction pattern(s). ! 521: ; ! 522: ! 523: (define_insn "" ! 524: [(set (match_operand:DI 0 "r_or_s_operand" "=dm") ! 525: (match_operand:DI 1 "r_or_s_operand" "dim*fF"))] ! 526: "TARGET_CHAR_INSTRUCTIONS" ! 527: "* ! 528: { ! 529: check_label_emit (); ! 530: if (REG_P (operands[0])) ! 531: { ! 532: if (FP_REG_P (operands[1])) ! 533: { ! 534: mvs_check_page (0, 8, 0); ! 535: return \"STD %1,140(,13)\;LM %0,%N0,140(13)\"; ! 536: } ! 537: if (REG_P (operands[1])) ! 538: { ! 539: mvs_check_page (0, 4, 0); ! 540: return \"LR %0,%1\;LR %N0,%N1\"; ! 541: } ! 542: if (operands[1] == const0_rtx) ! 543: { ! 544: CC_STATUS_INIT; ! 545: mvs_check_page (0, 4, 0); ! 546: return \"SLR %0,%0\;SLR %N0,%N0\"; ! 547: } ! 548: if (GET_CODE (operands[1]) == CONST_INT ! 549: && (unsigned) INTVAL (operands[1]) < 4096) ! 550: { ! 551: CC_STATUS_INIT; ! 552: mvs_check_page (0, 6, 0); ! 553: return \"SLR %0,%0\;LA %N0,%c1\"; ! 554: } ! 555: if (GET_CODE (operands[1]) == CONST_INT) ! 556: { ! 557: CC_STATUS_SET (operands[0], operands[1]); ! 558: mvs_check_page (0, 8, 0); ! 559: return \"L %0,%1\;SRDA %0,32\"; ! 560: } ! 561: mvs_check_page (0, 4, 0); ! 562: return \"LM %0,%N0,%1\"; ! 563: } ! 564: else if (FP_REG_P (operands[1])) ! 565: { ! 566: mvs_check_page (0, 4, 0); ! 567: return \"STD %1,%0\"; ! 568: } ! 569: else if (REG_P (operands[1])) ! 570: { ! 571: mvs_check_page (0, 4, 0); ! 572: return \"STM %1,%N1,%0\"; ! 573: } ! 574: mvs_check_page (0, 6, 0); ! 575: return \"MVC %O0(8,%R0),%1\"; ! 576: }") ! 577: ! 578: (define_insn "movdi" ! 579: [(set (match_operand:DI 0 "general_operand" "=dm") ! 580: (match_operand:DI 1 "general_operand" "dim*fF"))] ! 581: "" ! 582: "* ! 583: { ! 584: check_label_emit (); ! 585: if (REG_P (operands[0])) ! 586: { ! 587: if (FP_REG_P (operands[1])) ! 588: { ! 589: mvs_check_page (0, 8, 0); ! 590: return \"STD %1,140(,13)\;LM %0,%N0,140(13)\"; ! 591: } ! 592: if (REG_P (operands[1])) ! 593: { ! 594: mvs_check_page (0, 4, 0); ! 595: return \"LR %0,%1\;LR %N0,%N1\"; ! 596: } ! 597: if (operands[1] == const0_rtx) ! 598: { ! 599: CC_STATUS_INIT; ! 600: mvs_check_page (0, 4, 0); ! 601: return \"SLR %0,%0\;SLR %N0,%N0\"; ! 602: } ! 603: if (GET_CODE (operands[1]) == CONST_INT ! 604: && (unsigned) INTVAL (operands[1]) < 4096) ! 605: { ! 606: CC_STATUS_INIT; ! 607: mvs_check_page (0, 6, 0); ! 608: return \"SLR %0,%0\;LA %N0,%c1\"; ! 609: } ! 610: if (GET_CODE (operands[1]) == CONST_INT) ! 611: { ! 612: CC_STATUS_SET (operands[0], operands[1]); ! 613: mvs_check_page (0, 8, 0); ! 614: return \"L %0,%1\;SRDA %0,32\"; ! 615: } ! 616: mvs_check_page (0, 4, 0); ! 617: return \"LM %0,%N0,%1\"; ! 618: } ! 619: else if (FP_REG_P (operands[1])) ! 620: { ! 621: mvs_check_page (0, 4, 0); ! 622: return \"STD %1,%0\"; ! 623: } ! 624: mvs_check_page (0, 4, 0); ! 625: return \"STM %1,%N1,%0\"; ! 626: }") ! 627: ! 628: ; ! 629: ; movsi instruction pattern(s). ! 630: ; ! 631: ! 632: (define_insn "" ! 633: [(set (match_operand:SI 0 "r_or_s_operand" "=dm,dm") ! 634: (match_operand:SI 1 "r_or_s_operand" "dim,*fF"))] ! 635: "TARGET_CHAR_INSTRUCTIONS" ! 636: "* ! 637: { ! 638: check_label_emit (); ! 639: if (REG_P (operands[0])) ! 640: { ! 641: if (FP_REG_P (operands[1])) ! 642: { ! 643: mvs_check_page (0, 8, 0); ! 644: return \"STE %1,140(,13)\;L %0,140(,13)\"; ! 645: } ! 646: if (REG_P (operands[1])) ! 647: { ! 648: mvs_check_page (0, 2, 0); ! 649: return \"LR %0,%1\"; ! 650: } ! 651: if (operands[1] == const0_rtx) ! 652: { ! 653: CC_STATUS_INIT; ! 654: mvs_check_page (0, 2, 0); ! 655: return \"SLR %0,%0\"; ! 656: } ! 657: if (GET_CODE (operands[1]) == CONST_INT ! 658: && (unsigned) INTVAL (operands[1]) < 4096) ! 659: { ! 660: mvs_check_page (0, 4, 0); ! 661: return \"LA %0,%c1\"; ! 662: } ! 663: mvs_check_page (0, 4, 0); ! 664: return \"L %0,%1\"; ! 665: } ! 666: else if (FP_REG_P (operands[1])) ! 667: { ! 668: mvs_check_page (0, 4, 0); ! 669: return \"STE %1,%0\"; ! 670: } ! 671: else if (REG_P (operands[1])) ! 672: { ! 673: mvs_check_page (0, 4, 0); ! 674: return \"ST %1,%0\"; ! 675: } ! 676: mvs_check_page (0, 6, 0); ! 677: return \"MVC %O0(4,%R0),%1\"; ! 678: }") ! 679: ! 680: (define_insn "movsi" ! 681: [(set (match_operand:SI 0 "general_operand" "=d,dm") ! 682: (match_operand:SI 1 "general_operand" "dimF,*fd"))] ! 683: "" ! 684: "* ! 685: { ! 686: check_label_emit (); ! 687: if (REG_P (operands[0])) ! 688: { ! 689: if (FP_REG_P (operands[1])) ! 690: { ! 691: mvs_check_page (0, 8, 0); ! 692: return \"STE %1,140(,13)\;L %0,140(,13)\"; ! 693: } ! 694: if (REG_P (operands[1])) ! 695: { ! 696: mvs_check_page (0, 2, 0); ! 697: return \"LR %0,%1\"; ! 698: } ! 699: if (operands[1] == const0_rtx) ! 700: { ! 701: CC_STATUS_INIT; ! 702: mvs_check_page (0, 2, 0); ! 703: return \"SLR %0,%0\"; ! 704: } ! 705: if (GET_CODE (operands[1]) == CONST_INT ! 706: && (unsigned) INTVAL (operands[1]) < 4096) ! 707: { ! 708: mvs_check_page (0, 4, 0); ! 709: return \"LA %0,%c1\"; ! 710: } ! 711: mvs_check_page (0, 4, 0); ! 712: return \"L %0,%1\"; ! 713: } ! 714: else if (FP_REG_P (operands[1])) ! 715: { ! 716: mvs_check_page (0, 4, 0); ! 717: return \"STE %1,%0\"; ! 718: } ! 719: mvs_check_page (0, 4, 0); ! 720: return \"ST %1,%0\"; ! 721: }") ! 722: ! 723: ;(define_expand "movsi" ! 724: ; [(set (match_operand:SI 0 "general_operand" "=d,dm") ! 725: ; (match_operand:SI 1 "general_operand" "dimF,*fd"))] ! 726: ; "" ! 727: ; " ! 728: ;{ ! 729: ; rtx op0, op1; ! 730: ; ! 731: ; op0 = operands[0]; ! 732: ; if (GET_CODE (op0) == CONST ! 733: ; && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SYMBOL_REF ! 734: ; && SYMBOL_REF_FLAG (XEXP (XEXP (op0, 0), 0))) ! 735: ; { ! 736: ; op0 = gen_rtx (MEM, SImode, copy_to_mode_reg (SImode, XEXP (op0, 0))); ! 737: ; } ! 738: ; ! 739: ; op1 = operands[1]; ! 740: ; if (GET_CODE (op1) == CONST ! 741: ; && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF ! 742: ; && SYMBOL_REF_FLAG (XEXP (XEXP (op1, 0), 0))) ! 743: ; { ! 744: ; op1 = gen_rtx (MEM, SImode, copy_to_mode_reg (SImode, XEXP (op1, 0))); ! 745: ; } ! 746: ; ! 747: ; emit_insn (gen_rtx (SET, VOIDmode, op0, op1)); ! 748: ; DONE; ! 749: ;}") ! 750: ! 751: ; ! 752: ; movhi instruction pattern(s). ! 753: ; ! 754: ! 755: (define_insn "" ! 756: [(set (match_operand:HI 0 "r_or_s_operand" "=g") ! 757: (match_operand:HI 1 "r_or_s_operand" "g"))] ! 758: "TARGET_CHAR_INSTRUCTIONS" ! 759: "* ! 760: { ! 761: check_label_emit (); ! 762: if (REG_P (operands[0])) ! 763: { ! 764: if (REG_P (operands[1])) ! 765: { ! 766: mvs_check_page (0, 2, 0); ! 767: return \"LR %0,%1\"; ! 768: } ! 769: if (operands[1] == const0_rtx) ! 770: { ! 771: CC_STATUS_INIT; ! 772: mvs_check_page (0, 2, 0); ! 773: return \"SLR %0,%0\"; ! 774: } ! 775: if (GET_CODE (operands[1]) == CONST_INT ! 776: && (unsigned) INTVAL (operands[1]) < 4096) ! 777: { ! 778: mvs_check_page (0, 4, 0); ! 779: return \"LA %0,%c1\"; ! 780: } ! 781: if (GET_CODE (operands[1]) == CONST_INT) ! 782: { ! 783: mvs_check_page (0, 4, 2); ! 784: return \"LH %0,=H'%h1'\"; ! 785: } ! 786: mvs_check_page (0, 4, 0); ! 787: return \"LH %0,%1\"; ! 788: } ! 789: else if (REG_P (operands[1])) ! 790: { ! 791: mvs_check_page (0, 4, 0); ! 792: return \"STH %1,%0\"; ! 793: } ! 794: if (GET_CODE (operands[1]) == CONST_INT) ! 795: { ! 796: mvs_check_page (0, 6, 0); ! 797: return \"MVC %O0(2,%R0),=H'%h1'\"; ! 798: } ! 799: mvs_check_page (0, 6, 0); ! 800: return \"MVC %O0(2,%R0),%1\"; ! 801: }") ! 802: ! 803: (define_insn "movhi" ! 804: [(set (match_operand:HI 0 "general_operand" "=d,m") ! 805: (match_operand:HI 1 "general_operand" "g,d"))] ! 806: "" ! 807: "* ! 808: { ! 809: check_label_emit (); ! 810: if (REG_P (operands[0])) ! 811: { ! 812: if (REG_P (operands[1])) ! 813: { ! 814: mvs_check_page (0, 2, 0); ! 815: return \"LR %0,%1\"; ! 816: } ! 817: if (operands[1] == const0_rtx) ! 818: { ! 819: CC_STATUS_INIT; ! 820: mvs_check_page (0, 2, 0); ! 821: return \"SLR %0,%0\"; ! 822: } ! 823: if (GET_CODE (operands[1]) == CONST_INT ! 824: && (unsigned) INTVAL (operands[1]) < 4096) ! 825: { ! 826: mvs_check_page (0, 4, 0); ! 827: return \"LA %0,%c1\"; ! 828: } ! 829: if (GET_CODE (operands[1]) == CONST_INT) ! 830: { ! 831: mvs_check_page (0, 4, 2); ! 832: return \"LH %0,=H'%h1'\"; ! 833: } ! 834: mvs_check_page (0, 4, 0); ! 835: return \"LH %0,%1\"; ! 836: } ! 837: mvs_check_page (0, 4, 0); ! 838: return \"STH %1,%0\"; ! 839: }") ! 840: ! 841: ; ! 842: ; movqi instruction pattern(s). ! 843: ; ! 844: ! 845: (define_insn "" ! 846: [(set (match_operand:QI 0 "r_or_s_operand" "=g") ! 847: (match_operand:QI 1 "r_or_s_operand" "g"))] ! 848: "TARGET_CHAR_INSTRUCTIONS" ! 849: "* ! 850: { ! 851: check_label_emit (); ! 852: if (REG_P (operands[0])) ! 853: { ! 854: if (REG_P (operands[1])) ! 855: { ! 856: mvs_check_page (0, 2, 0); ! 857: return \"LR %0,%1\"; ! 858: } ! 859: if (operands[1] == const0_rtx) ! 860: { ! 861: CC_STATUS_INIT; ! 862: mvs_check_page (0, 2, 0); ! 863: return \"SLR %0,%0\"; ! 864: } ! 865: if (GET_CODE (operands[1]) == CONST_INT) ! 866: { ! 867: if (INTVAL (operands[1]) >= 0) ! 868: { ! 869: mvs_check_page (0, 4, 0); ! 870: return \"LA %0,%c1\"; ! 871: } ! 872: mvs_check_page (0, 4, 0); ! 873: return \"L %0,=F'%c1'\"; ! 874: } ! 875: mvs_check_page (0, 4, 0); ! 876: return \"IC %0,%1\"; ! 877: } ! 878: else if (REG_P (operands[1])) ! 879: { ! 880: mvs_check_page (0, 4, 0); ! 881: return \"STC %1,%0\"; ! 882: } ! 883: else if (GET_CODE (operands[1]) == CONST_INT) ! 884: { ! 885: mvs_check_page (0, 4, 0); ! 886: return \"MVI %0,%B1\"; ! 887: } ! 888: mvs_check_page (0, 6, 0); ! 889: return \"MVC %O0(1,%R0),%1\"; ! 890: }") ! 891: ! 892: (define_insn "movqi" ! 893: [(set (match_operand:QI 0 "general_operand" "=d,m") ! 894: (match_operand:QI 1 "general_operand" "g,d"))] ! 895: "" ! 896: "* ! 897: { ! 898: check_label_emit (); ! 899: if (REG_P (operands[0])) ! 900: { ! 901: if (REG_P (operands[1])) ! 902: { ! 903: mvs_check_page (0, 2, 0); ! 904: return \"LR %0,%1\"; ! 905: } ! 906: if (operands[1] == const0_rtx) ! 907: { ! 908: CC_STATUS_INIT; ! 909: mvs_check_page (0, 2, 0); ! 910: return \"SLR %0,%0\"; ! 911: } ! 912: if (GET_CODE (operands[1]) == CONST_INT) ! 913: { ! 914: if (INTVAL (operands[1]) >= 0) ! 915: { ! 916: mvs_check_page (0, 4, 0); ! 917: return \"LA %0,%c1\"; ! 918: } ! 919: mvs_check_page (0, 4, 0); ! 920: return \"L %0,=F'%c1'\"; ! 921: } ! 922: mvs_check_page (0, 4, 0); ! 923: return \"IC %0,%1\"; ! 924: } ! 925: mvs_check_page (0, 4, 0); ! 926: return \"STC %1,%0\"; ! 927: }") ! 928: ! 929: ; ! 930: ; movestrictqi instruction pattern(s). ! 931: ; ! 932: ! 933: (define_insn "movestrictqi" ! 934: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=d")) ! 935: (match_operand:QI 1 "general_operand" "g"))] ! 936: "" ! 937: "* ! 938: { ! 939: check_label_emit (); ! 940: if (REG_P (operands[1])) ! 941: { ! 942: mvs_check_page (0, 8, 0); ! 943: return \"STC %1,140(,13)\;IC %0,140(,13)\"; ! 944: } ! 945: mvs_check_page (0, 4, 0); ! 946: return \"IC %0,%1\"; ! 947: }") ! 948: ! 949: ; ! 950: ; movstricthi instruction pattern(s). ! 951: ; ! 952: ! 953: (define_insn "" ! 954: [(set (strict_low_part (match_operand:HI 0 "register_operand" "=d")) ! 955: (match_operand:HI 1 "r_or_s_operand" "g"))] ! 956: "" ! 957: "* ! 958: { ! 959: check_label_emit (); ! 960: if (REG_P (operands[1])) ! 961: { ! 962: mvs_check_page (0, 8, 0); ! 963: return \"STH %1,140(,13)\;ICM %0,3,140(13)\"; ! 964: } ! 965: else if (GET_CODE (operands[1]) == CONST_INT) ! 966: { ! 967: mvs_check_page (0, 4, 2); ! 968: return \"ICM %0,3,=H'%h1'\"; ! 969: } ! 970: mvs_check_page (0, 4, 0); ! 971: return \"ICM %0,3,%1\"; ! 972: }") ! 973: ! 974: (define_insn "movestricthi" ! 975: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=dm")) ! 976: (match_operand:HI 1 "general_operand" "d"))] ! 977: "" ! 978: "* ! 979: { ! 980: check_label_emit (); ! 981: if (REG_P (operands[0])) ! 982: { ! 983: mvs_check_page (0, 8, 0); ! 984: return \"STH %1,140(,13)\;ICM %0,3,140(13)\"; ! 985: } ! 986: mvs_check_page (0, 4, 0); ! 987: return \"STH %1,%0\"; ! 988: }") ! 989: ! 990: ; ! 991: ; movdf instruction pattern(s). ! 992: ; ! 993: ! 994: (define_insn "" ! 995: [(set (match_operand:DF 0 "r_or_s_operand" "=fm,fm,*dm") ! 996: (match_operand:DF 1 "r_or_s_operand" "fmF,*dm,fmF"))] ! 997: "TARGET_CHAR_INSTRUCTIONS" ! 998: "* ! 999: { ! 1000: check_label_emit (); ! 1001: if (FP_REG_P (operands[0])) ! 1002: { ! 1003: if (FP_REG_P (operands[1])) ! 1004: { ! 1005: mvs_check_page (0, 2, 0); ! 1006: return \"LDR %0,%1\"; ! 1007: } ! 1008: if (REG_P (operands[1])) ! 1009: { ! 1010: mvs_check_page (0, 8, 0); ! 1011: return \"STM %1,%N1,140(13)\;LD %0,140(,13)\"; ! 1012: } ! 1013: if (operands[1] == const0_rtx) ! 1014: { ! 1015: CC_STATUS_SET (operands[0], operands[1]); ! 1016: mvs_check_page (0, 2, 0); ! 1017: return \"SDR %0,%0\"; ! 1018: } ! 1019: mvs_check_page (0, 4, 0); ! 1020: return \"LD %0,%1\"; ! 1021: } ! 1022: if (REG_P (operands[0])) ! 1023: { ! 1024: if (FP_REG_P (operands[1])) ! 1025: { ! 1026: mvs_check_page (0, 12, 0); ! 1027: return \"STD %1,140(,13)\;LM %0,%N0,140(13)\"; ! 1028: } ! 1029: mvs_check_page (0, 4, 0); ! 1030: return \"LM %0,%N0,%1\"; ! 1031: } ! 1032: else if (FP_REG_P (operands[1])) ! 1033: { ! 1034: mvs_check_page (0, 4, 0); ! 1035: return \"STD %1,%0\"; ! 1036: } ! 1037: else if (REG_P (operands[1])) ! 1038: { ! 1039: mvs_check_page (0, 4, 0); ! 1040: return \"STM %1,%N1,%0\"; ! 1041: } ! 1042: mvs_check_page (0, 6, 0); ! 1043: return \"MVC %O0(8,%R0),%1\"; ! 1044: }") ! 1045: ! 1046: (define_insn "movdf" ! 1047: [(set (match_operand:DF 0 "general_operand" "=f,fm,m,*d") ! 1048: (match_operand:DF 1 "general_operand" "fmF,*d,f,fmF"))] ! 1049: "" ! 1050: "* ! 1051: { ! 1052: check_label_emit (); ! 1053: if (FP_REG_P (operands[0])) ! 1054: { ! 1055: if (FP_REG_P (operands[1])) ! 1056: { ! 1057: mvs_check_page (0, 2, 0); ! 1058: return \"LDR %0,%1\"; ! 1059: } ! 1060: if (REG_P (operands[1])) ! 1061: { ! 1062: mvs_check_page (0, 8, 0); ! 1063: return \"STM %1,%N1,140(13)\;LD %0,140(,13)\"; ! 1064: } ! 1065: if (operands[1] == const0_rtx) ! 1066: { ! 1067: CC_STATUS_SET (operands[0], operands[1]); ! 1068: mvs_check_page (0, 2, 0); ! 1069: return \"SDR %0,%0\"; ! 1070: } ! 1071: mvs_check_page (0, 4, 0); ! 1072: return \"LD %0,%1\"; ! 1073: } ! 1074: else if (REG_P (operands[0])) ! 1075: { ! 1076: if (FP_REG_P (operands[1])) ! 1077: { ! 1078: mvs_check_page (0, 12, 0); ! 1079: return \"STD %1,140(,13)\;LM %0,%N0,140(13)\"; ! 1080: } ! 1081: mvs_check_page (0, 4, 0); ! 1082: return \"LM %0,%N0,%1\"; ! 1083: } ! 1084: else if (FP_REG_P (operands[1])) ! 1085: { ! 1086: mvs_check_page (0, 4, 0); ! 1087: return \"STD %1,%0\"; ! 1088: } ! 1089: mvs_check_page (0, 4, 0); ! 1090: return \"STM %1,%N1,%0\"; ! 1091: }") ! 1092: ! 1093: ; ! 1094: ; movsf instruction pattern(s). ! 1095: ; ! 1096: ! 1097: (define_insn "" ! 1098: [(set (match_operand:SF 0 "r_or_s_operand" "=fm,fm,*dm") ! 1099: (match_operand:SF 1 "r_or_s_operand" "fmF,*dm,fmF"))] ! 1100: "TARGET_CHAR_INSTRUCTIONS" ! 1101: "* ! 1102: { ! 1103: check_label_emit (); ! 1104: if (FP_REG_P (operands[0])) ! 1105: { ! 1106: if (FP_REG_P (operands[1])) ! 1107: { ! 1108: mvs_check_page (0, 2, 0); ! 1109: return \"LER %0,%1\"; ! 1110: } ! 1111: if (REG_P (operands[1])) ! 1112: { ! 1113: mvs_check_page (0, 8, 0); ! 1114: return \"ST %1,140(,13)\;LE %0,140(,13)\"; ! 1115: } ! 1116: if (operands[1] == const0_rtx) ! 1117: { ! 1118: CC_STATUS_SET (operands[0], operands[1]); ! 1119: mvs_check_page (0, 2, 0); ! 1120: return \"SER %0,%0\"; ! 1121: } ! 1122: mvs_check_page (0, 4, 0); ! 1123: return \"LE %0,%1\"; ! 1124: } ! 1125: else if (REG_P (operands[0])) ! 1126: { ! 1127: if (FP_REG_P (operands[1])) ! 1128: { ! 1129: mvs_check_page (0, 8, 0); ! 1130: return \"STE %1,140(,13)\;L %0,140(,13)\"; ! 1131: } ! 1132: mvs_check_page (0, 4, 0); ! 1133: return \"L %0,%1\"; ! 1134: } ! 1135: else if (FP_REG_P (operands[1])) ! 1136: { ! 1137: mvs_check_page (0, 4, 0); ! 1138: return \"STE %1,%0\"; ! 1139: } ! 1140: else if (REG_P (operands[1])) ! 1141: { ! 1142: mvs_check_page (0, 4, 0); ! 1143: return \"ST %1,%0\"; ! 1144: } ! 1145: mvs_check_page (0, 6, 0); ! 1146: return \"MVC %O0(4,%R0),%1\"; ! 1147: }") ! 1148: ! 1149: (define_insn "movsf" ! 1150: [(set (match_operand:SF 0 "general_operand" "=f,fm,m,*d") ! 1151: (match_operand:SF 1 "general_operand" "fmF,*d,f,fmF"))] ! 1152: "" ! 1153: "* ! 1154: { ! 1155: check_label_emit (); ! 1156: if (FP_REG_P (operands[0])) ! 1157: { ! 1158: if (FP_REG_P (operands[1])) ! 1159: { ! 1160: mvs_check_page (0, 2, 0); ! 1161: return \"LER %0,%1\"; ! 1162: } ! 1163: if (REG_P (operands[1])) ! 1164: { ! 1165: mvs_check_page (0, 8, 0); ! 1166: return \"ST %1,140(,13)\;LE %0,140(,13)\"; ! 1167: } ! 1168: if (operands[1] == const0_rtx) ! 1169: { ! 1170: CC_STATUS_SET (operands[0], operands[1]); ! 1171: mvs_check_page (0, 2, 0); ! 1172: return \"SER %0,%0\"; ! 1173: } ! 1174: mvs_check_page (0, 4, 0); ! 1175: return \"LE %0,%1\"; ! 1176: } ! 1177: else if (REG_P (operands[0])) ! 1178: { ! 1179: if (FP_REG_P (operands[1])) ! 1180: { ! 1181: mvs_check_page (0, 8, 0); ! 1182: return \"STE %1,140(,13)\;L %0,140(,13)\"; ! 1183: } ! 1184: mvs_check_page (0, 4, 0); ! 1185: return \"L %0,%1\"; ! 1186: } ! 1187: else if (FP_REG_P (operands[1])) ! 1188: { ! 1189: mvs_check_page (0, 4, 0); ! 1190: return \"STE %1,%0\"; ! 1191: } ! 1192: mvs_check_page (0, 4, 0); ! 1193: return \"ST %1,%0\"; ! 1194: }") ! 1195: ! 1196: ; ! 1197: ; movstrsi instruction pattern(s). ! 1198: ; ! 1199: ! 1200: (define_expand "movstrsi" ! 1201: [(set (match_operand:BLK 0 "general_operand" "") ! 1202: (match_operand:BLK 1 "general_operand" "")) ! 1203: (use (match_operand:SI 2 "general_operand" "")) ! 1204: (match_operand 3 "" "")] ! 1205: "" ! 1206: " ! 1207: { ! 1208: rtx op0, op1; ! 1209: ! 1210: op0 = XEXP (operands[0], 0); ! 1211: if (GET_CODE (op0) == REG ! 1212: || (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 0)) == REG ! 1213: && GET_CODE (XEXP (op0, 1)) == CONST_INT ! 1214: && (unsigned) INTVAL (XEXP (op0, 1)) < 4096)) ! 1215: { ! 1216: op0 = operands[0]; ! 1217: } ! 1218: else ! 1219: { ! 1220: op0 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op0)); ! 1221: } ! 1222: ! 1223: op1 = XEXP (operands[1], 0); ! 1224: if (GET_CODE (op1) == REG ! 1225: || (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1, 0)) == REG ! 1226: && GET_CODE (XEXP (op1, 1)) == CONST_INT ! 1227: && (unsigned) INTVAL (XEXP (op1, 1)) < 4096)) ! 1228: { ! 1229: op1 = operands[1]; ! 1230: } ! 1231: else ! 1232: { ! 1233: op1 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op1)); ! 1234: } ! 1235: ! 1236: if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 256) ! 1237: { ! 1238: emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, ! 1239: gen_rtx (SET, VOIDmode, op0, op1), ! 1240: gen_rtx (USE, VOIDmode, operands[2])))); ! 1241: } ! 1242: else ! 1243: { ! 1244: rtx reg1 = gen_reg_rtx (DImode); ! 1245: rtx reg2 = gen_reg_rtx (DImode); ! 1246: rtx subreg = gen_rtx (SUBREG, SImode, reg1, 1); ! 1247: ! 1248: emit_insn (gen_rtx (SET, VOIDmode, subreg, operands[2])); ! 1249: emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode, reg2, 1), ! 1250: subreg)); ! 1251: emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5, ! 1252: gen_rtx (SET, VOIDmode, op0, op1), ! 1253: gen_rtx (USE, VOIDmode, reg1), ! 1254: gen_rtx (USE, VOIDmode, reg2), ! 1255: gen_rtx (CLOBBER, VOIDmode, reg1), ! 1256: gen_rtx (CLOBBER, VOIDmode, reg2)))); ! 1257: } ! 1258: DONE; ! 1259: }") ! 1260: ! 1261: ; Move a block that is less than 256 bytes in length. ! 1262: ! 1263: (define_insn "" ! 1264: [(set (match_operand:BLK 0 "s_operand" "=m") ! 1265: (match_operand:BLK 1 "s_operand" "m")) ! 1266: (use (match_operand 2 "immediate_operand" "I"))] ! 1267: "((unsigned) INTVAL (operands[2]) < 256)" ! 1268: "* ! 1269: { ! 1270: check_label_emit (); ! 1271: mvs_check_page (0, 6, 0); ! 1272: return \"MVC %O0(%c2,%R0),%1\"; ! 1273: }") ! 1274: ! 1275: ; Move a block that is larger than 255 bytes in length. ! 1276: ! 1277: (define_insn "" ! 1278: [(set (match_operand:BLK 0 "general_operand" "=m") ! 1279: (match_operand:BLK 1 "general_operand" "m")) ! 1280: (use (match_operand:DI 2 "register_operand" "d")) ! 1281: (use (match_operand:DI 3 "register_operand" "d")) ! 1282: (clobber (match_dup 2)) ! 1283: (clobber (match_dup 3))] ! 1284: "" ! 1285: "* ! 1286: { ! 1287: check_label_emit (); ! 1288: mvs_check_page (0, 10, 0); ! 1289: return \"LA %2,%0\;LA %3,%1\;MVCL %2,%3\"; ! 1290: }") ! 1291: ! 1292: ;; ! 1293: ;;- Conversion instructions. ! 1294: ;; ! 1295: ! 1296: ; ! 1297: ; extendsidi2 instruction pattern(s). ! 1298: ; ! 1299: ! 1300: (define_expand "extendsidi2" ! 1301: [(set (match_operand:DI 0 "general_operand" "") ! 1302: (sign_extend:DI (match_operand:SI 1 "general_operand" "")))] ! 1303: "" ! 1304: " ! 1305: { ! 1306: if (GET_CODE (operands[1]) != CONST_INT) ! 1307: { ! 1308: emit_insn (gen_rtx (SET, VOIDmode, ! 1309: operand_subword (operands[0], 0, 1, DImode), operands[1])); ! 1310: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 1311: gen_rtx (ASHIFTRT, DImode, operands[0], ! 1312: gen_rtx (CONST_INT, SImode, 32)))); ! 1313: } ! 1314: else ! 1315: { ! 1316: if (INTVAL (operands[1]) < 0) ! 1317: { ! 1318: emit_insn (gen_rtx (SET, VOIDmode, ! 1319: operand_subword (operands[0], 0, 1, DImode), ! 1320: gen_rtx (CONST_INT, SImode, -1))); ! 1321: } ! 1322: else ! 1323: { ! 1324: emit_insn (gen_rtx (SET, VOIDmode, ! 1325: operand_subword (operands[0], 0, 1, DImode), ! 1326: gen_rtx (CONST_INT, SImode, 0))); ! 1327: } ! 1328: emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (SImode, operands[0]), ! 1329: operands[1])); ! 1330: } ! 1331: DONE; ! 1332: }") ! 1333: ! 1334: ; ! 1335: ; extendhisi2 instruction pattern(s). ! 1336: ; ! 1337: ! 1338: (define_insn "extendhisi2" ! 1339: [(set (match_operand:SI 0 "general_operand" "=d,m") ! 1340: (sign_extend:SI (match_operand:HI 1 "general_operand" "g,d")))] ! 1341: "" ! 1342: "* ! 1343: { ! 1344: check_label_emit (); ! 1345: if (REG_P (operands[0])) ! 1346: { ! 1347: if (REG_P (operands[1])) ! 1348: if (REGNO (operands[0]) != REGNO (operands[1])) ! 1349: { ! 1350: mvs_check_page (0, 2, 0); ! 1351: return \"LR %0,%1\;SLL %0,16\;SRA %0,16\"; ! 1352: } ! 1353: else ! 1354: return \"\"; /* Should be empty. 16-bits regs are always 32-bits. */ ! 1355: if (operands[1] == const0_rtx) ! 1356: { ! 1357: CC_STATUS_INIT; ! 1358: mvs_check_page (0, 2, 0); ! 1359: return \"SLR %0,%0\"; ! 1360: } ! 1361: if (GET_CODE (operands[1]) == CONST_INT ! 1362: && (unsigned) INTVAL (operands[1]) < 4096) ! 1363: { ! 1364: mvs_check_page (0, 4, 0); ! 1365: return \"LA %0,%c1\"; ! 1366: } ! 1367: if (GET_CODE (operands[1]) == CONST_INT) ! 1368: { ! 1369: mvs_check_page (0, 4, 2); ! 1370: return \"LH %0,=H'%h1'\"; ! 1371: } ! 1372: mvs_check_page (0, 4, 0); ! 1373: return \"LH %0,%1\"; ! 1374: } ! 1375: mvs_check_page (0, 4, 0); ! 1376: return \"SLL %0,16\;SRA %0,16\;ST %1,%0\"; ! 1377: }") ! 1378: ! 1379: ; ! 1380: ; extendqisi2 instruction pattern(s). ! 1381: ; ! 1382: ! 1383: (define_insn "extendqisi2" ! 1384: [(set (match_operand:SI 0 "general_operand" "=d") ! 1385: (sign_extend:SI (match_operand:QI 1 "general_operand" "0mi")))] ! 1386: "" ! 1387: "* ! 1388: { ! 1389: check_label_emit (); ! 1390: CC_STATUS_SET (operands[0], operands[1]); ! 1391: if (REG_P (operands[1])) ! 1392: { ! 1393: mvs_check_page (0, 8, 0); ! 1394: return \"SLL %0,24\;SRA %0,24\"; ! 1395: } ! 1396: if (s_operand (operands[1])) ! 1397: { ! 1398: mvs_check_page (0, 8, 0); ! 1399: return \"ICM %0,8,%1\;SRA %0,24\"; ! 1400: } ! 1401: mvs_check_page (0, 12, 0); ! 1402: return \"IC %0,%1\;SLL %0,24\;SRA %0,24\"; ! 1403: }") ! 1404: ! 1405: ; ! 1406: ; extendqihi2 instruction pattern(s). ! 1407: ; ! 1408: ! 1409: (define_insn "extendqihi2" ! 1410: [(set (match_operand:HI 0 "general_operand" "=d") ! 1411: (sign_extend:HI (match_operand:QI 1 "general_operand" "0m")))] ! 1412: "" ! 1413: "* ! 1414: { ! 1415: check_label_emit (); ! 1416: CC_STATUS_SET (operands[0], operands[1]); ! 1417: if (REG_P (operands[1])) ! 1418: { ! 1419: mvs_check_page (0, 8, 0); ! 1420: return \"SLL %0,24\;SRA %0,24\"; ! 1421: } ! 1422: if (s_operand (operands[1])) ! 1423: { ! 1424: mvs_check_page (0, 8, 0); ! 1425: return \"ICM %0,8,%1\;SRA %0,24\"; ! 1426: } ! 1427: mvs_check_page (0, 12, 0); ! 1428: return \"IC %0,%1\;SLL %0,24\;SRA %0,24\"; ! 1429: }") ! 1430: ! 1431: ; ! 1432: ; zero_extendsidi2 instruction pattern(s). ! 1433: ; ! 1434: ! 1435: (define_expand "zero_extendsidi2" ! 1436: [(set (match_operand:DI 0 "general_operand" "") ! 1437: (zero_extend:DI (match_operand:SI 1 "general_operand" "")))] ! 1438: "" ! 1439: " ! 1440: { ! 1441: emit_insn (gen_rtx (SET, VOIDmode, ! 1442: operand_subword (operands[0], 0, 1, DImode), operands[1])); ! 1443: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 1444: gen_rtx (LSHIFTRT, DImode, operands[0], ! 1445: gen_rtx (CONST_INT, SImode, 32)))); ! 1446: DONE; ! 1447: }") ! 1448: ! 1449: ; ! 1450: ; zero_extendhisi2 instruction pattern(s). ! 1451: ; ! 1452: ! 1453: (define_insn "zero_extendhisi2" ! 1454: [(set (match_operand:SI 0 "general_operand" "=d") ! 1455: (zero_extend:SI (match_operand:HI 1 "general_operand" "0")))] ! 1456: "" ! 1457: "* ! 1458: { ! 1459: check_label_emit (); ! 1460: CC_STATUS_SET (operands[0], operands[1]); ! 1461: mvs_check_page (0, 4, 4); ! 1462: return \"N %1,=X'0000FFFF'\"; ! 1463: }") ! 1464: ! 1465: ; ! 1466: ; zero_extendqisi2 instruction pattern(s). ! 1467: ; ! 1468: ! 1469: (define_insn "zero_extendqisi2" ! 1470: [(set (match_operand:SI 0 "general_operand" "=d,&d") ! 1471: (zero_extend:SI (match_operand:QI 1 "general_operand" "0i,m")))] ! 1472: "" ! 1473: "* ! 1474: { ! 1475: check_label_emit (); ! 1476: if (REG_P (operands[1])) ! 1477: { ! 1478: CC_STATUS_SET (operands[0], operands[1]); ! 1479: mvs_check_page (0, 4, 4); ! 1480: return \"N %0,=X'000000FF'\"; ! 1481: } ! 1482: if (GET_CODE (operands[1]) == CONST_INT) ! 1483: { ! 1484: mvs_check_page (0, 4, 0); ! 1485: return \"LA %0,%c1\"; ! 1486: } ! 1487: CC_STATUS_INIT; ! 1488: mvs_check_page (0, 8, 0); ! 1489: return \"SLR %0,%0\;IC %0,%1\"; ! 1490: }") ! 1491: ! 1492: ; ! 1493: ; zero_extendqihi2 instruction pattern(s). ! 1494: ; ! 1495: ! 1496: (define_insn "zero_extendqihi2" ! 1497: [(set (match_operand:HI 0 "general_operand" "=d,&d") ! 1498: (zero_extend:HI (match_operand:QI 1 "general_operand" "0i,m")))] ! 1499: "" ! 1500: "* ! 1501: { ! 1502: check_label_emit (); ! 1503: if (REG_P (operands[1])) ! 1504: { ! 1505: CC_STATUS_SET (operands[0], operands[1]); ! 1506: mvs_check_page (0, 4, 4); ! 1507: return \"N %0,=X'000000FF'\"; ! 1508: } ! 1509: if (GET_CODE (operands[1]) == CONST_INT) ! 1510: { ! 1511: mvs_check_page (0, 4, 0); ! 1512: return \"LA %0,%c1\"; ! 1513: } ! 1514: CC_STATUS_INIT; ! 1515: mvs_check_page (0, 8, 0); ! 1516: return \"SLR %0,%0\;IC %0,%1\"; ! 1517: }") ! 1518: ! 1519: ; ! 1520: ; truncsihi2 instruction pattern(s). ! 1521: ; ! 1522: ! 1523: (define_insn "truncsihi2" ! 1524: [(set (match_operand:HI 0 "general_operand" "=d,m") ! 1525: (truncate:HI (match_operand:SI 1 "general_operand" "0,d")))] ! 1526: "" ! 1527: "* ! 1528: { ! 1529: check_label_emit (); ! 1530: if (REG_P (operands[0])) ! 1531: { ! 1532: CC_STATUS_SET (operands[0], operands[1]); ! 1533: mvs_check_page (0, 8, 0); ! 1534: return \"SLL %0,16\;SRA %0,16\"; ! 1535: } ! 1536: mvs_check_page (0, 4, 0); ! 1537: return \"STH %1,%0\"; ! 1538: }") ! 1539: ! 1540: ; ! 1541: ; fix_truncdfsi2 instruction pattern(s). ! 1542: ; ! 1543: ! 1544: (define_insn "fix_truncdfsi2" ! 1545: [(set (match_operand:SI 0 "general_operand" "=d") ! 1546: (fix:SI (truncate:DF (match_operand:DF 1 "general_operand" "f")))) ! 1547: (clobber (reg:DF 16))] ! 1548: "" ! 1549: "* ! 1550: { ! 1551: check_label_emit (); ! 1552: CC_STATUS_INIT; ! 1553: if (REGNO (operands[1]) == 16) ! 1554: { ! 1555: mvs_check_page (0, 12, 8); ! 1556: return \"AD 0,=XL8'4F08000000000000'\;STD 0,140(,13)\;L %0,144(,13)\"; ! 1557: } ! 1558: mvs_check_page (0, 14, 8); ! 1559: return \"LDR 0,%1\;AD 0,=XL8'4F08000000000000'\;STD 0,140(,13)\;L %0,144(,13)\"; ! 1560: }") ! 1561: ! 1562: ; ! 1563: ; floatsidf2 instruction pattern(s). ! 1564: ; ! 1565: ; Uses the float field of the TCA. ! 1566: ; ! 1567: ! 1568: (define_insn "floatsidf2" ! 1569: [(set (match_operand:DF 0 "general_operand" "=f") ! 1570: (float:DF (match_operand:SI 1 "general_operand" "d")))] ! 1571: "" ! 1572: "* ! 1573: { ! 1574: check_label_emit (); ! 1575: CC_STATUS_INIT; ! 1576: mvs_check_page (0, 16, 8); ! 1577: return \"ST %1,508(,12)\;XI 508(12),128\;LD %0,504(,12)\;SD %0,=XL8'4E00000080000000'\"; ! 1578: }") ! 1579: ! 1580: ; ! 1581: ; truncdfsf2 instruction pattern(s). ! 1582: ; ! 1583: ! 1584: (define_insn "truncdfsf2" ! 1585: [(set (match_operand:SF 0 "general_operand" "=f") ! 1586: (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))] ! 1587: "" ! 1588: "* ! 1589: { ! 1590: check_label_emit (); ! 1591: mvs_check_page (0, 2, 0); ! 1592: return \"LRER %0,%1\"; ! 1593: }") ! 1594: ! 1595: ; ! 1596: ; extendsfdf2 instruction pattern(s). ! 1597: ; ! 1598: ! 1599: (define_insn "extendsfdf2" ! 1600: [(set (match_operand:DF 0 "general_operand" "=f") ! 1601: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))] ! 1602: "" ! 1603: "* ! 1604: { ! 1605: check_label_emit (); ! 1606: CC_STATUS_SET (0, const0_rtx); ! 1607: if (FP_REG_P (operands[1])) ! 1608: { ! 1609: if (REGNO (operands[0]) == REGNO (operands[1])) ! 1610: { ! 1611: mvs_check_page (0, 10, 0); ! 1612: return \"STE %1,140(,13)\;SDR %0,%0\;LE %0,140(,13)\"; ! 1613: } ! 1614: mvs_check_page (0, 4, 0); ! 1615: return \"SDR %0,%0\;LER %0,%1\"; ! 1616: } ! 1617: mvs_check_page (0, 6, 0); ! 1618: return \"SDR %0,%0\;LE %0,%1\"; ! 1619: }") ! 1620: ! 1621: ;; ! 1622: ;;- Add instructions. ! 1623: ;; ! 1624: ! 1625: ; ! 1626: ; adddi3 instruction pattern(s). ! 1627: ; ! 1628: ! 1629: (define_expand "adddi3" ! 1630: [(set (match_operand:DI 0 "general_operand" "") ! 1631: (plus:DI (match_operand:DI 1 "general_operand" "") ! 1632: (match_operand:DI 2 "general_operand" "")))] ! 1633: "" ! 1634: " ! 1635: { ! 1636: rtx label = gen_label_rtx (); ! 1637: rtx op0_high = operand_subword (operands[0], 0, 1, DImode); ! 1638: rtx op0_low = gen_lowpart (SImode, operands[0]); ! 1639: ! 1640: emit_insn (gen_rtx (SET, VOIDmode, op0_high, ! 1641: gen_rtx (PLUS, SImode, ! 1642: operand_subword (operands[1], 0, 1, DImode), ! 1643: operand_subword (operands[2], 0, 1, DImode)))); ! 1644: emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, ! 1645: gen_rtx (SET, VOIDmode, op0_low, ! 1646: gen_rtx (PLUS, SImode, gen_lowpart (SImode, operands[1]), ! 1647: gen_lowpart (SImode, operands[2]))), ! 1648: gen_rtx (USE, VOIDmode, gen_rtx (LABEL_REF, VOIDmode, label))))); ! 1649: emit_insn (gen_rtx (SET, VOIDmode, op0_high, ! 1650: gen_rtx (PLUS, SImode, op0_high, ! 1651: gen_rtx (CONST_INT, SImode, 1)))); ! 1652: emit_label (label); ! 1653: DONE; ! 1654: }") ! 1655: ! 1656: (define_insn "" ! 1657: [(set (match_operand:SI 0 "general_operand" "=d") ! 1658: (plus:SI (match_operand:SI 1 "general_operand" "%0") ! 1659: (match_operand:SI 2 "general_operand" "g"))) ! 1660: (use (label_ref (match_operand 3 "" "")))] ! 1661: "" ! 1662: "* ! 1663: { ! 1664: int onpage; ! 1665: ! 1666: check_label_emit (); ! 1667: onpage = mvs_check_label (CODE_LABEL_NUMBER (operands[3])); ! 1668: if (REG_P (operands[2])) ! 1669: { ! 1670: if (!onpage) ! 1671: { ! 1672: mvs_check_page (0, 8, 4); ! 1673: return \"ALR %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; ! 1674: } ! 1675: if (mvs_check_page (0, 6, 0)) ! 1676: { ! 1677: mvs_check_page (0, 2, 4); ! 1678: return \"ALR %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; ! 1679: } ! 1680: return \"ALR %0,%2\;BC 12,%l3\"; ! 1681: } ! 1682: if (!onpage) ! 1683: { ! 1684: mvs_check_page (0, 10, 4); ! 1685: return \"AL %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; ! 1686: } ! 1687: if (mvs_check_page (0, 8 ,0)) ! 1688: { ! 1689: mvs_check_page (0, 2, 4); ! 1690: return \"AL %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; ! 1691: } ! 1692: return \"AL %0,%2\;BC 12,%l3\"; ! 1693: }") ! 1694: ! 1695: ; ! 1696: ; addsi3 instruction pattern(s). ! 1697: ; ! 1698: ; The following insn is used when it is known that operand one is an address, ! 1699: ; frame, stack or argument pointer, and operand two is a constant that is ! 1700: ; small enough to fit in the displacement field. ! 1701: ; Notice that we can't allow the frame pointer to used as a normal register ! 1702: ; because of this insn. ! 1703: ; ! 1704: ! 1705: (define_insn "" ! 1706: [(set (match_operand:SI 0 "register_operand" "=d") ! 1707: (plus:SI (match_operand:SI 1 "general_operand" "%a") ! 1708: (match_operand:SI 2 "immediate_operand" "J")))] ! 1709: "((REGNO (operands[1]) == FRAME_POINTER_REGNUM || REGNO (operands[1]) == ARG_POINTER_REGNUM || REGNO (operands[1]) == STACK_POINTER_REGNUM) && (unsigned) INTVAL (operands[2]) < 4096)" ! 1710: "* ! 1711: { ! 1712: check_label_emit (); ! 1713: CC_STATUS_INIT; ! 1714: mvs_check_page (0, 4, 0); ! 1715: return \"LA %0,%c2(,%1)\"; ! 1716: }") ! 1717: ! 1718: ; This insn handles additions that are relative to the frame pointer. ! 1719: ! 1720: (define_insn "" ! 1721: [(set (match_operand:SI 0 "register_operand" "=d") ! 1722: (plus:SI (match_operand:SI 1 "register_operand" "%a") ! 1723: (match_operand:SI 2 "immediate_operand" "i")))] ! 1724: "REGNO (operands[1]) == FRAME_POINTER_REGNUM" ! 1725: "* ! 1726: { ! 1727: check_label_emit (); ! 1728: if ((unsigned) INTVAL (operands[2]) < 4096) ! 1729: { ! 1730: mvs_check_page (0, 4, 0); ! 1731: return \"LA %0,%c2(,%1)\"; ! 1732: } ! 1733: if (REGNO (operands[1]) == REGNO (operands[0])) ! 1734: { ! 1735: mvs_check_page (0, 4, 0); ! 1736: return \"A %0,%2\"; ! 1737: } ! 1738: mvs_check_page (0, 6, 0); ! 1739: return \"L %0,%2\;AR %0,%1\"; ! 1740: }") ! 1741: ! 1742: (define_insn "addsi3" ! 1743: [(set (match_operand:SI 0 "general_operand" "=d") ! 1744: (plus:SI (match_operand:SI 1 "general_operand" "%0") ! 1745: (match_operand:SI 2 "general_operand" "g")))] ! 1746: "" ! 1747: "* ! 1748: { ! 1749: check_label_emit (); ! 1750: if (REG_P (operands[2])) ! 1751: { ! 1752: mvs_check_page (0, 2, 0); ! 1753: return \"AR %0,%2\"; ! 1754: } ! 1755: if (GET_CODE (operands[2]) == CONST_INT) ! 1756: { ! 1757: if (INTVAL (operands[2]) == -1) ! 1758: { ! 1759: CC_STATUS_INIT; ! 1760: mvs_check_page (0, 2, 0); ! 1761: return \"BCTR %0,0\"; ! 1762: } ! 1763: } ! 1764: mvs_check_page (0, 4, 0); ! 1765: return \"A %0,%2\"; ! 1766: }") ! 1767: ! 1768: ; ! 1769: ; addhi3 instruction pattern(s). ! 1770: ; ! 1771: ! 1772: (define_insn "addhi3" ! 1773: [(set (match_operand:HI 0 "general_operand" "=d") ! 1774: (plus:HI (match_operand:HI 1 "general_operand" "%0") ! 1775: (match_operand:HI 2 "general_operand" "dmi")))] ! 1776: "" ! 1777: "* ! 1778: { ! 1779: check_label_emit (); ! 1780: if (REG_P (operands[2])) ! 1781: { ! 1782: mvs_check_page (0, 2, 0); ! 1783: return \"STH %2,140(,13)\;AH %0,140(,13)\"; ! 1784: } ! 1785: if (GET_CODE (operands[2]) == CONST_INT) ! 1786: { ! 1787: if (INTVAL (operands[2]) == -1) ! 1788: { ! 1789: CC_STATUS_INIT; ! 1790: mvs_check_page (0, 2, 0); ! 1791: return \"BCTR %0,0\"; ! 1792: } ! 1793: mvs_check_page (0, 4, 2); ! 1794: return \"AH %0,=H'%h2'\"; ! 1795: } ! 1796: mvs_check_page (0, 4, 0); ! 1797: return \"AH %0,%2\"; ! 1798: }") ! 1799: ! 1800: ; ! 1801: ; addqi3 instruction pattern(s). ! 1802: ; ! 1803: ! 1804: (define_insn "addqi3" ! 1805: [(set (match_operand:QI 0 "general_operand" "=d") ! 1806: (plus:QI (match_operand:QI 1 "general_operand" "%a") ! 1807: (match_operand:QI 2 "general_operand" "ai")))] ! 1808: "" ! 1809: "* ! 1810: { ! 1811: check_label_emit (); ! 1812: CC_STATUS_INIT; ! 1813: mvs_check_page (0, 4, 0); ! 1814: if (REG_P (operands[2])) ! 1815: return \"LA %0,0(%1,%2)\"; ! 1816: return \"LA %0,%B2(,%1)\"; ! 1817: }") ! 1818: ! 1819: ; ! 1820: ; adddf3 instruction pattern(s). ! 1821: ; ! 1822: ! 1823: (define_insn "adddf3" ! 1824: [(set (match_operand:DF 0 "general_operand" "=f") ! 1825: (plus:DF (match_operand:DF 1 "general_operand" "%0") ! 1826: (match_operand:DF 2 "general_operand" "fmF")))] ! 1827: "" ! 1828: "* ! 1829: { ! 1830: check_label_emit (); ! 1831: if (FP_REG_P (operands[2])) ! 1832: { ! 1833: mvs_check_page (0, 2, 0); ! 1834: return \"ADR %0,%2\"; ! 1835: } ! 1836: mvs_check_page (0, 4, 0); ! 1837: return \"AD %0,%2\"; ! 1838: }") ! 1839: ! 1840: ; ! 1841: ; addsf3 instruction pattern(s). ! 1842: ; ! 1843: ! 1844: (define_insn "addsf3" ! 1845: [(set (match_operand:SF 0 "general_operand" "=f") ! 1846: (plus:SF (match_operand:SF 1 "general_operand" "%0") ! 1847: (match_operand:SF 2 "general_operand" "fmF")))] ! 1848: "" ! 1849: "* ! 1850: { ! 1851: check_label_emit (); ! 1852: if (FP_REG_P (operands[2])) ! 1853: { ! 1854: mvs_check_page (0, 2, 0); ! 1855: return \"AER %0,%2\"; ! 1856: } ! 1857: mvs_check_page (0, 4, 0); ! 1858: return \"AE %0,%2\"; ! 1859: }") ! 1860: ! 1861: ;; ! 1862: ;;- Subtract instructions. ! 1863: ;; ! 1864: ! 1865: ; ! 1866: ; subdi3 instruction pattern(s). ! 1867: ; ! 1868: ! 1869: (define_expand "subdi3" ! 1870: [(set (match_operand:DI 0 "general_operand" "") ! 1871: (minus:DI (match_operand:DI 1 "general_operand" "") ! 1872: (match_operand:DI 2 "general_operand" "")))] ! 1873: "" ! 1874: " ! 1875: { ! 1876: rtx label = gen_label_rtx (); ! 1877: rtx op0_high = operand_subword (operands[0], 0, 1, DImode); ! 1878: rtx op0_low = gen_lowpart (SImode, operands[0]); ! 1879: ! 1880: emit_insn (gen_rtx (SET, VOIDmode, op0_high, ! 1881: gen_rtx (MINUS, SImode, ! 1882: operand_subword (operands[1], 0, 1, DImode), ! 1883: operand_subword (operands[2], 0, 1, DImode)))); ! 1884: emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, ! 1885: gen_rtx (SET, VOIDmode, op0_low, ! 1886: gen_rtx (MINUS, SImode, ! 1887: gen_lowpart (SImode, operands[1]), ! 1888: gen_lowpart (SImode, operands[2]))), ! 1889: gen_rtx (USE, VOIDmode, ! 1890: gen_rtx (LABEL_REF, VOIDmode, label))))); ! 1891: emit_insn (gen_rtx (SET, VOIDmode, op0_high, ! 1892: gen_rtx (MINUS, SImode, op0_high, ! 1893: gen_rtx (CONST_INT, SImode, 1)))); ! 1894: emit_label (label); ! 1895: DONE; ! 1896: }") ! 1897: ! 1898: (define_insn "" ! 1899: [(set (match_operand:SI 0 "general_operand" "=d") ! 1900: (minus:SI (match_operand:SI 1 "general_operand" "0") ! 1901: (match_operand:SI 2 "general_operand" "g"))) ! 1902: (use (label_ref (match_operand 3 "" "")))] ! 1903: "" ! 1904: "* ! 1905: { ! 1906: int onpage; ! 1907: ! 1908: check_label_emit (); ! 1909: CC_STATUS_INIT; ! 1910: onpage = mvs_check_label (CODE_LABEL_NUMBER (operands[3])); ! 1911: if (REG_P (operands[2])) ! 1912: { ! 1913: if (!onpage) ! 1914: { ! 1915: mvs_check_page (0, 8, 4); ! 1916: return \"SLR %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; ! 1917: } ! 1918: if (mvs_check_page (0, 6, 0)) ! 1919: { ! 1920: mvs_check_page (0, 2, 4); ! 1921: return \"SLR %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; ! 1922: } ! 1923: return \"SLR %0,%2\;BC 12,%l3\"; ! 1924: } ! 1925: if (!onpage) ! 1926: { ! 1927: mvs_check_page (0, 10, 4); ! 1928: return \"SL %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; ! 1929: } ! 1930: if (mvs_check_page (0, 8, 0)) ! 1931: { ! 1932: mvs_check_page (0, 2, 4); ! 1933: return \"SL %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; ! 1934: } ! 1935: return \"SL %0,%2\;BC 12,%l3\"; ! 1936: }") ! 1937: ! 1938: ; ! 1939: ; subsi3 instruction pattern(s). ! 1940: ; ! 1941: ! 1942: (define_insn "subsi3" ! 1943: [(set (match_operand:SI 0 "general_operand" "=d") ! 1944: (minus:SI (match_operand:SI 1 "general_operand" "0") ! 1945: (match_operand:SI 2 "general_operand" "g")))] ! 1946: "" ! 1947: "* ! 1948: { ! 1949: check_label_emit (); ! 1950: if (REG_P (operands[2])) ! 1951: { ! 1952: mvs_check_page (0, 2, 0); ! 1953: return \"SR %0,%2\"; ! 1954: } ! 1955: if (operands[2] == const1_rtx) ! 1956: { ! 1957: CC_STATUS_INIT; ! 1958: mvs_check_page (0, 2, 0); ! 1959: return \"BCTR %0,0\"; ! 1960: } ! 1961: mvs_check_page (0, 4, 0); ! 1962: return \"S %0,%2\"; ! 1963: }") ! 1964: ! 1965: ; ! 1966: ; subhi3 instruction pattern(s). ! 1967: ; ! 1968: ! 1969: (define_insn "subhi3" ! 1970: [(set (match_operand:HI 0 "general_operand" "=d") ! 1971: (minus:HI (match_operand:HI 1 "general_operand" "0") ! 1972: (match_operand:HI 2 "general_operand" "g")))] ! 1973: "" ! 1974: "* ! 1975: { ! 1976: check_label_emit (); ! 1977: if (REG_P (operands[2])) ! 1978: { ! 1979: mvs_check_page (0, 2, 0); ! 1980: return \"STH %2,140(,13)\;SH %0,140(,13)\"; ! 1981: } ! 1982: if (operands[2] == const1_rtx) ! 1983: { ! 1984: CC_STATUS_INIT; ! 1985: mvs_check_page (0, 2, 0); ! 1986: return \"BCTR %0,0\"; ! 1987: } ! 1988: if (GET_CODE (operands[2]) == CONST_INT) ! 1989: { ! 1990: mvs_check_page (0, 4, 2); ! 1991: return \"SH %0,=H'%h2'\"; ! 1992: } ! 1993: mvs_check_page (0, 4, 0); ! 1994: return \"SH %0,%2\"; ! 1995: }") ! 1996: ! 1997: ; ! 1998: ; subqi3 instruction pattern(s). ! 1999: ; ! 2000: ! 2001: (define_expand "subqi3" ! 2002: [(set (match_operand:QI 0 "general_operand" "=d") ! 2003: (minus:QI (match_operand:QI 1 "general_operand" "%0") ! 2004: (match_operand:QI 2 "general_operand" "di")))] ! 2005: "" ! 2006: " ! 2007: { ! 2008: if (REG_P (operands[2])) ! 2009: { ! 2010: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 2011: gen_rtx (MINUS, QImode, operands[1], operands[2]))); ! 2012: } ! 2013: else ! 2014: { ! 2015: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 2016: gen_rtx (PLUS, QImode, operands[1], ! 2017: negate_rtx (QImode, operands[2])))); ! 2018: } ! 2019: DONE; ! 2020: }") ! 2021: ! 2022: (define_insn "" ! 2023: [(set (match_operand:QI 0 "register_operand" "=d") ! 2024: (minus:QI (match_operand:QI 1 "register_operand" "%0") ! 2025: (match_operand:QI 2 "register_operand" "d")))] ! 2026: "" ! 2027: "* ! 2028: { ! 2029: check_label_emit (); ! 2030: CC_STATUS_INIT; ! 2031: mvs_check_page (0, 2, 0); ! 2032: return \"SR %0,%2\"; ! 2033: }") ! 2034: ! 2035: ; ! 2036: ; subdf3 instruction pattern(s). ! 2037: ; ! 2038: ! 2039: (define_insn "subdf3" ! 2040: [(set (match_operand:DF 0 "general_operand" "=f") ! 2041: (minus:DF (match_operand:DF 1 "general_operand" "0") ! 2042: (match_operand:DF 2 "general_operand" "fmF")))] ! 2043: "" ! 2044: "* ! 2045: { ! 2046: check_label_emit (); ! 2047: if (FP_REG_P (operands[2])) ! 2048: { ! 2049: mvs_check_page (0, 2, 0); ! 2050: return \"SDR %0,%2\"; ! 2051: } ! 2052: mvs_check_page (0, 4, 0); ! 2053: return \"SD %0,%2\"; ! 2054: }") ! 2055: ! 2056: ; ! 2057: ; subsf3 instruction pattern(s). ! 2058: ; ! 2059: ! 2060: (define_insn "subsf3" ! 2061: [(set (match_operand:SF 0 "general_operand" "=f") ! 2062: (minus:SF (match_operand:SF 1 "general_operand" "0") ! 2063: (match_operand:SF 2 "general_operand" "fmF")))] ! 2064: "" ! 2065: "* ! 2066: { ! 2067: check_label_emit (); ! 2068: if (FP_REG_P (operands[2])) ! 2069: { ! 2070: mvs_check_page (0, 2, 0); ! 2071: return \"SER %0,%2\"; ! 2072: } ! 2073: mvs_check_page (0, 4, 0); ! 2074: return \"SE %0,%2\"; ! 2075: }") ! 2076: ! 2077: ;; ! 2078: ;;- Multiply instructions. ! 2079: ;; ! 2080: ! 2081: ; ! 2082: ; mulsi3 instruction pattern(s). ! 2083: ; ! 2084: ! 2085: (define_expand "mulsi3" ! 2086: [(set (match_operand:SI 0 "general_operand" "") ! 2087: (mult:SI (match_operand:SI 1 "general_operand" "") ! 2088: (match_operand:SI 2 "general_operand" "")))] ! 2089: "" ! 2090: " ! 2091: { ! 2092: if (GET_CODE (operands[1]) == CONST_INT ! 2093: && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')) ! 2094: { ! 2095: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 2096: gen_rtx (MULT, SImode, operands[2], operands[1]))); ! 2097: } ! 2098: else if (GET_CODE (operands[2]) == CONST_INT ! 2099: && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')) ! 2100: { ! 2101: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 2102: gen_rtx (MULT, SImode, operands[1], operands[2]))); ! 2103: } ! 2104: else ! 2105: { ! 2106: rtx r = gen_reg_rtx (DImode); ! 2107: ! 2108: emit_insn (gen_rtx (SET, VOIDmode, ! 2109: gen_rtx (SUBREG, SImode, r, 1), operands[1])); ! 2110: emit_insn (gen_rtx (SET, VOIDmode, r, ! 2111: gen_rtx (MULT, SImode, r, operands[2]))); ! 2112: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 2113: gen_rtx (SUBREG, SImode, r, 1))); ! 2114: } ! 2115: DONE; ! 2116: }") ! 2117: ! 2118: (define_insn "" ! 2119: [(set (match_operand:SI 0 "register_operand" "=d") ! 2120: (mult:SI (match_operand:SI 1 "general_operand" "%0") ! 2121: (match_operand:SI 2 "immediate_operand" "K")))] ! 2122: "" ! 2123: "* ! 2124: { ! 2125: check_label_emit (); ! 2126: mvs_check_page (0, 4, 0); ! 2127: return \"MH %0,%2\"; ! 2128: }") ! 2129: ! 2130: (define_insn "" ! 2131: [(set (match_operand:DI 0 "register_operand" "=d") ! 2132: (mult:SI (match_operand:DI 1 "general_operand" "%0") ! 2133: (match_operand:SI 2 "general_operand" "g")))] ! 2134: "" ! 2135: "* ! 2136: { ! 2137: check_label_emit (); ! 2138: if (REG_P (operands[2])) ! 2139: { ! 2140: mvs_check_page (0, 2, 0); ! 2141: return \"MR %0,%2\"; ! 2142: } ! 2143: mvs_check_page (0, 4, 0); ! 2144: return \"M %0,%2\"; ! 2145: }") ! 2146: ! 2147: ; ! 2148: ; muldf3 instruction pattern(s). ! 2149: ; ! 2150: ! 2151: (define_insn "muldf3" ! 2152: [(set (match_operand:DF 0 "general_operand" "=f") ! 2153: (mult:DF (match_operand:DF 1 "general_operand" "%0") ! 2154: (match_operand:DF 2 "general_operand" "fmF")))] ! 2155: "" ! 2156: "* ! 2157: { ! 2158: check_label_emit (); ! 2159: if (FP_REG_P (operands[2])) ! 2160: { ! 2161: mvs_check_page (0, 2, 0); ! 2162: return \"MDR %0,%2\"; ! 2163: } ! 2164: mvs_check_page (0, 4, 0); ! 2165: return \"MD %0,%2\"; ! 2166: }") ! 2167: ! 2168: ; ! 2169: ; mulsf3 instruction pattern(s). ! 2170: ; ! 2171: ! 2172: (define_insn "mulsf3" ! 2173: [(set (match_operand:SF 0 "general_operand" "=f") ! 2174: (mult:SF (match_operand:SF 1 "general_operand" "%0") ! 2175: (match_operand:SF 2 "general_operand" "fmF")))] ! 2176: "" ! 2177: "* ! 2178: { ! 2179: check_label_emit (); ! 2180: if (FP_REG_P (operands[2])) ! 2181: { ! 2182: mvs_check_page (0, 2, 0); ! 2183: return \"MER %0,%2\"; ! 2184: } ! 2185: mvs_check_page (0, 4, 0); ! 2186: return \"ME %0,%2\"; ! 2187: }") ! 2188: ! 2189: ;; ! 2190: ;;- Divide instructions. ! 2191: ;; ! 2192: ! 2193: ; ! 2194: ; divsi3 instruction pattern(s). ! 2195: ; ! 2196: ! 2197: (define_expand "divsi3" ! 2198: [(set (match_operand:SI 0 "general_operand" "") ! 2199: (div:SI (match_operand:SI 1 "general_operand" "") ! 2200: (match_operand:SI 2 "general_operand" "")))] ! 2201: "" ! 2202: " ! 2203: { ! 2204: rtx r = gen_reg_rtx (DImode); ! 2205: ! 2206: emit_insn (gen_extendsidi2 (r, operands[1])); ! 2207: emit_insn (gen_rtx (SET, VOIDmode, r, ! 2208: gen_rtx (DIV, SImode, r, operands[2]))); ! 2209: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 2210: gen_rtx (SUBREG, SImode, r, 1))); ! 2211: DONE; ! 2212: }") ! 2213: ! 2214: ! 2215: ; ! 2216: ; udivsi3 instruction pattern(s). ! 2217: ; ! 2218: ! 2219: (define_expand "udivsi3" ! 2220: [(set (match_operand:SI 0 "general_operand" "") ! 2221: (udiv:SI (match_operand:SI 1 "general_operand" "") ! 2222: (match_operand:SI 2 "general_operand" "")))] ! 2223: "" ! 2224: " ! 2225: { ! 2226: rtx dr = gen_reg_rtx (DImode); ! 2227: rtx dr_0 = gen_rtx (SUBREG, SImode, dr, 0); ! 2228: rtx dr_1 = gen_rtx (SUBREG, SImode, dr, 1); ! 2229: ! 2230: ! 2231: if (GET_CODE (operands[2]) == CONST_INT) ! 2232: { ! 2233: if (INTVAL (operands[2]) > 0) ! 2234: { ! 2235: emit_insn (gen_zero_extendsidi2 (dr, operands[1])); ! 2236: emit_insn (gen_rtx (SET, VOIDmode, dr, ! 2237: gen_rtx (DIV, SImode, dr, operands[2]))); ! 2238: } ! 2239: else ! 2240: { ! 2241: rtx label1 = gen_label_rtx (); ! 2242: ! 2243: emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1])); ! 2244: emit_insn (gen_rtx (SET, VOIDmode, dr_1, const0_rtx)); ! 2245: emit_insn (gen_cmpsi (dr_0, operands[2])); ! 2246: emit_jump_insn (gen_bltu (label1)); ! 2247: emit_insn (gen_rtx (SET, VOIDmode, dr_1, const1_rtx)); ! 2248: emit_label (label1); ! 2249: } ! 2250: } ! 2251: else ! 2252: { ! 2253: rtx label1 = gen_label_rtx (); ! 2254: rtx label2 = gen_label_rtx (); ! 2255: rtx label3 = gen_label_rtx (); ! 2256: rtx sr = gen_reg_rtx (SImode); ! 2257: ! 2258: emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1])); ! 2259: emit_insn (gen_rtx (SET, VOIDmode, sr, operands[2])); ! 2260: emit_insn (gen_rtx (SET, VOIDmode, dr_1, const0_rtx)); ! 2261: emit_insn (gen_cmpsi (sr, dr_0)); ! 2262: emit_jump_insn (gen_bgtu (label3)); ! 2263: emit_insn (gen_cmpsi (sr, const1_rtx)); ! 2264: emit_jump_insn (gen_blt (label2)); ! 2265: emit_jump_insn (gen_beq (label1)); ! 2266: emit_insn (gen_rtx (SET, VOIDmode, dr, ! 2267: gen_rtx (LSHIFTRT, DImode, dr, ! 2268: gen_rtx (CONST_INT, SImode, 32)))); ! 2269: emit_insn (gen_rtx (SET, VOIDmode, dr, ! 2270: gen_rtx (DIV, SImode, dr, sr))); ! 2271: emit_jump_insn (gen_jump (label3)); ! 2272: emit_label (label1); ! 2273: emit_insn (gen_rtx (SET, VOIDmode, dr_1, dr_0)); ! 2274: emit_jump_insn (gen_jump (label3)); ! 2275: emit_label (label2); ! 2276: emit_insn (gen_rtx (SET, VOIDmode, dr_1, const1_rtx)); ! 2277: emit_label (label3); ! 2278: } ! 2279: emit_insn (gen_rtx (SET, VOIDmode, operands[0], dr_1)); ! 2280: ! 2281: DONE; ! 2282: }") ! 2283: ! 2284: ; This is used by divsi3 & udivsi3. ! 2285: ! 2286: (define_insn "" ! 2287: [(set (match_operand:DI 0 "register_operand" "=d") ! 2288: (div:SI (match_operand:DI 1 "register_operand" "0") ! 2289: (match_operand:SI 2 "general_operand" "")))] ! 2290: "" ! 2291: "* ! 2292: { ! 2293: check_label_emit (); ! 2294: if (REG_P (operands[2])) ! 2295: { ! 2296: mvs_check_page (0, 2, 0); ! 2297: return \"DR %0,%2\"; ! 2298: } ! 2299: mvs_check_page (0, 4, 0); ! 2300: return \"D %0,%2\"; ! 2301: }") ! 2302: ! 2303: ; ! 2304: ; divdf3 instruction pattern(s). ! 2305: ; ! 2306: ! 2307: (define_insn "divdf3" ! 2308: [(set (match_operand:DF 0 "general_operand" "=f") ! 2309: (div:DF (match_operand:DF 1 "general_operand" "0") ! 2310: (match_operand:DF 2 "general_operand" "fmF")))] ! 2311: "" ! 2312: "* ! 2313: { ! 2314: check_label_emit (); ! 2315: if (FP_REG_P (operands[2])) ! 2316: { ! 2317: mvs_check_page (0, 2, 0); ! 2318: return \"DDR %0,%2\"; ! 2319: } ! 2320: mvs_check_page (0, 4, 0); ! 2321: return \"DD %0,%2\"; ! 2322: }") ! 2323: ! 2324: ; ! 2325: ; divsf3 instruction pattern(s). ! 2326: ; ! 2327: ! 2328: (define_insn "divsf3" ! 2329: [(set (match_operand:SF 0 "general_operand" "=f") ! 2330: (div:SF (match_operand:SF 1 "general_operand" "0") ! 2331: (match_operand:SF 2 "general_operand" "fmF")))] ! 2332: "" ! 2333: "* ! 2334: { ! 2335: check_label_emit (); ! 2336: if (FP_REG_P (operands[2])) ! 2337: { ! 2338: mvs_check_page (0, 2, 0); ! 2339: return \"DER %0,%2\"; ! 2340: } ! 2341: mvs_check_page (0, 4, 0); ! 2342: return \"DE %0,%2\"; ! 2343: }") ! 2344: ! 2345: ;; ! 2346: ;;- Modulo instructions. ! 2347: ;; ! 2348: ! 2349: ; ! 2350: ; modsi3 instruction pattern(s). ! 2351: ; ! 2352: ! 2353: (define_expand "modsi3" ! 2354: [(set (match_operand:SI 0 "general_operand" "") ! 2355: (mod:SI (match_operand:SI 1 "general_operand" "") ! 2356: (match_operand:SI 2 "general_operand" "")))] ! 2357: "" ! 2358: " ! 2359: { ! 2360: rtx r = gen_reg_rtx (DImode); ! 2361: ! 2362: emit_insn (gen_extendsidi2 (r, operands[1])); ! 2363: emit_insn (gen_rtx (SET, VOIDmode, r, ! 2364: gen_rtx (MOD, SImode, r, operands[2]))); ! 2365: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 2366: gen_rtx (SUBREG, SImode, r, 0))); ! 2367: DONE; ! 2368: }") ! 2369: ! 2370: ; ! 2371: ; umodsi3 instruction pattern(s). ! 2372: ; ! 2373: ! 2374: (define_expand "umodsi3" ! 2375: [(set (match_operand:SI 0 "general_operand" "") ! 2376: (umod:SI (match_operand:SI 1 "general_operand" "") ! 2377: (match_operand:SI 2 "general_operand" "")))] ! 2378: "" ! 2379: " ! 2380: { ! 2381: rtx dr = gen_reg_rtx (DImode); ! 2382: rtx dr_0 = gen_rtx (SUBREG, SImode, dr, 0); ! 2383: rtx dr_1 = gen_rtx (SUBREG, SImode, dr, 1); ! 2384: ! 2385: emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1])); ! 2386: ! 2387: if (GET_CODE (operands[2]) == CONST_INT) ! 2388: { ! 2389: if (INTVAL (operands[2]) > 0) ! 2390: { ! 2391: emit_insn (gen_rtx (SET, VOIDmode, dr, ! 2392: gen_rtx (LSHIFTRT, DImode, dr, ! 2393: gen_rtx (CONST_INT, SImode, 32)))); ! 2394: emit_insn (gen_rtx (SET, VOIDmode, dr, ! 2395: gen_rtx (MOD, SImode, dr, operands[2]))); ! 2396: } ! 2397: else ! 2398: { ! 2399: rtx label1 = gen_label_rtx (); ! 2400: rtx sr = gen_reg_rtx (SImode); ! 2401: ! 2402: emit_insn (gen_rtx (SET, VOIDmode, sr, operands[2])); ! 2403: emit_insn (gen_cmpsi (dr_0, sr)); ! 2404: emit_jump_insn (gen_bltu (label1)); ! 2405: emit_insn (gen_rtx (SET, VOIDmode, sr, gen_rtx (ABS, SImode, sr))); ! 2406: emit_insn (gen_rtx (SET, VOIDmode, dr_0, ! 2407: gen_rtx (PLUS, SImode, dr_0, sr))); ! 2408: emit_label (label1); ! 2409: } ! 2410: } ! 2411: else ! 2412: { ! 2413: rtx label1 = gen_label_rtx (); ! 2414: rtx label2 = gen_label_rtx (); ! 2415: rtx label3 = gen_label_rtx (); ! 2416: rtx sr = gen_reg_rtx (SImode); ! 2417: ! 2418: emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1])); ! 2419: emit_insn (gen_rtx (SET, VOIDmode, sr, operands[2])); ! 2420: emit_insn (gen_cmpsi (sr, dr_0)); ! 2421: emit_jump_insn (gen_bgtu (label3)); ! 2422: emit_insn (gen_cmpsi (sr, const1_rtx)); ! 2423: emit_jump_insn (gen_blt (label2)); ! 2424: emit_jump_insn (gen_beq (label1)); ! 2425: emit_insn (gen_rtx (SET, VOIDmode, dr, ! 2426: gen_rtx (LSHIFTRT, DImode, dr, ! 2427: gen_rtx (CONST_INT, SImode, 32)))); ! 2428: emit_insn (gen_rtx (SET, VOIDmode, dr, gen_rtx (MOD, SImode, dr, sr))); ! 2429: emit_jump_insn (gen_jump (label3)); ! 2430: emit_label (label1); ! 2431: emit_insn (gen_rtx (SET, VOIDmode, dr_0, const0_rtx)); ! 2432: emit_jump_insn (gen_jump (label3)); ! 2433: emit_label (label2); ! 2434: emit_insn (gen_rtx (SET, VOIDmode, dr_0, ! 2435: gen_rtx (MINUS, SImode, dr_0, sr))); ! 2436: emit_label (label3); ! 2437: ! 2438: } ! 2439: emit_insn (gen_rtx (SET, VOIDmode, operands[0], dr_0)); ! 2440: ! 2441: DONE; ! 2442: }") ! 2443: ! 2444: ; This is used by modsi3 & umodsi3. ! 2445: ! 2446: (define_insn "" ! 2447: [(set (match_operand:DI 0 "register_operand" "=d") ! 2448: (mod:SI (match_operand:DI 1 "register_operand" "0") ! 2449: (match_operand:SI 2 "general_operand" "")))] ! 2450: "" ! 2451: "* ! 2452: { ! 2453: check_label_emit (); ! 2454: if (REG_P (operands[2])) ! 2455: { ! 2456: mvs_check_page (0, 2, 0); ! 2457: return \"DR %0,%2\"; ! 2458: } ! 2459: mvs_check_page (0, 4, 0); ! 2460: return \"D %0,%2\"; ! 2461: }") ! 2462: ! 2463: ;; ! 2464: ;;- And instructions. ! 2465: ;; ! 2466: ! 2467: ; ! 2468: ; anddi3 instruction pattern(s). ! 2469: ; ! 2470: ! 2471: ;(define_expand "anddi3" ! 2472: ; [(set (match_operand:DI 0 "general_operand" "") ! 2473: ; (and:DI (match_operand:DI 1 "general_operand" "") ! 2474: ; (match_operand:DI 2 "general_operand" "")))] ! 2475: ; "" ! 2476: ; " ! 2477: ;{ ! 2478: ; rtx gen_andsi3(); ! 2479: ; ! 2480: ; emit_insn (gen_andsi3 (operand_subword (operands[0], 0, 1, DImode), ! 2481: ; operand_subword (operands[1], 0, 1, DImode), ! 2482: ; operand_subword (operands[2], 0, 1, DImode))); ! 2483: ; emit_insn (gen_andsi3 (gen_lowpart (SImode, operands[0]), ! 2484: ; gen_lowpart (SImode, operands[1]), ! 2485: ; gen_lowpart (SImode, operands[2]))); ! 2486: ; DONE; ! 2487: ;}") ! 2488: ! 2489: ; ! 2490: ; andsi3 instruction pattern(s). ! 2491: ; ! 2492: ! 2493: (define_insn "" ! 2494: [(set (match_operand:SI 0 "r_or_s_operand" "=d,m") ! 2495: (and:SI (match_operand:SI 1 "r_or_s_operand" "%0,0") ! 2496: (match_operand:SI 2 "r_or_s_operand" "g,mi")))] ! 2497: "TARGET_CHAR_INSTRUCTIONS" ! 2498: "* ! 2499: { ! 2500: check_label_emit (); ! 2501: if (REG_P (operands[2])) ! 2502: { ! 2503: mvs_check_page (0, 2, 0); ! 2504: return \"NR %0,%2\"; ! 2505: } ! 2506: if (REG_P (operands[0])) ! 2507: { ! 2508: mvs_check_page (0, 4, 0); ! 2509: return \"N %0,%2\"; ! 2510: } ! 2511: CC_STATUS_INIT; ! 2512: mvs_check_page (0, 6, 0); ! 2513: return \"NC %O0(4,%R0),%2\"; ! 2514: }") ! 2515: ! 2516: (define_insn "andsi3" ! 2517: [(set (match_operand:SI 0 "general_operand" "=d") ! 2518: (and:SI (match_operand:SI 1 "general_operand" "%0") ! 2519: (match_operand:SI 2 "general_operand" "g")))] ! 2520: "" ! 2521: "* ! 2522: { ! 2523: check_label_emit (); ! 2524: if (REG_P (operands[2])) ! 2525: { ! 2526: mvs_check_page (0, 2, 0); ! 2527: return \"NR %0,%2\"; ! 2528: } ! 2529: mvs_check_page (0, 4, 0); ! 2530: return \"N %0,%2\"; ! 2531: }") ! 2532: ! 2533: ; ! 2534: ; andhi3 instruction pattern(s). ! 2535: ; ! 2536: ! 2537: (define_insn "" ! 2538: [(set (match_operand:HI 0 "r_or_s_operand" "=d,m") ! 2539: (and:HI (match_operand:HI 1 "r_or_s_operand" "%0,0") ! 2540: (match_operand:HI 2 "r_or_s_operand" "di,mi")))] ! 2541: "TARGET_CHAR_INSTRUCTIONS" ! 2542: "* ! 2543: { ! 2544: check_label_emit (); ! 2545: if (REG_P (operands[2])) ! 2546: { ! 2547: mvs_check_page (0, 2, 0); ! 2548: return \"NR %0,%2\"; ! 2549: } ! 2550: if (REG_P (operands[0])) ! 2551: { ! 2552: mvs_check_page (0, 4, 0); ! 2553: return \"N %0,%H2\"; ! 2554: } ! 2555: CC_STATUS_INIT; ! 2556: if (GET_CODE (operands[2]) == CONST_INT) ! 2557: { ! 2558: mvs_check_page (0, 6, 2); ! 2559: return \"NC %O0(2,%R0),=H'%h2'\"; ! 2560: } ! 2561: mvs_check_page (0, 6, 0); ! 2562: return \"NC %O0(2,%R0),%2\"; ! 2563: }") ! 2564: ! 2565: (define_insn "andhi3" ! 2566: [(set (match_operand:HI 0 "general_operand" "=d") ! 2567: (and:HI (match_operand:HI 1 "general_operand" "%0") ! 2568: (match_operand:HI 2 "general_operand" "di")))] ! 2569: "" ! 2570: "* ! 2571: { ! 2572: check_label_emit (); ! 2573: if (GET_CODE (operands[2]) == CONST_INT) ! 2574: { ! 2575: mvs_check_page (0, 4, 0); ! 2576: return \"N %0,%H2\"; ! 2577: } ! 2578: mvs_check_page (0, 2, 0); ! 2579: return \"NR %0,%2\"; ! 2580: }") ! 2581: ! 2582: ; ! 2583: ; andqi3 instruction pattern(s). ! 2584: ; ! 2585: ! 2586: (define_insn "" ! 2587: [(set (match_operand:QI 0 "r_or_s_operand" "=d,m") ! 2588: (and:QI (match_operand:QI 1 "r_or_s_operand" "%0,0") ! 2589: (match_operand:QI 2 "r_or_s_operand" "di,mi")))] ! 2590: "TARGET_CHAR_INSTRUCTIONS" ! 2591: "* ! 2592: { ! 2593: check_label_emit (); ! 2594: CC_STATUS_INIT; ! 2595: if (REG_P (operands[2])) ! 2596: { ! 2597: mvs_check_page (0, 2, 0); ! 2598: return \"NR %0,%2\"; ! 2599: } ! 2600: if (REG_P (operands[0])) ! 2601: { ! 2602: mvs_check_page (0, 4, 0); ! 2603: return \"N %0,%2\"; ! 2604: } ! 2605: if (GET_CODE (operands[2]) == CONST_INT) ! 2606: { ! 2607: mvs_check_page (0, 4, 0); ! 2608: return \"NI %0,%B2\"; ! 2609: } ! 2610: mvs_check_page (0, 6, 0); ! 2611: return \"NC %O0(1,%R0),%2\"; ! 2612: }") ! 2613: ! 2614: (define_insn "andqi3" ! 2615: [(set (match_operand:QI 0 "general_operand" "=d") ! 2616: (and:QI (match_operand:QI 1 "general_operand" "%0") ! 2617: (match_operand:QI 2 "general_operand" "di")))] ! 2618: "" ! 2619: "* ! 2620: { ! 2621: check_label_emit (); ! 2622: CC_STATUS_INIT; ! 2623: if (GET_CODE (operands[2]) == CONST_INT) ! 2624: { ! 2625: mvs_check_page (0, 4, 0); ! 2626: return \"N %0,%2\"; ! 2627: } ! 2628: mvs_check_page (0, 2, 0); ! 2629: return \"NR %0,%2\"; ! 2630: }") ! 2631: ! 2632: ;; ! 2633: ;;- Bit set (inclusive or) instructions. ! 2634: ;; ! 2635: ! 2636: ; ! 2637: ; iordi3 instruction pattern(s). ! 2638: ; ! 2639: ! 2640: ;(define_expand "iordi3" ! 2641: ; [(set (match_operand:DI 0 "general_operand" "") ! 2642: ; (ior:DI (match_operand:DI 1 "general_operand" "") ! 2643: ; (match_operand:DI 2 "general_operand" "")))] ! 2644: ; "" ! 2645: ; " ! 2646: ;{ ! 2647: ; rtx gen_iorsi3(); ! 2648: ; ! 2649: ; emit_insn (gen_iorsi3 (operand_subword (operands[0], 0, 1, DImode), ! 2650: ; operand_subword (operands[1], 0, 1, DImode), ! 2651: ; operand_subword (operands[2], 0, 1, DImode))); ! 2652: ; emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), ! 2653: ; gen_lowpart (SImode, operands[1]), ! 2654: ; gen_lowpart (SImode, operands[2]))); ! 2655: ; DONE; ! 2656: ;}") ! 2657: ! 2658: ; ! 2659: ; iorsi3 instruction pattern(s). ! 2660: ; ! 2661: ! 2662: (define_insn "" ! 2663: [(set (match_operand:SI 0 "r_or_s_operand" "=d,m") ! 2664: (ior:SI (match_operand:SI 1 "r_or_s_operand" "%0,0") ! 2665: (match_operand:SI 2 "r_or_s_operand" "g,mi")))] ! 2666: "TARGET_CHAR_INSTRUCTIONS" ! 2667: "* ! 2668: { ! 2669: check_label_emit (); ! 2670: if (REG_P (operands[2])) ! 2671: { ! 2672: mvs_check_page (0, 2, 0); ! 2673: return \"OR %0,%2\"; ! 2674: } ! 2675: if (REG_P (operands[0])) ! 2676: { ! 2677: mvs_check_page (0, 4, 0); ! 2678: return \"O %0,%2\"; ! 2679: } ! 2680: CC_STATUS_INIT; ! 2681: mvs_check_page (0, 6, 0); ! 2682: return \"OC %O0(4,%R0),%2\"; ! 2683: }") ! 2684: ! 2685: (define_insn "iorsi3" ! 2686: [(set (match_operand:SI 0 "general_operand" "=d") ! 2687: (ior:SI (match_operand:SI 1 "general_operand" "%0") ! 2688: (match_operand:SI 2 "general_operand" "g")))] ! 2689: "" ! 2690: "* ! 2691: { ! 2692: check_label_emit (); ! 2693: if (REG_P (operands[2])) ! 2694: { ! 2695: mvs_check_page (0, 2, 0); ! 2696: return \"OR %0,%2\"; ! 2697: } ! 2698: mvs_check_page (0, 4, 0); ! 2699: return \"O %0,%2\"; ! 2700: }") ! 2701: ! 2702: ; ! 2703: ; iorhi3 instruction pattern(s). ! 2704: ; ! 2705: ! 2706: (define_insn "" ! 2707: [(set (match_operand:HI 0 "r_or_s_operand" "=d,m") ! 2708: (ior:HI (match_operand:HI 1 "r_or_s_operand" "%0,0") ! 2709: (match_operand:HI 2 "r_or_s_operand" "di,mi")))] ! 2710: "TARGET_CHAR_INSTRUCTIONS" ! 2711: "* ! 2712: { ! 2713: check_label_emit (); ! 2714: if (REG_P (operands[2])) ! 2715: { ! 2716: mvs_check_page (0, 2, 0); ! 2717: return \"OR %0,%2\"; ! 2718: } ! 2719: if (REG_P (operands[0])) ! 2720: { ! 2721: mvs_check_page (0, 4, 0); ! 2722: return \"O %0,%H2\"; ! 2723: } ! 2724: CC_STATUS_INIT; ! 2725: if (GET_CODE (operands[2]) == CONST_INT) ! 2726: { ! 2727: mvs_check_page (0, 6, 2); ! 2728: return \"OC %O0(2,%R0),=H'%h2'\"; ! 2729: } ! 2730: mvs_check_page (0, 6, 0); ! 2731: return \"OC %O0(2,%R0),%2\"; ! 2732: }") ! 2733: ! 2734: (define_insn "iorhi3" ! 2735: [(set (match_operand:HI 0 "general_operand" "=d") ! 2736: (ior:HI (match_operand:HI 1 "general_operand" "%0") ! 2737: (match_operand:HI 2 "general_operand" "di")))] ! 2738: "" ! 2739: "* ! 2740: { ! 2741: check_label_emit (); ! 2742: if (GET_CODE (operands[2]) == CONST_INT) ! 2743: { ! 2744: mvs_check_page (0, 4, 0); ! 2745: return \"O %0,%H2\"; ! 2746: } ! 2747: mvs_check_page (0, 2, 0); ! 2748: return \"OR %0,%2\"; ! 2749: }") ! 2750: ! 2751: ; ! 2752: ; iorqi3 instruction pattern(s). ! 2753: ; ! 2754: ! 2755: (define_insn "" ! 2756: [(set (match_operand:QI 0 "r_or_s_operand" "=d,m") ! 2757: (ior:QI (match_operand:QI 1 "r_or_s_operand" "%0,0") ! 2758: (match_operand:QI 2 "r_or_s_operand" "di,mi")))] ! 2759: "TARGET_CHAR_INSTRUCTIONS" ! 2760: "* ! 2761: { ! 2762: check_label_emit (); ! 2763: CC_STATUS_INIT; ! 2764: if (REG_P (operands[2])) ! 2765: { ! 2766: mvs_check_page (0, 2, 0); ! 2767: return \"OR %0,%2\"; ! 2768: } ! 2769: if (REG_P (operands[0])) ! 2770: { ! 2771: mvs_check_page (0, 4, 0); ! 2772: return \"O %0,%2\"; ! 2773: } ! 2774: CC_STATUS_INIT; ! 2775: if (GET_CODE (operands[2]) == CONST_INT) ! 2776: { ! 2777: mvs_check_page (0, 4, 0); ! 2778: return \"OI %0,%B2\"; ! 2779: } ! 2780: mvs_check_page (0, 6, 0); ! 2781: return \"OC %O0(1,%R0),%2\"; ! 2782: }") ! 2783: ! 2784: (define_insn "iorqi3" ! 2785: [(set (match_operand:QI 0 "general_operand" "=d") ! 2786: (ior:QI (match_operand:QI 1 "general_operand" "%0") ! 2787: (match_operand:QI 2 "general_operand" "di")))] ! 2788: "" ! 2789: "* ! 2790: { ! 2791: check_label_emit (); ! 2792: CC_STATUS_INIT; ! 2793: if (GET_CODE (operands[2]) == CONST_INT) ! 2794: { ! 2795: mvs_check_page (0, 4, 0); ! 2796: return \"O %0,%2\"; ! 2797: } ! 2798: mvs_check_page (0, 2, 0); ! 2799: return \"OR %0,%2\"; ! 2800: }") ! 2801: ! 2802: ;; ! 2803: ;;- Xor instructions. ! 2804: ;; ! 2805: ! 2806: ; ! 2807: ; xordi3 instruction pattern(s). ! 2808: ; ! 2809: ! 2810: ;(define_expand "xordi3" ! 2811: ; [(set (match_operand:DI 0 "general_operand" "") ! 2812: ; (xor:DI (match_operand:DI 1 "general_operand" "") ! 2813: ; (match_operand:DI 2 "general_operand" "")))] ! 2814: ; "" ! 2815: ; " ! 2816: ;{ ! 2817: ; rtx gen_xorsi3(); ! 2818: ; ! 2819: ; emit_insn (gen_xorsi3 (operand_subword (operands[0], 0, 1, DImode), ! 2820: ; operand_subword (operands[1], 0, 1, DImode), ! 2821: ; operand_subword (operands[2], 0, 1, DImode))); ! 2822: ; emit_insn (gen_xorsi3 (gen_lowpart (SImode, operands[0]), ! 2823: ; gen_lowpart (SImode, operands[1]), ! 2824: ; gen_lowpart (SImode, operands[2]))); ! 2825: ; DONE; ! 2826: ;}") ! 2827: ! 2828: ; ! 2829: ; xorsi3 instruction pattern(s). ! 2830: ; ! 2831: ! 2832: (define_insn "" ! 2833: [(set (match_operand:SI 0 "r_or_s_operand" "=d,m") ! 2834: (xor:SI (match_operand:SI 1 "r_or_s_operand" "%0,0") ! 2835: (match_operand:SI 2 "r_or_s_operand" "g,mi")))] ! 2836: "TARGET_CHAR_INSTRUCTIONS" ! 2837: "* ! 2838: { ! 2839: check_label_emit (); ! 2840: if (REG_P (operands[2])) ! 2841: { ! 2842: mvs_check_page (0, 2, 0); ! 2843: return \"XR %0,%2\"; ! 2844: } ! 2845: if (REG_P (operands[0])) ! 2846: { ! 2847: mvs_check_page (0, 4, 0); ! 2848: return \"X %0,%2\"; ! 2849: } ! 2850: CC_STATUS_INIT; ! 2851: mvs_check_page (0, 6, 0); ! 2852: return \"XC %O0(4,%R0),%2\"; ! 2853: }") ! 2854: ! 2855: (define_insn "xorsi3" ! 2856: [(set (match_operand:SI 0 "general_operand" "=d") ! 2857: (xor:SI (match_operand:SI 1 "general_operand" "%0") ! 2858: (match_operand:SI 2 "general_operand" "g")))] ! 2859: "" ! 2860: "* ! 2861: { ! 2862: check_label_emit (); ! 2863: if (REG_P (operands[2])) ! 2864: { ! 2865: mvs_check_page (0, 2, 0); ! 2866: return \"XR %0,%2\"; ! 2867: } ! 2868: mvs_check_page (0, 4, 0); ! 2869: return \"X %0,%2\"; ! 2870: }") ! 2871: ! 2872: ; ! 2873: ; xorhi3 instruction pattern(s). ! 2874: ; ! 2875: ! 2876: (define_insn "" ! 2877: [(set (match_operand:HI 0 "r_or_s_operand" "=d,m") ! 2878: (xor:HI (match_operand:HI 1 "r_or_s_operand" "%0,0") ! 2879: (match_operand:HI 2 "r_or_s_operand" "di,mi")))] ! 2880: "TARGET_CHAR_INSTRUCTIONS" ! 2881: "* ! 2882: { ! 2883: check_label_emit (); ! 2884: if (REG_P (operands[2])) ! 2885: { ! 2886: mvs_check_page (0, 2, 0); ! 2887: return \"XR %0,%2\"; ! 2888: } ! 2889: if (REG_P (operands[0])) ! 2890: { ! 2891: mvs_check_page (0, 4, 0); ! 2892: return \"X %0,%H2\"; ! 2893: } ! 2894: CC_STATUS_INIT; ! 2895: if (GET_CODE (operands[2]) == CONST_INT) ! 2896: { ! 2897: mvs_check_page (0, 6, 2); ! 2898: return \"XC %O0(2,%R0),=H'%h2'\"; ! 2899: } ! 2900: mvs_check_page (0, 6, 0); ! 2901: return \"XC %O0(2,%R0),%2\"; ! 2902: }") ! 2903: ! 2904: (define_insn "xorhi3" ! 2905: [(set (match_operand:HI 0 "general_operand" "=d") ! 2906: (xor:HI (match_operand:HI 1 "general_operand" "%0") ! 2907: (match_operand:HI 2 "general_operand" "di")))] ! 2908: "" ! 2909: "* ! 2910: { ! 2911: check_label_emit (); ! 2912: if (GET_CODE (operands[2]) == CONST_INT) ! 2913: { ! 2914: mvs_check_page (0, 4, 0); ! 2915: return \"X %0,%2\"; ! 2916: } ! 2917: mvs_check_page (0, 2, 0); ! 2918: return \"XR %0,%2\"; ! 2919: }") ! 2920: ! 2921: ; ! 2922: ; xorqi3 instruction pattern(s). ! 2923: ; ! 2924: ! 2925: (define_insn "" ! 2926: [(set (match_operand:QI 0 "r_or_s_operand" "=d,m") ! 2927: (xor:QI (match_operand:QI 1 "r_or_s_operand" "%0,0") ! 2928: (match_operand:QI 2 "r_or_s_operand" "di,mi")))] ! 2929: "TARGET_CHAR_INSTRUCTIONS" ! 2930: "* ! 2931: { ! 2932: check_label_emit (); ! 2933: CC_STATUS_INIT; ! 2934: if (REG_P (operands[2])) ! 2935: { ! 2936: mvs_check_page (0, 2, 0); ! 2937: return \"XR %0,%2\"; ! 2938: } ! 2939: if (REG_P (operands[0])) ! 2940: { ! 2941: mvs_check_page (0, 4, 0); ! 2942: return \"X %0,%2\"; ! 2943: } ! 2944: if (GET_CODE (operands[2]) == CONST_INT) ! 2945: { ! 2946: mvs_check_page (0, 4, 0); ! 2947: return \"XI %0,%B2\"; ! 2948: } ! 2949: mvs_check_page (0, 6, 0); ! 2950: return \"XC %O0(1,%R0),%2\"; ! 2951: }") ! 2952: ! 2953: (define_insn "xorqi3" ! 2954: [(set (match_operand:QI 0 "general_operand" "=d") ! 2955: (xor:QI (match_operand:QI 1 "general_operand" "%0") ! 2956: (match_operand:QI 2 "general_operand" "di")))] ! 2957: "" ! 2958: "* ! 2959: { ! 2960: check_label_emit (); ! 2961: CC_STATUS_INIT; ! 2962: if (GET_CODE (operands[2]) == CONST_INT) ! 2963: { ! 2964: mvs_check_page (0, 4, 0); ! 2965: return \"X %0,%2\"; ! 2966: } ! 2967: mvs_check_page (0, 2, 0); ! 2968: return \"XR %0,%2\"; ! 2969: }") ! 2970: ! 2971: ;; ! 2972: ;;- Negate instructions. ! 2973: ;; ! 2974: ! 2975: ; ! 2976: ; negsi2 instruction pattern(s). ! 2977: ; ! 2978: ! 2979: (define_insn "negsi2" ! 2980: [(set (match_operand:SI 0 "general_operand" "=d") ! 2981: (neg:SI (match_operand:SI 1 "general_operand" "d")))] ! 2982: "" ! 2983: "* ! 2984: { ! 2985: check_label_emit (); ! 2986: mvs_check_page (0, 2, 0); ! 2987: return \"LCR %0,%1\"; ! 2988: }") ! 2989: ! 2990: ; ! 2991: ; neghi2 instruction pattern(s). ! 2992: ; ! 2993: ! 2994: (define_insn "neghi2" ! 2995: [(set (match_operand:HI 0 "general_operand" "=d") ! 2996: (neg:HI (match_operand:HI 1 "general_operand" "d")))] ! 2997: "" ! 2998: "* ! 2999: { ! 3000: check_label_emit (); ! 3001: mvs_check_page (0, 10, 0); ! 3002: return \"SLL %1,16\;SRA %1,16\;LCR %0,%1\"; ! 3003: }") ! 3004: ! 3005: ; ! 3006: ; negdf2 instruction pattern(s). ! 3007: ; ! 3008: ! 3009: (define_insn "negdf2" ! 3010: [(set (match_operand:DF 0 "general_operand" "=f") ! 3011: (neg:DF (match_operand:DF 1 "general_operand" "f")))] ! 3012: "" ! 3013: "* ! 3014: { ! 3015: check_label_emit (); ! 3016: mvs_check_page (0, 2, 0); ! 3017: return \"LCDR %0,%1\"; ! 3018: }") ! 3019: ! 3020: ; ! 3021: ; negsf2 instruction pattern(s). ! 3022: ; ! 3023: ! 3024: (define_insn "negsf2" ! 3025: [(set (match_operand:SF 0 "general_operand" "=f") ! 3026: (neg:SF (match_operand:SF 1 "general_operand" "f")))] ! 3027: "" ! 3028: "* ! 3029: { ! 3030: check_label_emit (); ! 3031: mvs_check_page (0, 2, 0); ! 3032: return \"LCER %0,%1\"; ! 3033: }") ! 3034: ! 3035: ;; ! 3036: ;;- Absolute value instructions. ! 3037: ;; ! 3038: ! 3039: ; ! 3040: ; abssi2 instruction pattern(s). ! 3041: ; ! 3042: ! 3043: (define_insn "abssi2" ! 3044: [(set (match_operand:SI 0 "general_operand" "=d") ! 3045: (abs:SI (match_operand:SI 1 "general_operand" "d")))] ! 3046: "" ! 3047: "* ! 3048: { ! 3049: check_label_emit (); ! 3050: mvs_check_page (0, 2, 0); ! 3051: return \"LPR %0,%1\"; ! 3052: }") ! 3053: ! 3054: ; ! 3055: ; abshi2 instruction pattern(s). ! 3056: ; ! 3057: ! 3058: (define_insn "abshi2" ! 3059: [(set (match_operand:HI 0 "general_operand" "=d") ! 3060: (abs:HI (match_operand:HI 1 "general_operand" "d")))] ! 3061: "" ! 3062: "* ! 3063: { ! 3064: check_label_emit (); ! 3065: mvs_check_page (0, 10, 0); ! 3066: return \"SLL %1,16\;SRA %1,16\;LPR %0,%1\"; ! 3067: }") ! 3068: ! 3069: ; ! 3070: ; absdf2 instruction pattern(s). ! 3071: ; ! 3072: ! 3073: (define_insn "absdf2" ! 3074: [(set (match_operand:DF 0 "general_operand" "=f") ! 3075: (abs:DF (match_operand:DF 1 "general_operand" "f")))] ! 3076: "" ! 3077: "* ! 3078: { ! 3079: check_label_emit (); ! 3080: mvs_check_page (0, 2, 0); ! 3081: return \"LPDR %0,%1\"; ! 3082: }") ! 3083: ! 3084: ; ! 3085: ; abssf2 instruction pattern(s). ! 3086: ; ! 3087: ! 3088: (define_insn "abssf2" ! 3089: [(set (match_operand:SF 0 "general_operand" "=f") ! 3090: (abs:SF (match_operand:SF 1 "general_operand" "f")))] ! 3091: "" ! 3092: "* ! 3093: { ! 3094: check_label_emit (); ! 3095: mvs_check_page (0, 2, 0); ! 3096: return \"LPER %0,%1\"; ! 3097: }") ! 3098: ! 3099: ;; ! 3100: ;;- One complement instructions. ! 3101: ;; ! 3102: ! 3103: ; ! 3104: ; one_cmpldi2 instruction pattern(s). ! 3105: ; ! 3106: ! 3107: ;(define_expand "one_cmpldi2" ! 3108: ; [(set (match_operand:DI 0 "general_operand" "") ! 3109: ; (not:DI (match_operand:DI 1 "general_operand" "")))] ! 3110: ; "" ! 3111: ; " ! 3112: ;{ ! 3113: ; rtx gen_one_cmplsi2(); ! 3114: ; ! 3115: ; emit_insn (gen_one_cmplsi2 (operand_subword (operands[0], 0, 1, DImode), ! 3116: ; operand_subword (operands[1], 0, 1, DImode))); ! 3117: ; emit_insn (gen_one_cmplsi2 (gen_lowpart (SImode, operands[0]), ! 3118: ; gen_lowpart (SImode, operands[1]))); ! 3119: ; DONE; ! 3120: ;}") ! 3121: ! 3122: ; ! 3123: ; one_cmplsi2 instruction pattern(s). ! 3124: ; ! 3125: ! 3126: (define_insn "" ! 3127: [(set (match_operand:SI 0 "r_or_s_operand" "=dm") ! 3128: (not:SI (match_operand:SI 1 "r_or_s_operand" "0")))] ! 3129: "TARGET_CHAR_INSTRUCTIONS" ! 3130: "* ! 3131: { ! 3132: check_label_emit (); ! 3133: if (REG_P (operands[0])) ! 3134: { ! 3135: mvs_check_page (0, 4, 4); ! 3136: return \"X %0,=F'-1'\"; ! 3137: } ! 3138: CC_STATUS_INIT; ! 3139: mvs_check_page (0, 6, 4); ! 3140: return \"XC %O0(4,%R0),=F'-1'\"; ! 3141: }") ! 3142: ! 3143: (define_insn "one_cmplsi2" ! 3144: [(set (match_operand:SI 0 "general_operand" "=d") ! 3145: (not:SI (match_operand:SI 1 "general_operand" "0")))] ! 3146: "" ! 3147: "* ! 3148: { ! 3149: check_label_emit (); ! 3150: mvs_check_page (0, 4, 4); ! 3151: return \"X %0,=F'-1'\"; ! 3152: }") ! 3153: ! 3154: ; ! 3155: ; one_cmplhi2 instruction pattern(s). ! 3156: ; ! 3157: ! 3158: (define_insn "" ! 3159: [(set (match_operand:HI 0 "r_or_s_operand" "=dm") ! 3160: (not:HI (match_operand:HI 1 "r_or_s_operand" "0")))] ! 3161: "TARGET_CHAR_INSTRUCTIONS" ! 3162: "* ! 3163: { ! 3164: check_label_emit (); ! 3165: if (REG_P (operands[0])) ! 3166: { ! 3167: mvs_check_page (0, 4, 4); ! 3168: return \"X %0,=F'-1'\"; ! 3169: } ! 3170: CC_STATUS_INIT; ! 3171: mvs_check_page (0, 6, 4); ! 3172: return \"XC %O0(2,%R0),=X'FFFF'\"; ! 3173: }") ! 3174: ! 3175: (define_insn "one_cmplhi2" ! 3176: [(set (match_operand:HI 0 "general_operand" "=d") ! 3177: (not:HI (match_operand:HI 1 "general_operand" "0")))] ! 3178: "" ! 3179: "* ! 3180: { ! 3181: check_label_emit (); ! 3182: mvs_check_page (0, 4, 4); ! 3183: return \"X %0,=F'-1'\"; ! 3184: }") ! 3185: ! 3186: ; ! 3187: ; one_cmplqi2 instruction pattern(s). ! 3188: ; ! 3189: ! 3190: (define_insn "" ! 3191: [(set (match_operand:QI 0 "r_or_s_operand" "=dm") ! 3192: (not:QI (match_operand:QI 1 "r_or_s_operand" "0")))] ! 3193: "TARGET_CHAR_INSTRUCTIONS" ! 3194: "* ! 3195: { ! 3196: check_label_emit (); ! 3197: CC_STATUS_INIT; ! 3198: if (REG_P (operands[0])) ! 3199: { ! 3200: mvs_check_page (0, 4, 4); ! 3201: return \"X %0,=F'-1'\"; ! 3202: } ! 3203: mvs_check_page (0, 4, 0); ! 3204: return \"XI %0,255\"; ! 3205: }") ! 3206: ! 3207: (define_insn "one_cmplqi2" ! 3208: [(set (match_operand:QI 0 "general_operand" "=d") ! 3209: (not:QI (match_operand:QI 1 "general_operand" "0")))] ! 3210: "" ! 3211: "* ! 3212: { ! 3213: check_label_emit (); ! 3214: CC_STATUS_INIT; ! 3215: mvs_check_page (0, 4, 4); ! 3216: return \"X %0,=F'-1'\"; ! 3217: }") ! 3218: ! 3219: ;; ! 3220: ;;- Arithmetic shift instructions. ! 3221: ;; ! 3222: ! 3223: ; ! 3224: ; ashldi3 instruction pattern(s). ! 3225: ; ! 3226: ! 3227: (define_insn "ashldi3" ! 3228: [(set (match_operand:DI 0 "general_operand" "=d") ! 3229: (ashift:DI (match_operand:DI 1 "general_operand" "0") ! 3230: (match_operand:SI 2 "general_operand" "Ja")))] ! 3231: "" ! 3232: "* ! 3233: { ! 3234: check_label_emit (); ! 3235: CC_STATUS_INIT; ! 3236: mvs_check_page (0, 4, 0); ! 3237: if (REG_P (operands[2])) ! 3238: return \"SLDA %0,0(%2)\"; ! 3239: return \"SLDA %0,%c2\"; ! 3240: }") ! 3241: ! 3242: ; ! 3243: ; ashrdi3 instruction pattern(s). ! 3244: ; ! 3245: ! 3246: (define_insn "ashrdi3" ! 3247: [(set (match_operand:DI 0 "register_operand" "=d") ! 3248: (ashiftrt:DI (match_operand:DI 1 "general_operand" "0") ! 3249: (match_operand:SI 2 "general_operand" "Ja")))] ! 3250: "" ! 3251: "* ! 3252: { ! 3253: check_label_emit (); ! 3254: mvs_check_page (0, 4, 0); ! 3255: if (REG_P (operands[2])) ! 3256: return \"SRDA %0,0(%2)\"; ! 3257: return \"SRDA %0,%c2\"; ! 3258: }") ! 3259: ! 3260: ; ! 3261: ; ashlsi3 instruction pattern(s). ! 3262: ; ! 3263: ! 3264: (define_insn "ashlsi3" ! 3265: [(set (match_operand:SI 0 "general_operand" "=d") ! 3266: (ashift:SI (match_operand:SI 1 "general_operand" "0") ! 3267: (match_operand:SI 2 "general_operand" "Ja")))] ! 3268: "" ! 3269: "* ! 3270: { ! 3271: check_label_emit (); ! 3272: CC_STATUS_INIT; ! 3273: mvs_check_page (0, 4, 0); ! 3274: if (REG_P (operands[2])) ! 3275: return \"SLL %0,0(%2)\"; ! 3276: return \"SLL %0,%c2\"; ! 3277: }") ! 3278: ! 3279: ; ! 3280: ; ashrsi3 instruction pattern(s). ! 3281: ; ! 3282: ! 3283: (define_insn "ashrsi3" ! 3284: [(set (match_operand:SI 0 "general_operand" "=d") ! 3285: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0") ! 3286: (match_operand:SI 2 "general_operand" "Ja")))] ! 3287: "" ! 3288: "* ! 3289: { ! 3290: check_label_emit (); ! 3291: mvs_check_page (0, 4, 0); ! 3292: if (REG_P (operands[2])) ! 3293: return \"SRA %0,0(%2)\"; ! 3294: return \"SRA %0,%c2\"; ! 3295: }") ! 3296: ! 3297: ; ! 3298: ; ashlhi3 instruction pattern(s). ! 3299: ; ! 3300: ! 3301: (define_insn "ashlhi3" ! 3302: [(set (match_operand:HI 0 "general_operand" "=d") ! 3303: (ashift:HI (match_operand:HI 1 "general_operand" "0") ! 3304: (match_operand:SI 2 "general_operand" "Ja")))] ! 3305: "" ! 3306: "* ! 3307: { ! 3308: check_label_emit (); ! 3309: mvs_check_page (0, 8, 0); ! 3310: if (REG_P (operands[2])) ! 3311: return \"SLL %0,16(%2)\;SRA %0,16\"; ! 3312: return \"SLL %0,16+%c2\;SRA %0,16\"; ! 3313: }") ! 3314: ! 3315: ; ! 3316: ; ashrhi3 instruction pattern(s). ! 3317: ; ! 3318: ! 3319: (define_insn "ashrhi3" ! 3320: [(set (match_operand:HI 0 "general_operand" "=d") ! 3321: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0") ! 3322: (match_operand:SI 2 "general_operand" "Ja")))] ! 3323: "" ! 3324: "* ! 3325: { ! 3326: check_label_emit (); ! 3327: mvs_check_page (0, 4, 0); ! 3328: if (REG_P (operands[2])) ! 3329: return \"SLL %0,16\;SRA %0,16(%2)\"; ! 3330: return \"SLL %0,16\;SRA %0,16+%c2\"; ! 3331: }") ! 3332: ! 3333: ; ! 3334: ; ashlqi3 instruction pattern(s). ! 3335: ; ! 3336: ! 3337: (define_insn "ashlqi3" ! 3338: [(set (match_operand:QI 0 "general_operand" "=d") ! 3339: (ashift:QI (match_operand:QI 1 "general_operand" "0") ! 3340: (match_operand:SI 2 "general_operand" "Ja")))] ! 3341: "" ! 3342: "* ! 3343: { ! 3344: check_label_emit (); ! 3345: CC_STATUS_INIT; ! 3346: mvs_check_page (0, 4, 0); ! 3347: if (REG_P (operands[2])) ! 3348: return \"SLL %0,0(%2)\"; ! 3349: return \"SLL %0,%c2\"; ! 3350: }") ! 3351: ! 3352: ; ! 3353: ; ashrqi3 instruction pattern(s). ! 3354: ; ! 3355: ! 3356: (define_insn "ashrqi3" ! 3357: [(set (match_operand:QI 0 "general_operand" "=d") ! 3358: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0") ! 3359: (match_operand:SI 2 "general_operand" "Ja")))] ! 3360: "" ! 3361: "* ! 3362: { ! 3363: check_label_emit (); ! 3364: mvs_check_page (0, 8, 0); ! 3365: if (REG_P (operands[2])) ! 3366: return \"SLL %0,24\;SRA %0,24(%2)\"; ! 3367: return \"SLL %0,24\;SRA %0,24+%c2\"; ! 3368: }") ! 3369: ! 3370: ;; ! 3371: ;;- Logical shift instructions. ! 3372: ;; ! 3373: ! 3374: ; ! 3375: ; lshldi3 instruction pattern(s). ! 3376: ; ! 3377: ! 3378: (define_insn "lshldi3" ! 3379: [(set (match_operand:DI 0 "general_operand" "=d") ! 3380: (lshift:DI (match_operand:DI 1 "general_operand" "0") ! 3381: (match_operand:SI 2 "general_operand" "Ja")))] ! 3382: "" ! 3383: "* ! 3384: { ! 3385: check_label_emit (); ! 3386: mvs_check_page (0, 4, 0); ! 3387: if (REG_P (operands[2])) ! 3388: return \"SLDL %0,0(%2)\"; ! 3389: return \"SLDL %0,%c2\"; ! 3390: }") ! 3391: ! 3392: ; ! 3393: ; lshrdi3 instruction pattern(s). ! 3394: ; ! 3395: ! 3396: (define_insn "lshrdi3" ! 3397: [(set (match_operand:DI 0 "general_operand" "=d") ! 3398: (lshiftrt:DI (match_operand:DI 1 "general_operand" "0") ! 3399: (match_operand:SI 2 "general_operand" "Ja")))] ! 3400: "" ! 3401: "* ! 3402: { ! 3403: check_label_emit (); ! 3404: mvs_check_page (0, 4, 0); ! 3405: if (REG_P (operands[2])) ! 3406: return \"SRDL %0,0(%2)\"; ! 3407: return \"SRDL %0,%c2\"; ! 3408: }") ! 3409: ! 3410: ; ! 3411: ; lshlsi3 instruction pattern(s). ! 3412: ; ! 3413: ! 3414: (define_insn "lshlsi3" ! 3415: [(set (match_operand:SI 0 "general_operand" "=d") ! 3416: (lshift:SI (match_operand:SI 1 "general_operand" "0") ! 3417: (match_operand:SI 2 "general_operand" "Ja")))] ! 3418: "" ! 3419: "* ! 3420: { ! 3421: check_label_emit (); ! 3422: mvs_check_page (0, 4, 0); ! 3423: if (REG_P (operands[2])) ! 3424: return \"SLL %0,0(%2)\"; ! 3425: return \"SLL %0,%c2\"; ! 3426: }") ! 3427: ! 3428: ; ! 3429: ; lshrsi3 instruction pattern(s). ! 3430: ; ! 3431: ! 3432: (define_insn "lshrsi3" ! 3433: [(set (match_operand:SI 0 "general_operand" "=d") ! 3434: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") ! 3435: (match_operand:SI 2 "general_operand" "Ja")))] ! 3436: "" ! 3437: "* ! 3438: { ! 3439: check_label_emit (); ! 3440: mvs_check_page (0, 4, 0); ! 3441: if (REG_P (operands[2])) ! 3442: return \"SRL %0,0(%2)\"; ! 3443: return \"SRL %0,%c2\"; ! 3444: }") ! 3445: ! 3446: ; ! 3447: ; lshlhi3 instruction pattern(s). ! 3448: ; ! 3449: ! 3450: (define_insn "lshlhi3" ! 3451: [(set (match_operand:HI 0 "general_operand" "=d") ! 3452: (lshift:HI (match_operand:HI 1 "general_operand" "0") ! 3453: (match_operand:SI 2 "general_operand" "Ja")))] ! 3454: "" ! 3455: "* ! 3456: { ! 3457: check_label_emit (); ! 3458: CC_STATUS_INIT; ! 3459: mvs_check_page (0, 4, 0); ! 3460: if (REG_P (operands[2])) ! 3461: return \"SLL %0,0(%2)\"; ! 3462: return \"SLL %0,%c2\"; ! 3463: }") ! 3464: ! 3465: ; ! 3466: ; lshrhi3 instruction pattern(s). ! 3467: ; ! 3468: ! 3469: (define_insn "lshrhi3" ! 3470: [(set (match_operand:HI 0 "general_operand" "=d") ! 3471: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") ! 3472: (match_operand:SI 2 "general_operand" "Ja")))] ! 3473: "" ! 3474: "* ! 3475: { ! 3476: check_label_emit (); ! 3477: CC_STATUS_INIT; ! 3478: if (REG_P (operands[2])) ! 3479: { ! 3480: mvs_check_page (0, 8, 4); ! 3481: return \"N %0,=X'0000FFFF'\;SRL %0,0(%2)\"; ! 3482: } ! 3483: mvs_check_page (0, 8, 4); ! 3484: return \"N %0,=X'0000FFFF'\;SRL %0,%c2\"; ! 3485: }") ! 3486: ! 3487: ; ! 3488: ; lshlqi3 instruction pattern(s). ! 3489: ; ! 3490: ! 3491: (define_insn "lshlqi3" ! 3492: [(set (match_operand:QI 0 "general_operand" "=d") ! 3493: (lshift:QI (match_operand:QI 1 "general_operand" "0") ! 3494: (match_operand:SI 2 "general_operand" "Ja")))] ! 3495: "" ! 3496: "* ! 3497: { ! 3498: check_label_emit (); ! 3499: mvs_check_page (0, 4, 0); ! 3500: if (REG_P (operands[2])) ! 3501: return \"SLL %0,0(%2)\"; ! 3502: return \"SLL %0,%c2\"; ! 3503: }") ! 3504: ! 3505: ; ! 3506: ; lshrqi3 instruction pattern(s). ! 3507: ; ! 3508: ! 3509: (define_insn "lshrqi3" ! 3510: [(set (match_operand:QI 0 "general_operand" "=d") ! 3511: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") ! 3512: (match_operand:SI 2 "general_operand" "Ja")))] ! 3513: "" ! 3514: "* ! 3515: { ! 3516: check_label_emit (); ! 3517: CC_STATUS_INIT; ! 3518: mvs_check_page (0, 8, 4); ! 3519: if (REG_P (operands[2])) ! 3520: return \"N %0,=X'000000FF'\;SRL %0,0(%2)\"; ! 3521: return \"N %0,=X'000000FF'\;SRL %0,%c2\"; ! 3522: }") ! 3523: ! 3524: ;; ! 3525: ;;- Conditional jump instructions. ! 3526: ;; ! 3527: ! 3528: ; ! 3529: ; beq instruction pattern(s). ! 3530: ; ! 3531: ! 3532: (define_insn "beq" ! 3533: [(set (pc) ! 3534: (if_then_else (eq (cc0) ! 3535: (const_int 0)) ! 3536: (label_ref (match_operand 0 "" "")) ! 3537: (pc)))] ! 3538: "" ! 3539: "* ! 3540: { ! 3541: check_label_emit (); ! 3542: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3543: { ! 3544: mvs_check_page (0, 6, 4); ! 3545: return \"L 14,=A(%l0)\;BER 14\"; ! 3546: } ! 3547: if (mvs_check_page (0, 4, 0)) ! 3548: { ! 3549: mvs_check_page (0, 2, 4); ! 3550: return \"L 14,=A(%l0)\;BER 14\"; ! 3551: } ! 3552: return \"BE %l0\"; ! 3553: }") ! 3554: ! 3555: ; ! 3556: ; bne instruction pattern(s). ! 3557: ; ! 3558: ! 3559: (define_insn "bne" ! 3560: [(set (pc) ! 3561: (if_then_else (ne (cc0) ! 3562: (const_int 0)) ! 3563: (label_ref (match_operand 0 "" "")) ! 3564: (pc)))] ! 3565: "" ! 3566: "* ! 3567: { ! 3568: check_label_emit (); ! 3569: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3570: { ! 3571: mvs_check_page (0, 6, 4); ! 3572: return \"L 14,=A(%l0)\;BNER 14\"; ! 3573: } ! 3574: if (mvs_check_page (0, 4, 0)) ! 3575: { ! 3576: mvs_check_page (0, 2, 4); ! 3577: return \"L 14,=A(%l0)\;BNER 14\"; ! 3578: } ! 3579: return \"BNE %l0\"; ! 3580: }") ! 3581: ! 3582: ; ! 3583: ; bgt instruction pattern(s). ! 3584: ; ! 3585: ! 3586: (define_insn "bgt" ! 3587: [(set (pc) ! 3588: (if_then_else (gt (cc0) ! 3589: (const_int 0)) ! 3590: (label_ref (match_operand 0 "" "")) ! 3591: (pc)))] ! 3592: "" ! 3593: "* ! 3594: { ! 3595: check_label_emit (); ! 3596: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3597: { ! 3598: mvs_check_page (0, 6, 4); ! 3599: return \"L 14,=A(%l0)\;BHR 14\"; ! 3600: } ! 3601: if (mvs_check_page (0, 4, 0)) ! 3602: { ! 3603: mvs_check_page (0, 2, 4); ! 3604: return \"L 14,=A(%l0)\;BHR 14\"; ! 3605: } ! 3606: return \"BH %l0\"; ! 3607: }") ! 3608: ! 3609: ; ! 3610: ; bgtu instruction pattern(s). ! 3611: ; ! 3612: ! 3613: (define_insn "bgtu" ! 3614: [(set (pc) ! 3615: (if_then_else (gtu (cc0) ! 3616: (const_int 0)) ! 3617: (label_ref (match_operand 0 "" "")) ! 3618: (pc)))] ! 3619: "" ! 3620: "* ! 3621: { ! 3622: check_label_emit (); ! 3623: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3624: { ! 3625: mvs_check_page (0, 6, 4); ! 3626: return \"L 14,=A(%l0)\;BHR 14\"; ! 3627: } ! 3628: if (mvs_check_page (0, 4, 0)) ! 3629: { ! 3630: mvs_check_page (0, 2, 4); ! 3631: return \"L 14,=A(%l0)\;BHR 14\"; ! 3632: } ! 3633: return \"BH %l0\"; ! 3634: }") ! 3635: ! 3636: ; ! 3637: ; blt instruction pattern(s). ! 3638: ; ! 3639: ! 3640: (define_insn "blt" ! 3641: [(set (pc) ! 3642: (if_then_else (lt (cc0) ! 3643: (const_int 0)) ! 3644: (label_ref (match_operand 0 "" "")) ! 3645: (pc)))] ! 3646: "" ! 3647: "* ! 3648: { ! 3649: check_label_emit (); ! 3650: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3651: { ! 3652: mvs_check_page (0, 6, 4); ! 3653: return \"L 14,=A(%l0)\;BLR 14\"; ! 3654: } ! 3655: if (mvs_check_page (0, 4, 0)) ! 3656: { ! 3657: mvs_check_page (0, 2, 4); ! 3658: return \"L 14,=A(%l0)\;BLR 14\"; ! 3659: } ! 3660: return \"BL %l0\"; ! 3661: }") ! 3662: ! 3663: ; ! 3664: ; bltu instruction pattern(s). ! 3665: ; ! 3666: ! 3667: (define_insn "bltu" ! 3668: [(set (pc) ! 3669: (if_then_else (ltu (cc0) ! 3670: (const_int 0)) ! 3671: (label_ref (match_operand 0 "" "")) ! 3672: (pc)))] ! 3673: "" ! 3674: "* ! 3675: { ! 3676: check_label_emit (); ! 3677: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3678: { ! 3679: mvs_check_page (0, 6, 4); ! 3680: return \"L 14,=A(%l0)\;BLR 14\"; ! 3681: } ! 3682: if (mvs_check_page (0, 4, 0)) ! 3683: { ! 3684: mvs_check_page (0, 2, 4); ! 3685: return \"L 14,=A(%l0)\;BLR 14\"; ! 3686: } ! 3687: return \"BL %l0\"; ! 3688: }") ! 3689: ! 3690: ; ! 3691: ; bge instruction pattern(s). ! 3692: ; ! 3693: ! 3694: (define_insn "bge" ! 3695: [(set (pc) ! 3696: (if_then_else (ge (cc0) ! 3697: (const_int 0)) ! 3698: (label_ref (match_operand 0 "" "")) ! 3699: (pc)))] ! 3700: "" ! 3701: "* ! 3702: { ! 3703: check_label_emit (); ! 3704: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3705: { ! 3706: mvs_check_page (0, 6, 4); ! 3707: return \"L 14,=A(%l0)\;BNLR 14\"; ! 3708: } ! 3709: if (mvs_check_page (0, 4, 0)) ! 3710: { ! 3711: mvs_check_page (0, 2, 4); ! 3712: return \"L 14,=A(%l0)\;BNLR 14\"; ! 3713: } ! 3714: return \"BNL %l0\"; ! 3715: }") ! 3716: ! 3717: ; ! 3718: ; bgeu instruction pattern(s). ! 3719: ; ! 3720: ! 3721: (define_insn "bgeu" ! 3722: [(set (pc) ! 3723: (if_then_else (geu (cc0) ! 3724: (const_int 0)) ! 3725: (label_ref (match_operand 0 "" "")) ! 3726: (pc)))] ! 3727: "" ! 3728: "* ! 3729: { ! 3730: check_label_emit (); ! 3731: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3732: { ! 3733: mvs_check_page (0, 6, 4); ! 3734: return \"L 14,=A(%l0)\;BNLR 14\"; ! 3735: } ! 3736: if (mvs_check_page (0, 4, 0)) ! 3737: { ! 3738: mvs_check_page (0, 2, 4); ! 3739: return \"L 14,=A(%l0)\;BNLR 14\"; ! 3740: } ! 3741: return \"BNL %l0\"; ! 3742: }") ! 3743: ! 3744: ; ! 3745: ; ble instruction pattern(s). ! 3746: ; ! 3747: ! 3748: (define_insn "ble" ! 3749: [(set (pc) ! 3750: (if_then_else (le (cc0) ! 3751: (const_int 0)) ! 3752: (label_ref (match_operand 0 "" "")) ! 3753: (pc)))] ! 3754: "" ! 3755: "* ! 3756: { ! 3757: check_label_emit (); ! 3758: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3759: { ! 3760: mvs_check_page (0, 6, 4); ! 3761: return \"L 14,=A(%l0)\;BNHR 14\"; ! 3762: } ! 3763: if (mvs_check_page (0, 4, 0)) ! 3764: { ! 3765: mvs_check_page (0, 2, 4); ! 3766: return \"L 14,=A(%l0)\;BNHR 14\"; ! 3767: } ! 3768: return \"BNH %l0\"; ! 3769: }") ! 3770: ! 3771: ; ! 3772: ; bleu instruction pattern(s). ! 3773: ; ! 3774: ! 3775: (define_insn "bleu" ! 3776: [(set (pc) ! 3777: (if_then_else (leu (cc0) ! 3778: (const_int 0)) ! 3779: (label_ref (match_operand 0 "" "")) ! 3780: (pc)))] ! 3781: "" ! 3782: "* ! 3783: { ! 3784: check_label_emit (); ! 3785: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3786: { ! 3787: mvs_check_page (0, 6, 4); ! 3788: return \"L 14,=A(%l0)\;BNHR 14\"; ! 3789: } ! 3790: if (mvs_check_page (0, 4, 0)) ! 3791: { ! 3792: mvs_check_page (0, 2, 4); ! 3793: return \"L 14,=A(%l0)\;BNHR 14\"; ! 3794: } ! 3795: return \"BNH %l0\"; ! 3796: }") ! 3797: ! 3798: ;; ! 3799: ;;- Negated conditional jump instructions. ! 3800: ;; ! 3801: ! 3802: (define_insn "" ! 3803: [(set (pc) ! 3804: (if_then_else (eq (cc0) ! 3805: (const_int 0)) ! 3806: (pc) ! 3807: (label_ref (match_operand 0 "" ""))))] ! 3808: "" ! 3809: "* ! 3810: { ! 3811: check_label_emit (); ! 3812: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3813: { ! 3814: mvs_check_page (0, 6, 4); ! 3815: return \"L 14,=A(%l0)\;BNER 14\"; ! 3816: } ! 3817: if (mvs_check_page (0, 4, 0)) ! 3818: { ! 3819: mvs_check_page (0, 2, 4); ! 3820: return \"L 14,=A(%l0)\;BNER 14\"; ! 3821: } ! 3822: return \"BNE %l0\"; ! 3823: }") ! 3824: ! 3825: (define_insn "" ! 3826: [(set (pc) ! 3827: (if_then_else (ne (cc0) ! 3828: (const_int 0)) ! 3829: (pc) ! 3830: (label_ref (match_operand 0 "" ""))))] ! 3831: "" ! 3832: "* ! 3833: { ! 3834: check_label_emit (); ! 3835: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3836: { ! 3837: mvs_check_page (0, 6, 4); ! 3838: return \"L 14,=A(%l0)\;BER 14\"; ! 3839: } ! 3840: if (mvs_check_page (0, 4, 0)) ! 3841: { ! 3842: mvs_check_page (0, 2, 4); ! 3843: return \"L 14,=A(%l0)\;BER 14\"; ! 3844: } ! 3845: return \"BE %l0\"; ! 3846: }") ! 3847: ! 3848: (define_insn "" ! 3849: [(set (pc) ! 3850: (if_then_else (gt (cc0) ! 3851: (const_int 0)) ! 3852: (pc) ! 3853: (label_ref (match_operand 0 "" ""))))] ! 3854: "" ! 3855: "* ! 3856: { ! 3857: check_label_emit (); ! 3858: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3859: { ! 3860: mvs_check_page (0, 6, 4); ! 3861: return \"L 14,=A(%l0)\;BNHR 14\"; ! 3862: } ! 3863: if (mvs_check_page (0, 4, 0)) ! 3864: { ! 3865: mvs_check_page (0, 2, 4); ! 3866: return \"L 14,=A(%l0)\;BNHR 14\"; ! 3867: } ! 3868: return \"BNH %l0\"; ! 3869: }") ! 3870: ! 3871: (define_insn "" ! 3872: [(set (pc) ! 3873: (if_then_else (gtu (cc0) ! 3874: (const_int 0)) ! 3875: (pc) ! 3876: (label_ref (match_operand 0 "" ""))))] ! 3877: "" ! 3878: "* ! 3879: { ! 3880: check_label_emit (); ! 3881: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3882: { ! 3883: mvs_check_page (0, 6, 4); ! 3884: return \"L 14,=A(%l0)\;BNHR 14\"; ! 3885: } ! 3886: if (mvs_check_page (0, 4, 0)) ! 3887: { ! 3888: mvs_check_page (0, 2, 4); ! 3889: return \"L 14,=A(%l0)\;BNHR 14\"; ! 3890: } ! 3891: return \"BNH %l0\"; ! 3892: }") ! 3893: ! 3894: (define_insn "" ! 3895: [(set (pc) ! 3896: (if_then_else (lt (cc0) ! 3897: (const_int 0)) ! 3898: (pc) ! 3899: (label_ref (match_operand 0 "" ""))))] ! 3900: "" ! 3901: "* ! 3902: { ! 3903: check_label_emit (); ! 3904: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3905: { ! 3906: mvs_check_page (0, 6, 4); ! 3907: return \"L 14,=A(%l0)\;BNLR 14\"; ! 3908: } ! 3909: if (mvs_check_page (0, 4, 0)) ! 3910: { ! 3911: mvs_check_page (0, 2, 4); ! 3912: return \"L 14,=A(%l0)\;BNLR 14\"; ! 3913: } ! 3914: return \"BNL %l0\"; ! 3915: }") ! 3916: ! 3917: (define_insn "" ! 3918: [(set (pc) ! 3919: (if_then_else (ltu (cc0) ! 3920: (const_int 0)) ! 3921: (pc) ! 3922: (label_ref (match_operand 0 "" ""))))] ! 3923: "" ! 3924: "* ! 3925: { ! 3926: check_label_emit (); ! 3927: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3928: { ! 3929: mvs_check_page (0, 6, 4); ! 3930: return \"L 14,=A(%l0)\;BNLR 14\"; ! 3931: } ! 3932: if (mvs_check_page (0, 4, 0)) ! 3933: { ! 3934: mvs_check_page (0, 2, 4); ! 3935: return \"L 14,=A(%l0)\;BNLR 14\"; ! 3936: } ! 3937: return \"BNL %l0\"; ! 3938: }") ! 3939: ! 3940: (define_insn "" ! 3941: [(set (pc) ! 3942: (if_then_else (ge (cc0) ! 3943: (const_int 0)) ! 3944: (pc) ! 3945: (label_ref (match_operand 0 "" ""))))] ! 3946: "" ! 3947: "* ! 3948: { ! 3949: check_label_emit (); ! 3950: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3951: { ! 3952: mvs_check_page (0, 6, 4); ! 3953: return \"L 14,=A(%l0)\;BLR 14\"; ! 3954: } ! 3955: if (mvs_check_page (0, 4, 0)) ! 3956: { ! 3957: mvs_check_page (0, 2, 4); ! 3958: return \"L 14,=A(%l0)\;BLR 14\"; ! 3959: } ! 3960: return \"BL %l0\"; ! 3961: }") ! 3962: ! 3963: (define_insn "" ! 3964: [(set (pc) ! 3965: (if_then_else (geu (cc0) ! 3966: (const_int 0)) ! 3967: (pc) ! 3968: (label_ref (match_operand 0 "" ""))))] ! 3969: "" ! 3970: "* ! 3971: { ! 3972: check_label_emit (); ! 3973: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3974: { ! 3975: mvs_check_page (0, 6, 4); ! 3976: return \"L 14,=A(%l0)\;BLR 14\"; ! 3977: } ! 3978: if (mvs_check_page (0, 4, 0)) ! 3979: { ! 3980: mvs_check_page (0, 2, 4); ! 3981: return \"L 14,=A(%l0)\;BLR 14\"; ! 3982: } ! 3983: return \"BL %l0\"; ! 3984: }") ! 3985: ! 3986: (define_insn "" ! 3987: [(set (pc) ! 3988: (if_then_else (le (cc0) ! 3989: (const_int 0)) ! 3990: (pc) ! 3991: (label_ref (match_operand 0 "" ""))))] ! 3992: "" ! 3993: "* ! 3994: { ! 3995: check_label_emit (); ! 3996: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 3997: { ! 3998: mvs_check_page (0, 6, 4); ! 3999: return \"L 14,=A(%l0)\;BHR 14\"; ! 4000: } ! 4001: if (mvs_check_page (0, 4, 0)) ! 4002: { ! 4003: mvs_check_page (0, 2, 4); ! 4004: return \"L 14,=A(%l0)\;BHR 14\"; ! 4005: } ! 4006: return \"BH %l0\"; ! 4007: }") ! 4008: ! 4009: (define_insn "" ! 4010: [(set (pc) ! 4011: (if_then_else (leu (cc0) ! 4012: (const_int 0)) ! 4013: (pc) ! 4014: (label_ref (match_operand 0 "" ""))))] ! 4015: "" ! 4016: "* ! 4017: { ! 4018: check_label_emit (); ! 4019: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 4020: { ! 4021: mvs_check_page (0, 6, 4); ! 4022: return \"L 14,=A(%l0)\;BHR 14\"; ! 4023: } ! 4024: if (mvs_check_page (0, 4, 0)) ! 4025: { ! 4026: mvs_check_page (0, 2, 4); ! 4027: return \"L 14,=A(%l0)\;BHR 14\"; ! 4028: } ! 4029: return \"BH %l0\"; ! 4030: }") ! 4031: ! 4032: ;; ! 4033: ;;- Subtract one and jump if not zero. ! 4034: ;; ! 4035: ! 4036: (define_insn "" ! 4037: [(set (pc) ! 4038: (if_then_else ! 4039: (ne (plus:SI (match_operand:SI 0 "register_operand" "+d") ! 4040: (const_int -1)) ! 4041: (const_int 0)) ! 4042: (label_ref (match_operand 1 "" "")) ! 4043: (pc))) ! 4044: (set (match_dup 0) ! 4045: (plus:SI (match_dup 0) ! 4046: (const_int -1)))] ! 4047: "" ! 4048: "* ! 4049: { ! 4050: check_label_emit (); ! 4051: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[1]))) ! 4052: { ! 4053: mvs_check_page (0, 6, 4); ! 4054: return \"L 14,=A(%l1)\;BCTR %0,14\"; ! 4055: } ! 4056: if (mvs_check_page (0, 4, 0)) ! 4057: { ! 4058: mvs_check_page (0, 2, 4); ! 4059: return \"L 14,=A(%l1)\;BCTR %0,14\"; ! 4060: } ! 4061: return \"BCT %0,%l1\"; ! 4062: }") ! 4063: ! 4064: (define_insn "" ! 4065: [(set (pc) ! 4066: (if_then_else ! 4067: (eq (plus:SI (match_operand:SI 0 "register_operand" "+d") ! 4068: (const_int -1)) ! 4069: (const_int 0)) ! 4070: (pc) ! 4071: (label_ref (match_operand 1 "" "")))) ! 4072: (set (match_dup 0) ! 4073: (plus:SI (match_dup 0) ! 4074: (const_int -1)))] ! 4075: "" ! 4076: "* ! 4077: { ! 4078: check_label_emit (); ! 4079: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[1]))) ! 4080: { ! 4081: mvs_check_page (0, 6, 4); ! 4082: return \"L 14,=A(%l1)\;BCTR %0,14\"; ! 4083: } ! 4084: if (mvs_check_page (0, 4, 0)) ! 4085: { ! 4086: mvs_check_page (0, 2, 4); ! 4087: return \"L 14,=A(%l1)\;BCTR %0,14\"; ! 4088: } ! 4089: return \"BCT %0,%l1\"; ! 4090: }") ! 4091: ! 4092: ;; ! 4093: ;;- Unconditional jump instructions. ! 4094: ;; ! 4095: ! 4096: ; ! 4097: ; jump instruction pattern(s). ! 4098: ; ! 4099: ! 4100: (define_insn "jump" ! 4101: [(set (pc) ! 4102: (label_ref (match_operand 0 "" "")))] ! 4103: "" ! 4104: "* ! 4105: { ! 4106: check_label_emit (); ! 4107: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) ! 4108: { ! 4109: mvs_check_page (0, 6, 4); ! 4110: return \"L 14,=A(%l0)\;BR 14\"; ! 4111: } ! 4112: if (mvs_check_page (0, 4, 0)) ! 4113: { ! 4114: mvs_check_page (0, 2, 4); ! 4115: return \"L 14,=A(%l0)\;BR 14\"; ! 4116: } ! 4117: return \"B %l0\"; ! 4118: }") ! 4119: ! 4120: ; ! 4121: ; indirect-jump instruction pattern(s). ! 4122: ; ! 4123: ! 4124: (define_insn "indirect_jump" ! 4125: [(set (pc) (match_operand:SI 0 "general_operand" "r"))] ! 4126: "(GET_CODE (operands[0]) != MEM )" ! 4127: "* ! 4128: { ! 4129: check_label_emit (); ! 4130: mvs_check_page (0, 2, 0); ! 4131: return \"BR %0\"; ! 4132: }") ! 4133: ! 4134: ; ! 4135: ; tablejump instruction pattern(s). ! 4136: ; ! 4137: ! 4138: (define_insn "tablejump" ! 4139: [(set (pc) ! 4140: (match_operand:SI 0 "general_operand" "am")) ! 4141: (use (label_ref (match_operand 1 "" "")))] ! 4142: "" ! 4143: "* ! 4144: { ! 4145: check_label_emit (); ! 4146: if (REG_P (operands[0])) ! 4147: { ! 4148: mvs_check_page (0, 6, 0); ! 4149: return \"BR %0\;DS 0F\"; ! 4150: } ! 4151: mvs_check_page (0, 10, 0); ! 4152: return \"L 14,%0\;BR 14\;DS 0F\"; ! 4153: }") ! 4154: ! 4155: ;; ! 4156: ;;- Jump to subroutine. ! 4157: ;; ! 4158: ;; For the C/370 environment the internal functions, ie. sqrt, are called with ! 4159: ;; a non-standard form. So, we must fix it here. There's no BM like IBM. ! 4160: ;; ! 4161: ! 4162: ; ! 4163: ; call instruction pattern(s). ! 4164: ; ! 4165: ! 4166: (define_insn "call" ! 4167: [(call (match_operand:QI 0 "memory_operand" "m") ! 4168: (match_operand:SI 1 "immediate_operand" "i"))] ! 4169: "" ! 4170: "* ! 4171: { ! 4172: static char temp[128]; ! 4173: int i = STACK_POINTER_OFFSET; ! 4174: ! 4175: check_label_emit (); ! 4176: if (mvs_function_check (XSTR (operands[0], 0))) ! 4177: { ! 4178: mvs_check_page (0, 22, 4); ! 4179: sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\;LD 0,136(,13)\", ! 4180: i - 4, i - 4 ); ! 4181: } ! 4182: else ! 4183: { ! 4184: mvs_check_page (0, 10, 4); ! 4185: sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\", i ); ! 4186: } ! 4187: return temp; ! 4188: }") ! 4189: ! 4190: ; ! 4191: ; call_value instruction pattern(s). ! 4192: ; ! 4193: ! 4194: (define_insn "call_value" ! 4195: [(set (match_operand 0 "" "rf") ! 4196: (call (match_operand:QI 1 "memory_operand" "m") ! 4197: (match_operand:SI 2 "general_operand" "i")))] ! 4198: "" ! 4199: "* ! 4200: { ! 4201: static char temp[128]; ! 4202: int i = STACK_POINTER_OFFSET; ! 4203: ! 4204: check_label_emit (); ! 4205: if (mvs_function_check (XSTR (operands[1], 0))) ! 4206: { ! 4207: mvs_check_page (0, 22, 4); ! 4208: sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\;LD 0,136(,13)\", ! 4209: i - 4, i - 4 ); ! 4210: } ! 4211: else ! 4212: { ! 4213: mvs_check_page (0, 10, 4); ! 4214: sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\", i ); ! 4215: } ! 4216: return temp; ! 4217: }") ! 4218: ! 4219: (define_insn "" ! 4220: [(call (mem:QI (match_operand:SI 0 "" "i")) ! 4221: (match_operand:SI 1 "general_operand" "g"))] ! 4222: "GET_CODE (operands[0]) == SYMBOL_REF" ! 4223: "* ! 4224: { ! 4225: static char temp[128]; ! 4226: int i = STACK_POINTER_OFFSET; ! 4227: ! 4228: check_label_emit (); ! 4229: if (mvs_function_check (XSTR (operands[0], 0))) ! 4230: { ! 4231: mvs_check_page (0, 22, 4); ! 4232: sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\;LD 0,136(,13)\", ! 4233: i - 4, i - 4 ); ! 4234: } ! 4235: else ! 4236: { ! 4237: mvs_check_page (0, 10, 4); ! 4238: sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\", i ); ! 4239: } ! 4240: return temp; ! 4241: }") ! 4242: ! 4243: (define_insn "" ! 4244: [(set (match_operand 0 "" "rf") ! 4245: (call (mem:QI (match_operand:SI 1 "" "i")) ! 4246: (match_operand:SI 2 "general_operand" "g")))] ! 4247: "GET_CODE (operands[1]) == SYMBOL_REF" ! 4248: "* ! 4249: { ! 4250: static char temp[128]; ! 4251: int i = STACK_POINTER_OFFSET; ! 4252: ! 4253: check_label_emit (); ! 4254: if (mvs_function_check (XSTR (operands[1], 0))) ! 4255: { ! 4256: mvs_check_page (0, 22, 4); ! 4257: sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\;LD 0,136(,13)\", ! 4258: i - 4, i - 4 ); ! 4259: } ! 4260: else ! 4261: { ! 4262: mvs_check_page (0, 10, 4); ! 4263: sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\", i ); ! 4264: } ! 4265: return temp; ! 4266: }") ! 4267: ! 4268: ! 4269: ;; ! 4270: ;;- Miscellaneous instructions. ! 4271: ;; ! 4272: ! 4273: ; ! 4274: ; nop instruction pattern(s). ! 4275: ; ! 4276: ! 4277: (define_insn "nop" ! 4278: [(const_int 0)] ! 4279: "" ! 4280: "* ! 4281: { ! 4282: check_label_emit (); ! 4283: mvs_check_page (0, 2, 0); ! 4284: return \"LR 0,0\"; ! 4285: }") ! 4286:
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