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1.1 root 1: /* Definitions of target machine for GNU compiler for Intel 80386.
2: Copyright (C) 1988, 1992 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is free software; you can redistribute it and/or modify
7: it under the terms of the GNU General Public License as published by
8: the Free Software Foundation; either version 2, or (at your option)
9: any later version.
10:
11: GNU CC is distributed in the hope that it will be useful,
12: but WITHOUT ANY WARRANTY; without even the implied warranty of
13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: GNU General Public License for more details.
15:
16: You should have received a copy of the GNU General Public License
17: along with GNU CC; see the file COPYING. If not, write to
18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19:
20:
21: /* The purpose of this file is to define the characteristics of the i386,
22: independent of assembler syntax or operating system.
23:
24: Three other files build on this one to describe a specific assembler syntax:
25: bsd386.h, att386.h, and sun386.h.
26:
27: The actual tm.h file for a particular system should include
28: this file, and then the file for the appropriate assembler syntax.
29:
30: Many macros that specify assembler syntax are omitted entirely from
31: this file because they really belong in the files for particular
32: assemblers. These include AS1, AS2, AS3, RP, IP, LPREFIX, L_SIZE,
33: PUT_OP_SIZE, USE_STAR, ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE,
34: PRINT_B_I_S, and many that start with ASM_ or end in ASM_OP. */
35:
36: /* Names to predefine in the preprocessor for this target machine. */
37:
38: #define I386 1
39:
40: /* Stubs for half-pic support if not OSF/1 reference platform. */
41:
42: #ifndef HALF_PIC_P
43: #define HALF_PIC_P() 0
44: #define HALF_PIC_NUMBER_PTRS 0
45: #define HALF_PIC_NUMBER_REFS 0
46: #define HALF_PIC_ENCODE(DECL)
47: #define HALF_PIC_DECLARE(NAME)
48: #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
49: #define HALF_PIC_ADDRESS_P(X) 0
50: #define HALF_PIC_PTR(X) X
51: #define HALF_PIC_FINISH(STREAM)
52: #endif
53:
54: /* Run-time compilation parameters selecting different hardware subsets. */
55:
56: extern int target_flags;
57:
58: /* Macros used in the machine description to test the flags. */
59:
60: /* configure can arrage to make this 2, to force a 486. */
61: #ifndef TARGET_CPU_DEFAULT
62: #define TARGET_CPU_DEFAULT 0
63: #endif
64:
65: /* Compile 80387 insns for floating point (not library calls). */
66: #define TARGET_80387 (target_flags & 1)
67: /* Compile code for an i486. */
68: #define TARGET_486 (target_flags & 2)
69: /* Compile using ret insn that pops args.
70: This will not work unless you use prototypes at least
71: for all functions that can take varying numbers of args. */
72: #define TARGET_RTD (target_flags & 8)
73: /* Compile passing first two args in regs 0 and 1.
74: This exists only to test compiler features that will
75: be needed for RISC chips. It is not usable
76: and is not intended to be usable on this cpu. */
77: #define TARGET_REGPARM (target_flags & 020)
78:
79: /* Put uninitialized locals into bss, not data.
80: Meaningful only on svr3. */
81: #define TARGET_SVR3_SHLIB (target_flags & 040)
82:
83: /* Use IEEE floating point comparisons. These handle correctly the cases
84: where the result of a comparison is unordered. Normally SIGFPE is
85: generated in such cases, in which case this isn't needed. */
86: #define TARGET_IEEE_FP (target_flags & 0100)
87:
88: /* Functions that return a floating point value may return that value
89: in the 387 FPU or in 386 integer registers. If set, this flag causes
90: the 387 to be used, which is compatible with most calling conventions. */
91: #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & 0200)
92:
93: /* Macro to define tables used to set the flags.
94: This is a list in braces of pairs in braces,
95: each pair being { "NAME", VALUE }
96: where VALUE is the bits to set or minus the bits to clear.
97: An empty string NAME is used to identify the default VALUE. */
98:
99: #define TARGET_SWITCHES \
100: { { "80387", 1}, \
101: { "no-80387", -1}, \
102: { "soft-float", -1}, \
103: { "no-soft-float", 1}, \
104: { "486", 2}, \
105: { "no-486", -2}, \
106: { "386", -2}, \
107: { "rtd", 8}, \
108: { "no-rtd", -8}, \
109: { "regparm", 020}, \
110: { "no-regparm", -020}, \
111: { "svr3-shlib", 040}, \
112: { "no-svr3-shlib", -040}, \
113: { "ieee-fp", 0100}, \
114: { "no-ieee-fp", -0100}, \
115: { "fp-ret-in-387", 0200}, \
116: { "no-fp-ret-in-387", -0200}, \
117: SUBTARGET_SWITCHES \
118: { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT}}
119:
120: /* This is meant to be redefined in the host dependent files */
121: #define SUBTARGET_SWITCHES
122:
123: #define OVERRIDE_OPTIONS \
124: { \
125: SUBTARGET_OVERRIDE_OPTIONS \
126: }
127:
128: /* This is meant to be redefined in the host dependent files */
129: #define SUBTARGET_OVERRIDE_OPTIONS
130:
131: /* target machine storage layout */
132:
133: /* Define for XFmode extended real floating point support.
134: This will automatically cause REAL_ARITHMETIC to be defined. */
135: #define LONG_DOUBLE_TYPE_SIZE 96
136:
137: /* Define if you don't want extended real, but do want to use the
138: software floating point emulator for REAL_ARITHMETIC and
139: decimal <-> binary conversion. */
140: /* #define REAL_ARITHMETIC */
141:
142: /* Define this if most significant byte of a word is the lowest numbered. */
143: /* That is true on the 80386. */
144:
145: #define BITS_BIG_ENDIAN 0
146:
147: /* Define this if most significant byte of a word is the lowest numbered. */
148: /* That is not true on the 80386. */
149: #define BYTES_BIG_ENDIAN 0
150:
151: /* Define this if most significant word of a multiword number is the lowest
152: numbered. */
153: /* Not true for 80386 */
154: #define WORDS_BIG_ENDIAN 0
155:
156: /* number of bits in an addressable storage unit */
157: #define BITS_PER_UNIT 8
158:
159: /* Width in bits of a "word", which is the contents of a machine register.
160: Note that this is not necessarily the width of data type `int';
161: if using 16-bit ints on a 80386, this would still be 32.
162: But on a machine with 16-bit registers, this would be 16. */
163: #define BITS_PER_WORD 32
164:
165: /* Width of a word, in units (bytes). */
166: #define UNITS_PER_WORD 4
167:
168: /* Width in bits of a pointer.
169: See also the macro `Pmode' defined below. */
170: #define POINTER_SIZE 32
171:
172: /* Allocation boundary (in *bits*) for storing arguments in argument list. */
173: #define PARM_BOUNDARY 32
174:
175: /* Boundary (in *bits*) on which stack pointer should be aligned. */
176: #define STACK_BOUNDARY 32
177:
178: /* Allocation boundary (in *bits*) for the code of a function.
179: For i486, we get better performance by aligning to a cache
180: line (i.e. 16 byte) boundary. */
181: #define FUNCTION_BOUNDARY (TARGET_486 ? 128 : 32)
182:
183: /* Alignment of field after `int : 0' in a structure. */
184:
185: #define EMPTY_FIELD_BOUNDARY 32
186:
187: /* Minimum size in bits of the largest boundary to which any
188: and all fundamental data types supported by the hardware
189: might need to be aligned. No data type wants to be aligned
190: rounder than this. The i386 supports 64-bit floating point
191: quantities, but these can be aligned on any 32-bit boundary. */
192: #define BIGGEST_ALIGNMENT 32
193:
194: /* Set this non-zero if move instructions will actually fail to work
195: when given unaligned data. */
196: #define STRICT_ALIGNMENT 0
197:
198: /* If bit field type is int, don't let it cross an int,
199: and give entire struct the alignment of an int. */
200: /* Required on the 386 since it doesn't have bitfield insns. */
201: #define PCC_BITFIELD_TYPE_MATTERS 1
202:
203: /* Align loop starts for optimal branching. */
204: #define ASM_OUTPUT_LOOP_ALIGN(FILE) \
205: ASM_OUTPUT_ALIGN (FILE, 2)
206:
207: /* This is how to align an instruction for optimal branching.
208: On i486 we'll get better performance by aligning on a
209: cache line (i.e. 16 byte) boundary. */
210: #define ASM_OUTPUT_ALIGN_CODE(FILE) \
211: ASM_OUTPUT_ALIGN ((FILE), (TARGET_486 ? 4 : 2))
212:
213: /* Standard register usage. */
214:
215: /* This processor has special stack-like registers. See reg-stack.c
216: for details. */
217:
218: #define STACK_REGS
219:
220: /* Number of actual hardware registers.
221: The hardware registers are assigned numbers for the compiler
222: from 0 to just below FIRST_PSEUDO_REGISTER.
223: All registers that the compiler knows about must be given numbers,
224: even those that are not normally considered general registers.
225:
226: In the 80386 we give the 8 general purpose registers the numbers 0-7.
227: We number the floating point registers 8-15.
228: Note that registers 0-7 can be accessed as a short or int,
229: while only 0-3 may be used with byte `mov' instructions.
230:
231: Reg 16 does not correspond to any hardware register, but instead
232: appears in the RTL as an argument pointer prior to reload, and is
233: eliminated during reloading in favor of either the stack or frame
234: pointer. */
235:
236: #define FIRST_PSEUDO_REGISTER 17
237:
238: /* 1 for registers that have pervasive standard uses
239: and are not available for the register allocator.
240: On the 80386, the stack pointer is such, as is the arg pointer. */
241: #define FIXED_REGISTERS \
242: /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \
243: { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
244:
245: /* 1 for registers not available across function calls.
246: These must include the FIXED_REGISTERS and also any
247: registers that can be used without being saved.
248: The latter must include the registers where values are returned
249: and the register where structure-value addresses are passed.
250: Aside from that, you can include as many other registers as you like. */
251:
252: #define CALL_USED_REGISTERS \
253: /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \
254: { 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
255:
256: /* Macro to conditionally modify fixed_regs/call_used_regs. */
257: #define CONDITIONAL_REGISTER_USAGE \
258: { \
259: if (flag_pic) \
260: { \
261: fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
262: call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
263: } \
264: if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
265: { \
266: int i; \
267: HARD_REG_SET x; \
268: COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
269: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
270: if (TEST_HARD_REG_BIT (x, i)) \
271: fixed_regs[i] = call_used_regs[i] = 1; \
272: } \
273: }
274:
275: /* Return number of consecutive hard regs needed starting at reg REGNO
276: to hold something of mode MODE.
277: This is ordinarily the length in words of a value of mode MODE
278: but can be less for certain modes in special long registers.
279:
280: Actually there are no two word move instructions for consecutive
281: registers. And only registers 0-3 may have mov byte instructions
282: applied to them.
283: */
284:
285: #define HARD_REGNO_NREGS(REGNO, MODE) \
286: (FP_REGNO_P (REGNO) ? 1 \
287: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
288:
289: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
290: On the 80386, the first 4 cpu registers can hold any mode
291: while the floating point registers may hold only floating point.
292: Make it clear that the fp regs could not hold a 16-byte float. */
293:
294: /* The casts to int placate a compiler on a microvax,
295: for cross-compiler testing. */
296:
297: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
298: ((REGNO) < 2 ? 1 \
299: : (REGNO) < 4 ? 1 \
300: : FP_REGNO_P (REGNO) \
301: ? (((int) GET_MODE_CLASS (MODE) == (int) MODE_FLOAT \
302: || (int) GET_MODE_CLASS (MODE) == (int) MODE_COMPLEX_FLOAT) \
303: && GET_MODE_UNIT_SIZE (MODE) <= 12) \
304: : (int) (MODE) != (int) QImode)
305:
306: /* Value is 1 if it is a good idea to tie two pseudo registers
307: when one has mode MODE1 and one has mode MODE2.
308: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
309: for any hard reg, then this must be 0 for correct output. */
310:
311: #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2))
312:
313: /* A C expression returning the cost of moving data from a register of class
314: CLASS1 to one of CLASS2.
315:
316: On the i386, copying between floating-point and fixed-point
317: registers is expensive. */
318:
319: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
320: (((FLOAT_CLASS_P (CLASS1) && ! FLOAT_CLASS_P (CLASS2)) \
321: || (! FLOAT_CLASS_P (CLASS1) && FLOAT_CLASS_P (CLASS2))) ? 10 \
322: : 2)
323:
324: /* Specify the registers used for certain standard purposes.
325: The values of these macros are register numbers. */
326:
327: /* on the 386 the pc register is %eip, and is not usable as a general
328: register. The ordinary mov instructions won't work */
329: /* #define PC_REGNUM */
330:
331: /* Register to use for pushing function arguments. */
332: #define STACK_POINTER_REGNUM 7
333:
334: /* Base register for access to local variables of the function. */
335: #define FRAME_POINTER_REGNUM 6
336:
337: /* First floating point reg */
338: #define FIRST_FLOAT_REG 8
339:
340: /* First & last stack-like regs */
341: #define FIRST_STACK_REG FIRST_FLOAT_REG
342: #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
343:
344: /* Value should be nonzero if functions must have frame pointers.
345: Zero means the frame pointer need not be set up (and parms
346: may be accessed via the stack pointer) in functions that seem suitable.
347: This is computed in `reload', in reload1.c. */
348: #define FRAME_POINTER_REQUIRED 0
349:
350: /* Base register for access to arguments of the function. */
351: #define ARG_POINTER_REGNUM 16
352:
353: /* Register in which static-chain is passed to a function. */
354: #define STATIC_CHAIN_REGNUM 2
355:
356: /* Register to hold the addressing base for position independent
357: code access to data items. */
358: #define PIC_OFFSET_TABLE_REGNUM 3
359:
360: /* Register in which address to store a structure value
361: arrives in the function. On the 386, the prologue
362: copies this from the stack to register %eax. */
363: #define STRUCT_VALUE_INCOMING 0
364:
365: /* Place in which caller passes the structure value address.
366: 0 means push the value on the stack like an argument. */
367: #define STRUCT_VALUE 0
368:
369: /* Define the classes of registers for register constraints in the
370: machine description. Also define ranges of constants.
371:
372: One of the classes must always be named ALL_REGS and include all hard regs.
373: If there is more than one class, another class must be named NO_REGS
374: and contain no registers.
375:
376: The name GENERAL_REGS must be the name of a class (or an alias for
377: another name such as ALL_REGS). This is the class of registers
378: that is allowed by "g" or "r" in a register constraint.
379: Also, registers outside this class are allocated only when
380: instructions express preferences for them.
381:
382: The classes must be numbered in nondecreasing order; that is,
383: a larger-numbered class must never be contained completely
384: in a smaller-numbered class.
385:
386: For any two classes, it is very desirable that there be another
387: class that represents their union.
388:
389: It might seem that class BREG is unnecessary, since no useful 386
390: opcode needs reg %ebx. But some systems pass args to the OS in ebx,
391: and the "b" register constraint is useful in asms for syscalls. */
392:
393: enum reg_class
394: {
395: NO_REGS,
396: AREG, DREG, CREG, BREG,
397: Q_REGS, /* %eax %ebx %ecx %edx */
398: SIREG, DIREG,
399: INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
400: GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
401: FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
402: FLOAT_REGS,
403: ALL_REGS, LIM_REG_CLASSES
404: };
405:
406: #define N_REG_CLASSES (int) LIM_REG_CLASSES
407:
408: #define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS))
409:
410: /* Give names of register classes as strings for dump file. */
411:
412: #define REG_CLASS_NAMES \
413: { "NO_REGS", \
414: "AREG", "DREG", "CREG", "BREG", \
415: "Q_REGS", \
416: "SIREG", "DIREG", \
417: "INDEX_REGS", \
418: "GENERAL_REGS", \
419: "FP_TOP_REG", "FP_SECOND_REG", \
420: "FLOAT_REGS", \
421: "ALL_REGS" }
422:
423: /* Define which registers fit in which classes.
424: This is an initializer for a vector of HARD_REG_SET
425: of length N_REG_CLASSES. */
426:
427: #define REG_CLASS_CONTENTS \
428: { 0, \
429: 0x1, 0x2, 0x4, 0x8, /* AREG, DREG, CREG, BREG */ \
430: 0xf, /* Q_REGS */ \
431: 0x10, 0x20, /* SIREG, DIREG */ \
432: 0x1007f, /* INDEX_REGS */ \
433: 0x100ff, /* GENERAL_REGS */ \
434: 0x0100, 0x0200, /* FP_TOP_REG, FP_SECOND_REG */ \
435: 0xff00, /* FLOAT_REGS */ \
436: 0x1ffff }
437:
438: /* The same information, inverted:
439: Return the class number of the smallest class containing
440: reg number REGNO. This could be a conditional expression
441: or could index an array. */
442:
443: extern enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
444: #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
445:
446: /* When defined, the compiler allows registers explicitly used in the
447: rtl to be used as spill registers but prevents the compiler from
448: extending the lifetime of these registers. */
449:
450: #define SMALL_REGISTER_CLASSES
451:
452: #define QI_REG_P(X) \
453: (REG_P (X) && REGNO (X) < 4)
454: #define NON_QI_REG_P(X) \
455: (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
456:
457: #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
458: #define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG)
459:
460: #define STACK_REG_P(xop) (REG_P (xop) && \
461: REGNO (xop) >= FIRST_STACK_REG && \
462: REGNO (xop) <= LAST_STACK_REG)
463:
464: #define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop))
465:
466: #define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG)
467:
468: /* Try to maintain the accuracy of the death notes for regs satisfying the
469: following. Important for stack like regs, to know when to pop. */
470:
471: /* #define PRESERVE_DEATH_INFO_REGNO_P(x) FP_REGNO_P(x) */
472:
473: /* 1 if register REGNO can magically overlap other regs.
474: Note that nonzero values work only in very special circumstances. */
475:
476: /* #define OVERLAPPING_REGNO_P(REGNO) FP_REGNO_P (REGNO) */
477:
478: /* The class value for index registers, and the one for base regs. */
479:
480: #define INDEX_REG_CLASS INDEX_REGS
481: #define BASE_REG_CLASS GENERAL_REGS
482:
483: /* Get reg_class from a letter such as appears in the machine description. */
484:
485: #define REG_CLASS_FROM_LETTER(C) \
486: ((C) == 'r' ? GENERAL_REGS : \
487: (C) == 'q' ? Q_REGS : \
488: (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
489: ? FLOAT_REGS \
490: : NO_REGS) : \
491: (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
492: ? FP_TOP_REG \
493: : NO_REGS) : \
494: (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
495: ? FP_SECOND_REG \
496: : NO_REGS) : \
497: (C) == 'a' ? AREG : \
498: (C) == 'b' ? BREG : \
499: (C) == 'c' ? CREG : \
500: (C) == 'd' ? DREG : \
501: (C) == 'D' ? DIREG : \
502: (C) == 'S' ? SIREG : NO_REGS)
503:
504: /* The letters I, J, K, L and M in a register constraint string
505: can be used to stand for particular ranges of immediate operands.
506: This macro defines what the ranges are.
507: C is the letter, and VALUE is a constant value.
508: Return 1 if VALUE is in the range specified by C.
509:
510: I is for non-DImode shifts.
511: J is for DImode shifts.
512: K and L are for an `andsi' optimization.
513: M is for shifts that can be executed by the "lea" opcode.
514: */
515:
516: #define CONST_OK_FOR_LETTER_P(VALUE, C) \
517: ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 : \
518: (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 : \
519: (C) == 'K' ? (VALUE) == 0xff : \
520: (C) == 'L' ? (VALUE) == 0xffff : \
521: (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 : \
522: 0)
523:
524: /* Similar, but for floating constants, and defining letters G and H.
525: Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
526: TARGET_387 isn't set, because the stack register converter may need to
527: load 0.0 into the function value register. */
528:
529: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
530: ((C) == 'G' ? standard_80387_constant_p (VALUE) : 0)
531:
532: /* Place additional restrictions on the register class to use when it
533: is necessary to be able to hold a value of mode MODE in a reload
534: register for which class CLASS would ordinarily be used. */
535:
536: #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
537: ((MODE) == QImode && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \
538: ? Q_REGS : (CLASS))
539:
540: /* Given an rtx X being reloaded into a reg required to be
541: in class CLASS, return the class of reg to actually use.
542: In general this is just CLASS; but on some machines
543: in some cases it is preferable to use a more restrictive class.
544: On the 80386 series, we prevent floating constants from being
545: reloaded into floating registers (since no move-insn can do that)
546: and we ensure that QImodes aren't reloaded into the esi or edi reg. */
547:
548: /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
549: QImode must go into class Q_REGS.
550: Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
551: movdf to do mem-to-mem moves through integer regs. */
552:
553: #define PREFERRED_RELOAD_CLASS(X,CLASS) \
554: (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode ? NO_REGS \
555: : GET_MODE (X) == QImode && ! reg_class_subset_p (CLASS, Q_REGS) ? Q_REGS \
556: : ((CLASS) == ALL_REGS \
557: && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) ? GENERAL_REGS \
558: : (CLASS))
559:
560: /* If we are copying between general and FP registers, we need a memory
561: location. */
562:
563: #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
564: ((FLOAT_CLASS_P (CLASS1) && ! FLOAT_CLASS_P (CLASS2)) \
565: || (! FLOAT_CLASS_P (CLASS1) && FLOAT_CLASS_P (CLASS2)))
566:
567: /* Return the maximum number of consecutive registers
568: needed to represent mode MODE in a register of class CLASS. */
569: /* On the 80386, this is the size of MODE in words,
570: except in the FP regs, where a single reg is always enough. */
571: #define CLASS_MAX_NREGS(CLASS, MODE) \
572: (FLOAT_CLASS_P (CLASS) ? 1 : \
573: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
574:
575: /* Stack layout; function entry, exit and calling. */
576:
577: /* Define this if pushing a word on the stack
578: makes the stack pointer a smaller address. */
579: #define STACK_GROWS_DOWNWARD
580:
581: /* Define this if the nominal address of the stack frame
582: is at the high-address end of the local variables;
583: that is, each additional local variable allocated
584: goes at a more negative offset in the frame. */
585: #define FRAME_GROWS_DOWNWARD
586:
587: /* Offset within stack frame to start allocating local variables at.
588: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
589: first local allocated. Otherwise, it is the offset to the BEGINNING
590: of the first local allocated. */
591: #define STARTING_FRAME_OFFSET 0
592:
593: /* If we generate an insn to push BYTES bytes,
594: this says how many the stack pointer really advances by.
595: On 386 pushw decrements by exactly 2 no matter what the position was.
596: On the 386 there is no pushb; we use pushw instead, and this
597: has the effect of rounding up to 2. */
598:
599: #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & (-2))
600:
601: /* Offset of first parameter from the argument pointer register value. */
602: #define FIRST_PARM_OFFSET(FNDECL) 0
603:
604: /* Value is the number of bytes of arguments automatically
605: popped when returning from a subroutine call.
606: FUNTYPE is the data type of the function (as a tree),
607: or for a library call it is an identifier node for the subroutine name.
608: SIZE is the number of bytes of arguments passed on the stack.
609:
610: On the 80386, the RTD insn may be used to pop them if the number
611: of args is fixed, but if the number is variable then the caller
612: must pop them all. RTD can't be used for library calls now
613: because the library is compiled with the Unix compiler.
614: Use of RTD is a selectable option, since it is incompatible with
615: standard Unix calling sequences. If the option is not selected,
616: the caller must always pop the args. */
617:
618: #define RETURN_POPS_ARGS(FUNTYPE,SIZE) \
619: (TREE_CODE (FUNTYPE) == IDENTIFIER_NODE ? 0 \
620: : (TARGET_RTD \
621: && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
622: || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
623: == void_type_node))) ? (SIZE) \
624: : (aggregate_value_p (TREE_TYPE (FUNTYPE))) ? GET_MODE_SIZE (Pmode) : 0)
625:
626: /* Define how to find the value returned by a function.
627: VALTYPE is the data type of the value (as a tree).
628: If the precise function being called is known, FUNC is its FUNCTION_DECL;
629: otherwise, FUNC is 0. */
630: #define FUNCTION_VALUE(VALTYPE, FUNC) \
631: gen_rtx (REG, TYPE_MODE (VALTYPE), \
632: VALUE_REGNO (TYPE_MODE (VALTYPE)))
633:
634: /* Define how to find the value returned by a library function
635: assuming the value has mode MODE. */
636:
637: #define LIBCALL_VALUE(MODE) \
638: gen_rtx (REG, MODE, VALUE_REGNO (MODE))
639:
640: /* Define the size of the result block used for communication between
641: untyped_call and untyped_return. The block contains a DImode value
642: followed by the block used by fnsave and frstor. */
643:
644: #define APPLY_RESULT_SIZE (8+108)
645:
646: /* 1 if N is a possible register number for function argument passing.
647: On the 80386, no registers are used in this way.
648: *NOTE* -mregparm does not work.
649: It exists only to test register calling conventions. */
650:
651: #define FUNCTION_ARG_REGNO_P(N) 0
652:
653: /* Define a data type for recording info about an argument list
654: during the scan of that argument list. This data type should
655: hold all necessary information about the function itself
656: and about the args processed so far, enough to enable macros
657: such as FUNCTION_ARG to determine where the next arg should go.
658:
659: On the 80386, this is a single integer, which is a number of bytes
660: of arguments scanned so far. */
661:
662: #define CUMULATIVE_ARGS int
663:
664: /* Initialize a variable CUM of type CUMULATIVE_ARGS
665: for a call to a function whose data type is FNTYPE.
666: For a library call, FNTYPE is 0.
667:
668: On the 80386, the offset starts at 0. */
669:
670: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
671: ((CUM) = 0)
672:
673: /* Update the data in CUM to advance over an argument
674: of mode MODE and data type TYPE.
675: (TYPE is null for libcalls where that information may not be available.) */
676:
677: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
678: ((CUM) += ((MODE) != BLKmode \
679: ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
680: : (int_size_in_bytes (TYPE) + 3) & ~3))
681:
682: /* Define where to put the arguments to a function.
683: Value is zero to push the argument on the stack,
684: or a hard register in which to store the argument.
685:
686: MODE is the argument's machine mode.
687: TYPE is the data type of the argument (as a tree).
688: This is null for libcalls where that information may
689: not be available.
690: CUM is a variable of type CUMULATIVE_ARGS which gives info about
691: the preceding args and about the function being called.
692: NAMED is nonzero if this argument is a named parameter
693: (otherwise it is an extra parameter matching an ellipsis). */
694:
695:
696: /* On the 80386 all args are pushed, except if -mregparm is specified
697: then the first two words of arguments are passed in EAX, EDX.
698: *NOTE* -mregparm does not work.
699: It exists only to test register calling conventions. */
700:
701: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
702: ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0)
703:
704: /* For an arg passed partly in registers and partly in memory,
705: this is the number of registers used.
706: For args passed entirely in registers or entirely in memory, zero. */
707:
708:
709: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
710: ((TARGET_REGPARM && (CUM) < 8 \
711: && 8 < ((CUM) + ((MODE) == BLKmode \
712: ? int_size_in_bytes (TYPE) \
713: : GET_MODE_SIZE (MODE)))) \
714: ? 2 - (CUM) / 4 : 0)
715:
716: /* This macro generates the assembly code for function entry.
717: FILE is a stdio stream to output the code to.
718: SIZE is an int: how many units of temporary storage to allocate.
719: Refer to the array `regs_ever_live' to determine which registers
720: to save; `regs_ever_live[I]' is nonzero if register number I
721: is ever used in the function. This macro is responsible for
722: knowing which registers should not be saved even if used. */
723:
724: #define FUNCTION_PROLOGUE(FILE, SIZE) \
725: function_prologue (FILE, SIZE)
726:
727: /* Output assembler code to FILE to increment profiler label # LABELNO
728: for profiling a function entry. */
729:
730: #define FUNCTION_PROFILER(FILE, LABELNO) \
731: { \
732: if (flag_pic) \
733: { \
734: fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \
735: LPREFIX, (LABELNO)); \
736: fprintf (FILE, "\tcall *_mcount@GOT(%%ebx)\n"); \
737: } \
738: else \
739: { \
740: fprintf (FILE, "\tmovl $%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
741: fprintf (FILE, "\tcall _mcount\n"); \
742: } \
743: }
744:
745: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
746: the stack pointer does not matter. The value is tested only in
747: functions that have frame pointers.
748: No definition is equivalent to always zero. */
749: /* Note on the 386 it might be more efficient not to define this since
750: we have to restore it ourselves from the frame pointer, in order to
751: use pop */
752:
753: #define EXIT_IGNORE_STACK 1
754:
755: /* This macro generates the assembly code for function exit,
756: on machines that need it. If FUNCTION_EPILOGUE is not defined
757: then individual return instructions are generated for each
758: return statement. Args are same as for FUNCTION_PROLOGUE.
759:
760: The function epilogue should not depend on the current stack pointer!
761: It should use the frame pointer only. This is mandatory because
762: of alloca; we also take advantage of it to omit stack adjustments
763: before returning.
764:
765: If the last non-note insn in the function is a BARRIER, then there
766: is no need to emit a function prologue, because control does not fall
767: off the end. This happens if the function ends in an "exit" call, or
768: if a `return' insn is emitted directly into the function. */
769:
770: #define FUNCTION_EPILOGUE(FILE, SIZE) \
771: do { \
772: rtx last = get_last_insn (); \
773: if (last && GET_CODE (last) == NOTE) \
774: last = prev_nonnote_insn (last); \
775: if (! last || GET_CODE (last) != BARRIER) \
776: function_epilogue (FILE, SIZE); \
777: } while (0)
778:
779: /* Output assembler code for a block containing the constant parts
780: of a trampoline, leaving space for the variable parts. */
781:
782: /* On the 386, the trampoline contains three instructions:
783: mov #STATIC,ecx
784: mov #FUNCTION,eax
785: jmp @eax */
786: #define TRAMPOLINE_TEMPLATE(FILE) \
787: { \
788: ASM_OUTPUT_CHAR (FILE, GEN_INT (0xb9)); \
789: ASM_OUTPUT_SHORT (FILE, const0_rtx); \
790: ASM_OUTPUT_SHORT (FILE, const0_rtx); \
791: ASM_OUTPUT_CHAR (FILE, GEN_INT (0xb8)); \
792: ASM_OUTPUT_SHORT (FILE, const0_rtx); \
793: ASM_OUTPUT_SHORT (FILE, const0_rtx); \
794: ASM_OUTPUT_CHAR (FILE, GEN_INT (0xff)); \
795: ASM_OUTPUT_CHAR (FILE, GEN_INT (0xe0)); \
796: }
797:
798: /* Length in units of the trampoline for entering a nested function. */
799:
800: #define TRAMPOLINE_SIZE 12
801:
802: /* Emit RTL insns to initialize the variable parts of a trampoline.
803: FNADDR is an RTX for the address of the function's pure code.
804: CXT is an RTX for the static chain value for the function. */
805:
806: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
807: { \
808: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 1)), CXT); \
809: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 6)), FNADDR); \
810: }
811:
812: /* Definitions for register eliminations.
813:
814: This is an array of structures. Each structure initializes one pair
815: of eliminable registers. The "from" register number is given first,
816: followed by "to". Eliminations of the same "from" register are listed
817: in order of preference.
818:
819: We have two registers that can be eliminated on the i386. First, the
820: frame pointer register can often be eliminated in favor of the stack
821: pointer register. Secondly, the argument pointer register can always be
822: eliminated; it is replaced with either the stack or frame pointer. */
823:
824: #define ELIMINABLE_REGS \
825: {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
826: { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
827: { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
828:
829: /* Given FROM and TO register numbers, say whether this elimination is allowed.
830: Frame pointer elimination is automatically handled.
831:
832: For the i386, if frame pointer elimination is being done, we would like to
833: convert ap into sp, not fp.
834:
835: All other eliminations are valid. */
836:
837: #define CAN_ELIMINATE(FROM, TO) \
838: ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
839: ? ! frame_pointer_needed \
840: : 1)
841:
842: /* Define the offset between two registers, one to be eliminated, and the other
843: its replacement, at the start of a routine. */
844:
845: #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
846: { \
847: if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
848: (OFFSET) = 8; /* Skip saved PC and previous frame pointer */ \
849: else \
850: { \
851: int regno; \
852: int offset = 0; \
853: \
854: for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
855: if ((regs_ever_live[regno] && ! call_used_regs[regno]) \
856: || (current_function_uses_pic_offset_table \
857: && regno == PIC_OFFSET_TABLE_REGNUM)) \
858: offset += 4; \
859: \
860: (OFFSET) = offset + get_frame_size (); \
861: \
862: if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
863: (OFFSET) += 4; /* Skip saved PC */ \
864: } \
865: }
866:
867: /* Addressing modes, and classification of registers for them. */
868:
869: /* #define HAVE_POST_INCREMENT */
870: /* #define HAVE_POST_DECREMENT */
871:
872: /* #define HAVE_PRE_DECREMENT */
873: /* #define HAVE_PRE_INCREMENT */
874:
875: /* Macros to check register numbers against specific register classes. */
876:
877: /* These assume that REGNO is a hard or pseudo reg number.
878: They give nonzero only if REGNO is a hard reg of the suitable class
879: or a pseudo reg currently allocated to a suitable hard reg.
880: Since they use reg_renumber, they are safe only once reg_renumber
881: has been allocated, which happens in local-alloc.c. */
882:
883: #define REGNO_OK_FOR_INDEX_P(REGNO) \
884: ((REGNO) < STACK_POINTER_REGNUM \
885: || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM)
886:
887: #define REGNO_OK_FOR_BASE_P(REGNO) \
888: ((REGNO) <= STACK_POINTER_REGNUM \
889: || (REGNO) == ARG_POINTER_REGNUM \
890: || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM)
891:
892: #define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4)
893: #define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5)
894:
895: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
896: and check its validity for a certain class.
897: We have two alternate definitions for each of them.
898: The usual definition accepts all pseudo regs; the other rejects
899: them unless they have been allocated suitable hard regs.
900: The symbol REG_OK_STRICT causes the latter definition to be used.
901:
902: Most source files want to accept pseudo regs in the hope that
903: they will get allocated to the class that the insn wants them to be in.
904: Source files for reload pass need to be strict.
905: After reload, it makes no difference, since pseudo regs have
906: been eliminated by then. */
907:
908: #ifndef REG_OK_STRICT
909:
910: /* Nonzero if X is a hard reg that can be used as an index or if
911: it is a pseudo reg. */
912:
913: #define REG_OK_FOR_INDEX_P(X) \
914: (REGNO (X) < STACK_POINTER_REGNUM \
915: || REGNO (X) >= FIRST_PSEUDO_REGISTER)
916:
917: /* Nonzero if X is a hard reg that can be used as a base reg
918: of if it is a pseudo reg. */
919: /* ?wfs */
920:
921: #define REG_OK_FOR_BASE_P(X) \
922: (REGNO (X) <= STACK_POINTER_REGNUM \
923: || REGNO (X) == ARG_POINTER_REGNUM \
924: || REGNO(X) >= FIRST_PSEUDO_REGISTER)
925:
926: #define REG_OK_FOR_STRREG_P(X) \
927: (REGNO (X) == 4 || REGNO (X) == 5 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
928:
929: #else
930:
931: /* Nonzero if X is a hard reg that can be used as an index. */
932: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
933: /* Nonzero if X is a hard reg that can be used as a base reg. */
934: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
935: #define REG_OK_FOR_STRREG_P(X) \
936: (REGNO_OK_FOR_DIREG_P (REGNO (X)) || REGNO_OK_FOR_SIREG_P (REGNO (X)))
937:
938: #endif
939:
940: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
941: that is a valid memory address for an instruction.
942: The MODE argument is the machine mode for the MEM expression
943: that wants to use this address.
944:
945: The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
946: except for CONSTANT_ADDRESS_P which is usually machine-independent.
947:
948: See legitimize_pic_address in i386.c for details as to what
949: constitutes a legitimate address when -fpic is used. */
950:
951: #define MAX_REGS_PER_ADDRESS 2
952:
953: #define CONSTANT_ADDRESS_P(X) \
954: (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
955: || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
956: || GET_CODE (X) == HIGH)
957:
958: /* Nonzero if the constant value X is a legitimate general operand.
959: It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
960:
961: #define LEGITIMATE_CONSTANT_P(X) 1
962:
963: #define GO_IF_INDEXABLE_BASE(X, ADDR) \
964: if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR
965:
966: #define LEGITIMATE_INDEX_REG_P(X) \
967: (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
968:
969: /* Return 1 if X is an index or an index times a scale. */
970:
971: #define LEGITIMATE_INDEX_P(X) \
972: (LEGITIMATE_INDEX_REG_P (X) \
973: || (GET_CODE (X) == MULT \
974: && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
975: && GET_CODE (XEXP (X, 1)) == CONST_INT \
976: && (INTVAL (XEXP (X, 1)) == 2 \
977: || INTVAL (XEXP (X, 1)) == 4 \
978: || INTVAL (XEXP (X, 1)) == 8)))
979:
980: /* Go to ADDR if X is an index term, a base reg, or a sum of those. */
981:
982: #define GO_IF_INDEXING(X, ADDR) \
983: { if (LEGITIMATE_INDEX_P (X)) goto ADDR; \
984: GO_IF_INDEXABLE_BASE (X, ADDR); \
985: if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
986: { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
987: if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
988: { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
989:
990: /* We used to allow this, but it isn't ever used.
991: || ((GET_CODE (X) == POST_DEC || GET_CODE (X) == POST_INC) \
992: && REG_P (XEXP (X, 0)) \
993: && REG_OK_FOR_STRREG_P (XEXP (X, 0))) \
994: */
995:
996: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
997: { \
998: if (CONSTANT_ADDRESS_P (X) \
999: && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1000: goto ADDR; \
1001: GO_IF_INDEXING (X, ADDR); \
1002: if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1003: { \
1004: rtx x0 = XEXP (X, 0); \
1005: if (! flag_pic || ! SYMBOLIC_CONST (XEXP (X, 1))) \
1006: { GO_IF_INDEXING (x0, ADDR); } \
1007: else if (x0 == pic_offset_table_rtx) \
1008: goto ADDR; \
1009: else if (GET_CODE (x0) == PLUS) \
1010: { \
1011: if (XEXP (x0, 0) == pic_offset_table_rtx) \
1012: { GO_IF_INDEXABLE_BASE (XEXP (x0, 1), ADDR); } \
1013: if (XEXP (x0, 1) == pic_offset_table_rtx) \
1014: { GO_IF_INDEXABLE_BASE (XEXP (x0, 0), ADDR); } \
1015: } \
1016: } \
1017: }
1018:
1019: /* Try machine-dependent ways of modifying an illegitimate address
1020: to be legitimate. If we find one, return the new, valid address.
1021: This macro is used in only one place: `memory_address' in explow.c.
1022:
1023: OLDX is the address as it was before break_out_memory_refs was called.
1024: In some cases it is useful to look at this to decide what needs to be done.
1025:
1026: MODE and WIN are passed so that this macro can use
1027: GO_IF_LEGITIMATE_ADDRESS.
1028:
1029: It is always safe for this macro to do nothing. It exists to recognize
1030: opportunities to optimize the output.
1031:
1032: For the 80386, we handle X+REG by loading X into a register R and
1033: using R+REG. R will go in a general reg and indexing will be used.
1034: However, if REG is a broken-out memory address or multiplication,
1035: nothing needs to be done because REG can certainly go in a general reg.
1036:
1037: When -fpic is used, special handling is needed for symbolic references.
1038: See comments by legitimize_pic_address in i386.c for details. */
1039:
1040: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1041: { extern rtx legitimize_pic_address (); \
1042: int ch = (X) != (OLDX); \
1043: if (flag_pic && SYMBOLIC_CONST (X)) \
1044: { \
1045: (X) = legitimize_pic_address (X, 0); \
1046: if (memory_address_p (MODE, X)) \
1047: goto WIN; \
1048: } \
1049: if (GET_CODE (X) == PLUS) \
1050: { if (GET_CODE (XEXP (X, 0)) == MULT) \
1051: ch = 1, XEXP (X, 0) = force_operand (XEXP (X, 0), 0); \
1052: if (GET_CODE (XEXP (X, 1)) == MULT) \
1053: ch = 1, XEXP (X, 1) = force_operand (XEXP (X, 1), 0); \
1054: if (ch && GET_CODE (XEXP (X, 1)) == REG \
1055: && GET_CODE (XEXP (X, 0)) == REG) \
1056: goto WIN; \
1057: if (flag_pic && SYMBOLIC_CONST (XEXP (X, 1))) \
1058: ch = 1, (X) = legitimize_pic_address (X, 0); \
1059: if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1060: if (GET_CODE (XEXP (X, 0)) == REG) \
1061: { register rtx temp = gen_reg_rtx (Pmode); \
1062: register rtx val = force_operand (XEXP (X, 1), temp); \
1063: if (val != temp) emit_move_insn (temp, val); \
1064: XEXP (X, 1) = temp; \
1065: goto WIN; } \
1066: else if (GET_CODE (XEXP (X, 1)) == REG) \
1067: { register rtx temp = gen_reg_rtx (Pmode); \
1068: register rtx val = force_operand (XEXP (X, 0), temp); \
1069: if (val != temp) emit_move_insn (temp, val); \
1070: XEXP (X, 0) = temp; \
1071: goto WIN; }}}
1072:
1073: /* Nonzero if the constant value X is a legitimate general operand
1074: when generating PIC code. It is given that flag_pic is on and
1075: that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1076:
1077: #ifndef MACHOPIC_OPERAND_P
1078: #define MACHOPIC_OPERAND_P(X) machopic_operand_p (X)
1079: #endif
1080:
1081: #define LEGITIMATE_PIC_OPERAND_P(X) \
1082: (! SYMBOLIC_CONST (X) || MACHOPIC_OPERAND_P (X) \
1083: || (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)))
1084:
1085: #define SYMBOLIC_CONST(X) \
1086: (GET_CODE (X) == SYMBOL_REF \
1087: || GET_CODE (X) == LABEL_REF \
1088: || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1089:
1090: /* Go to LABEL if ADDR (a legitimate address expression)
1091: has an effect that depends on the machine mode it is used for.
1092: On the 80386, only postdecrement and postincrement address depend thus
1093: (the amount of decrement or increment being the length of the operand). */
1094: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1095: if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL
1096:
1097: /* Define this macro if references to a symbol must be treated
1098: differently depending on something about the variable or
1099: function named by the symbol (such as what section it is in).
1100:
1101: On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
1102: so that we may access it directly in the GOT. */
1103:
1104: #define ENCODE_SECTION_INFO(DECL) \
1105: do \
1106: { \
1107: if (flag_pic) \
1108: { \
1109: rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
1110: ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
1111: SYMBOL_REF_FLAG (XEXP (rtl, 0)) \
1112: = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
1113: || ! TREE_PUBLIC (DECL)); \
1114: } \
1115: } \
1116: while (0)
1117:
1118: /* Initialize data used by insn expanders. This is called from
1119: init_emit, once for each function, before code is generated.
1120: For 386, clear stack slot assignments remembered from previous
1121: functions. */
1122:
1123: #define INIT_EXPANDERS clear_386_stack_locals ()
1124:
1125: /* The `FINALIZE_PIC' macro serves as a hook to emit these special
1126: codes once the function is being compiled into assembly code, but
1127: not before. (It is not done before, because in the case of
1128: compiling an inline function, it would lead to multiple PIC
1129: prologues being included in functions which used inline functions
1130: and were compiled to assembly language.) */
1131:
1132: #define FINALIZE_PIC \
1133: do \
1134: { \
1135: extern int current_function_uses_pic_offset_table; \
1136: \
1137: current_function_uses_pic_offset_table |= profile_flag | profile_block_flag; \
1138: } \
1139: while (0)
1140:
1141:
1142: /* Specify the machine mode that this machine uses
1143: for the index in the tablejump instruction. */
1144: #define CASE_VECTOR_MODE Pmode
1145:
1146: /* Define this if the tablejump instruction expects the table
1147: to contain offsets from the address of the table.
1148: Do not define this if the table should contain absolute addresses. */
1149: /* #define CASE_VECTOR_PC_RELATIVE */
1150:
1151: /* Specify the tree operation to be used to convert reals to integers.
1152: This should be changed to take advantage of fist --wfs ??
1153: */
1154: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1155:
1156: /* This is the kind of divide that is easiest to do in the general case. */
1157: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1158:
1159: /* Define this as 1 if `char' should by default be signed; else as 0. */
1160: #define DEFAULT_SIGNED_CHAR 1
1161:
1162: /* Max number of bytes we can move from memory to memory
1163: in one reasonably fast instruction. */
1164: #define MOVE_MAX 4
1165:
1166: /* MOVE_RATIO is the number of move instructions that is better than a
1167: block move. Make this large on i386, since the block move is very
1168: inefficient with small blocks, and the hard register needs of the
1169: block move require much reload work. */
1170: #define MOVE_RATIO 5
1171:
1172: /* Define this if zero-extension is slow (more than one real instruction). */
1173: /* #define SLOW_ZERO_EXTEND */
1174:
1175: /* Nonzero if access to memory by bytes is slow and undesirable. */
1176: #define SLOW_BYTE_ACCESS 0
1177:
1178: /* Define if shifts truncate the shift count
1179: which implies one can omit a sign-extension or zero-extension
1180: of a shift count. */
1181: /* One i386, shifts do truncate the count. But bit opcodes don't. */
1182:
1183: /* #define SHIFT_COUNT_TRUNCATED */
1184:
1185: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1186: is done just by pretending it is already truncated. */
1187: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1188:
1189: /* We assume that the store-condition-codes instructions store 0 for false
1190: and some other value for true. This is the value stored for true. */
1191:
1192: #define STORE_FLAG_VALUE 1
1193:
1194: /* When a prototype says `char' or `short', really pass an `int'.
1195: (The 386 can't easily push less than an int.) */
1196:
1197: #define PROMOTE_PROTOTYPES
1198:
1199: /* Specify the machine mode that pointers have.
1200: After generation of rtl, the compiler makes no further distinction
1201: between pointers and any other objects of this machine mode. */
1202: #define Pmode SImode
1203:
1204: /* A function address in a call instruction
1205: is a byte address (for indexing purposes)
1206: so give the MEM rtx a byte's mode. */
1207: #define FUNCTION_MODE QImode
1208:
1209: /* Define this if addresses of constant functions
1210: shouldn't be put through pseudo regs where they can be cse'd.
1211: Desirable on the 386 because a CALL with a constant address is
1212: not much slower than one with a register address. */
1213: #define NO_FUNCTION_CSE
1214:
1215: /* Provide the costs of a rtl expression. This is in the body of a
1216: switch on CODE. */
1217:
1218: #define RTX_COSTS(X,CODE,OUTER_CODE) \
1219: case MULT: \
1220: return COSTS_N_INSNS (10); \
1221: case DIV: \
1222: case UDIV: \
1223: case MOD: \
1224: case UMOD: \
1225: return COSTS_N_INSNS (40); \
1226: case PLUS: \
1227: if (GET_CODE (XEXP (X, 0)) == REG \
1228: && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1229: return 1; \
1230: break;
1231:
1232:
1233: /* Compute the cost of computing a constant rtl expression RTX
1234: whose rtx-code is CODE. The body of this macro is a portion
1235: of a switch statement. If the code is computed here,
1236: return it with a return statement. Otherwise, break from the switch. */
1237:
1238: #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1239: case CONST_INT: \
1240: case CONST: \
1241: case LABEL_REF: \
1242: case SYMBOL_REF: \
1243: return flag_pic && SYMBOLIC_CONST (RTX) ? 2 : 0; \
1244: case CONST_DOUBLE: \
1245: { \
1246: int code; \
1247: if (GET_MODE (RTX) == VOIDmode) \
1248: return 2; \
1249: code = standard_80387_constant_p (RTX); \
1250: return code == 1 ? 0 : \
1251: code == 2 ? 1 : \
1252: 2; \
1253: }
1254:
1255: /* Compute the cost of an address. This is meant to approximate the size
1256: and/or execution delay of an insn using that address. If the cost is
1257: approximated by the RTL complexity, including CONST_COSTS above, as
1258: is usually the case for CISC machines, this macro should not be defined.
1259: For aggressively RISCy machines, only one insn format is allowed, so
1260: this macro should be a constant. The value of this macro only matters
1261: for valid addresses.
1262:
1263: For i386, it is better to use a complex address than let gcc copy
1264: the address into a reg and make a new pseudo. But not if the address
1265: requires to two regs - that would mean more pseudos with longer
1266: lifetimes. */
1267:
1268: #define ADDRESS_COST(RTX) \
1269: ((CONSTANT_P (RTX) \
1270: || (GET_CODE (RTX) == PLUS && CONSTANT_P (XEXP (RTX, 1)) \
1271: && REG_P (XEXP (RTX, 0)))) ? 0 \
1272: : REG_P (RTX) ? 1 \
1273: : 2)
1274:
1275: /* Add any extra modes needed to represent the condition code.
1276:
1277: For the i386, we need separate modes when floating-point equality
1278: comparisons are being done. */
1279:
1280: #define EXTRA_CC_MODES CCFPEQmode
1281:
1282: /* Define the names for the modes specified above. */
1283: #define EXTRA_CC_NAMES "CCFPEQ"
1284:
1285: /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1286: return the mode to be used for the comparison.
1287:
1288: For floating-point equality comparisons, CCFPEQmode should be used.
1289: VOIDmode should be used in all other cases. */
1290:
1291: #define SELECT_CC_MODE(OP,X,Y) \
1292: (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1293: && ((OP) == EQ || (OP) == NE) ? CCFPEQmode : VOIDmode)
1294:
1295: /* Define the information needed to generate branch and scc insns. This is
1296: stored from the compare operation. Note that we can't use "rtx" here
1297: since it hasn't been defined! */
1298:
1299: extern struct rtx_def *i386_compare_op0, *i386_compare_op1;
1300: extern struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)();
1301:
1302: /* Tell final.c how to eliminate redundant test instructions. */
1303:
1304: /* Here we define machine-dependent flags and fields in cc_status
1305: (see `conditions.h'). */
1306:
1307: /* Set if the cc value is actually in the 80387, so a floating point
1308: conditional branch must be output. */
1309: #define CC_IN_80387 04000
1310:
1311: /* Set if the CC value was stored in a nonstandard way, so that
1312: the state of equality is indicated by zero in the carry bit. */
1313: #define CC_Z_IN_NOT_C 010000
1314:
1315: /* Store in cc_status the expressions
1316: that the condition codes will describe
1317: after execution of an instruction whose pattern is EXP.
1318: Do not alter them if the instruction would not alter the cc's. */
1319:
1320: #define NOTICE_UPDATE_CC(EXP, INSN) \
1321: notice_update_cc((EXP))
1322:
1323: /* Output a signed jump insn. Use template NORMAL ordinarily, or
1324: FLOAT following a floating point comparison.
1325: Use NO_OV following an arithmetic insn that set the cc's
1326: before a test insn that was deleted.
1327: NO_OV may be zero, meaning final should reinsert the test insn
1328: because the jump cannot be handled properly without it. */
1329:
1330: #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1331: { \
1332: if (cc_prev_status.flags & CC_IN_80387) \
1333: return FLOAT; \
1334: if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1335: return NO_OV; \
1336: return NORMAL; \
1337: }
1338:
1339: /* Control the assembler format that we output, to the extent
1340: this does not vary between assemblers. */
1341:
1342: /* How to refer to registers in assembler output.
1343: This sequence is indexed by compiler's hard-register-number (see above). */
1344:
1345: /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
1346: For non floating point regs, the following are the HImode names.
1347:
1348: For float regs, the stack top is sometimes referred to as "%st(0)"
1349: instead of just "%st". PRINT_REG handles this with the "y" code. */
1350:
1351: #define HI_REGISTER_NAMES \
1352: {"ax","dx","cx","bx","si","di","bp","sp", \
1353: "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","" }
1354:
1355: #define REGISTER_NAMES HI_REGISTER_NAMES
1356:
1357: /* Table of additional register names to use in user input. */
1358:
1359: #define ADDITIONAL_REGISTER_NAMES \
1360: { "eax", 0, "edx", 1, "ecx", 2, "ebx", 3, \
1361: "esi", 4, "edi", 5, "ebp", 6, "esp", 7, \
1362: "al", 0, "dl", 1, "cl", 2, "bl", 3, \
1363: "ah", 0, "dh", 1, "ch", 2, "bh", 3 }
1364:
1365: /* Note we are omitting these since currently I don't know how
1366: to get gcc to use these, since they want the same but different
1367: number as al, and ax.
1368: */
1369:
1370: /* note the last four are not really qi_registers, but
1371: the md will have to never output movb into one of them
1372: only a movw . There is no movb into the last four regs */
1373:
1374: #define QI_REGISTER_NAMES \
1375: {"al", "dl", "cl", "bl", "si", "di", "bp", "sp",}
1376:
1377: /* These parallel the array above, and can be used to access bits 8:15
1378: of regs 0 through 3. */
1379:
1380: #define QI_HIGH_REGISTER_NAMES \
1381: {"ah", "dh", "ch", "bh", }
1382:
1383: /* How to renumber registers for dbx and gdb. */
1384:
1385: /* {0,2,1,3,6,7,4,5,12,13,14,15,16,17} */
1386: #define DBX_REGISTER_NUMBER(n) \
1387: ((n) == 0 ? 0 : \
1388: (n) == 1 ? 2 : \
1389: (n) == 2 ? 1 : \
1390: (n) == 3 ? 3 : \
1391: (n) == 4 ? 6 : \
1392: (n) == 5 ? 7 : \
1393: (n) == 6 ? 4 : \
1394: (n) == 7 ? 5 : \
1395: (n) + 4)
1396:
1397: /* This is how to output the definition of a user-level label named NAME,
1398: such as the label on a static function or variable NAME. */
1399:
1400: #define ASM_OUTPUT_LABEL(FILE,NAME) \
1401: (assemble_name (FILE, NAME), fputs (":\n", FILE))
1402:
1403: /* This is how to output an assembler line defining a `double' constant. */
1404:
1405: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1406: do { long l[2]; \
1407: REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
1408: if (sizeof (int) == sizeof (long)) \
1409: fprintf (FILE, "%s 0x%x,0x%x\n", ASM_LONG, l[0], l[1]); \
1410: else \
1411: fprintf (FILE, "%s 0x%lx,0x%lx\n", ASM_LONG, l[0], l[1]); \
1412: } while (0)
1413:
1414: /* This is how to output a `long double' extended real constant. */
1415:
1416: #undef ASM_OUTPUT_LONG_DOUBLE
1417: #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
1418: do { long l[3]; \
1419: REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
1420: if (sizeof (int) == sizeof (long)) \
1421: fprintf (FILE, "%s 0x%x,0x%x,0x%x\n", ASM_LONG, l[0], l[1], l[2]); \
1422: else \
1423: fprintf (FILE, "%s 0x%lx,0x%lx,0x%lx\n", ASM_LONG, l[0], l[1], l[2]); \
1424: } while (0)
1425:
1426: /* This is how to output an assembler line defining a `float' constant. */
1427:
1428: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1429: do { long l; \
1430: REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1431: if (sizeof (int) == sizeof (long)) \
1432: fprintf ((FILE), "%s 0x%x\n", ASM_LONG, l); \
1433: else \
1434: fprintf ((FILE), "%s 0x%lx\n", ASM_LONG, l); \
1435: } while (0)
1436:
1437: /* Store in OUTPUT a string (made with alloca) containing
1438: an assembler-name for a local static variable named NAME.
1439: LABELNO is an integer which is different for each call. */
1440:
1441: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1442: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1443: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1444:
1445:
1446:
1447: /* This is how to output an assembler line defining an `int' constant. */
1448:
1449: #define ASM_OUTPUT_INT(FILE,VALUE) \
1450: ( fprintf (FILE, "%s ", ASM_LONG), \
1451: output_addr_const (FILE,(VALUE)), \
1452: putc('\n',FILE))
1453:
1454: /* Likewise for `char' and `short' constants. */
1455: /* is this supposed to do align too?? */
1456:
1457: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1458: ( fprintf (FILE, "%s ", ASM_SHORT), \
1459: output_addr_const (FILE,(VALUE)), \
1460: putc('\n',FILE))
1461:
1462: /*
1463: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1464: ( fprintf (FILE, "%s ", ASM_BYTE_OP), \
1465: output_addr_const (FILE,(VALUE)), \
1466: fputs (",", FILE), \
1467: output_addr_const (FILE,(VALUE)), \
1468: fputs (" >> 8\n",FILE))
1469: */
1470:
1471:
1472: #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1473: ( fprintf (FILE, "%s ", ASM_BYTE_OP), \
1474: output_addr_const (FILE, (VALUE)), \
1475: putc ('\n', FILE))
1476:
1477: /* This is how to output an assembler line for a numeric constant byte. */
1478:
1479: #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1480: fprintf ((FILE), "%s 0x%x\n", ASM_BYTE_OP, (VALUE))
1481:
1482: /* This is how to output an insn to push a register on the stack.
1483: It need not be very fast code. */
1484:
1485: #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1486: fprintf (FILE, "\tpushl e%s\n", reg_names[REGNO])
1487:
1488: /* This is how to output an insn to pop a register from the stack.
1489: It need not be very fast code. */
1490:
1491: #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1492: fprintf (FILE, "\tpopl e%s\n", reg_names[REGNO])
1493:
1494: /* This is how to output an element of a case-vector that is absolute.
1495: */
1496:
1497: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1498: fprintf (FILE, "%s %s%d\n", ASM_LONG, LPREFIX, VALUE)
1499:
1500: /* This is how to output an element of a case-vector that is relative.
1501: We don't use these on the 386 yet, because the ATT assembler can't do
1502: forward reference the differences.
1503: */
1504:
1505: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1506: fprintf (FILE, "\t.word %s%d-%s%d\n",LPREFIX, VALUE,LPREFIX, REL)
1507:
1508: /* Define the parentheses used to group arithmetic operations
1509: in assembler code. */
1510:
1511: #define ASM_OPEN_PAREN ""
1512: #define ASM_CLOSE_PAREN ""
1513:
1514: /* Define results of standard character escape sequences. */
1515: #define TARGET_BELL 007
1516: #define TARGET_BS 010
1517: #define TARGET_TAB 011
1518: #define TARGET_NEWLINE 012
1519: #define TARGET_VT 013
1520: #define TARGET_FF 014
1521: #define TARGET_CR 015
1522:
1523: /* Print operand X (an rtx) in assembler syntax to file FILE.
1524: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1525: The CODE z takes the size of operand from the following digit, and
1526: outputs b,w,or l respectively.
1527:
1528: On the 80386, we use several such letters:
1529: f -- float insn (print a CONST_DOUBLE as a float rather than in hex).
1530: L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
1531: R -- print the prefix for register names.
1532: z -- print the opcode suffix for the size of the current operand.
1533: * -- print a star (in certain assembler syntax)
1534: w -- print the operand as if it's a "word" (HImode) even if it isn't.
1535: b -- print the operand as if it's a byte (QImode) even if it isn't.
1536: c -- don't print special prefixes before constant operands. */
1537:
1538: #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1539: ((CODE) == '*')
1540:
1541: /* Print the name of a register based on its machine mode and number.
1542: If CODE is 'w', pretend the mode is HImode.
1543: If CODE is 'b', pretend the mode is QImode.
1544: If CODE is 'k', pretend the mode is SImode.
1545: If CODE is 'h', pretend the reg is the `high' byte register.
1546: If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
1547:
1548: extern char *hi_reg_name[];
1549: extern char *qi_reg_name[];
1550: extern char *qi_high_reg_name[];
1551:
1552: #define PRINT_REG(X, CODE, FILE) \
1553: do { if (REGNO (X) == ARG_POINTER_REGNUM) \
1554: abort (); \
1555: fprintf (FILE, "%s", RP); \
1556: switch ((CODE == 'w' ? 2 \
1557: : CODE == 'b' ? 1 \
1558: : CODE == 'k' ? 4 \
1559: : CODE == 'y' ? 3 \
1560: : CODE == 'h' ? 0 \
1561: : GET_MODE_SIZE (GET_MODE (X)))) \
1562: { \
1563: case 3: \
1564: if (STACK_TOP_P (X)) \
1565: { \
1566: fputs ("st(0)", FILE); \
1567: break; \
1568: } \
1569: case 4: \
1570: case 8: \
1571: case 12: \
1572: if (! FP_REG_P (X)) fputs ("e", FILE); \
1573: case 2: \
1574: fputs (hi_reg_name[REGNO (X)], FILE); \
1575: break; \
1576: case 1: \
1577: fputs (qi_reg_name[REGNO (X)], FILE); \
1578: break; \
1579: case 0: \
1580: fputs (qi_high_reg_name[REGNO (X)], FILE); \
1581: break; \
1582: } \
1583: } while (0)
1584:
1585: #define PRINT_OPERAND(FILE, X, CODE) \
1586: print_operand (FILE, X, CODE)
1587:
1588: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1589: print_operand_address (FILE, ADDR)
1590:
1591: /* Print the name of a register for based on its machine mode and number.
1592: This macro is used to print debugging output.
1593: This macro is different from PRINT_REG in that it may be used in
1594: programs that are not linked with aux-output.o. */
1595:
1596: #define DEBUG_PRINT_REG(X, CODE, FILE) \
1597: do { static char *hi_name[] = HI_REGISTER_NAMES; \
1598: static char *qi_name[] = QI_REGISTER_NAMES; \
1599: fprintf (FILE, "%d %s", REGNO (X), RP); \
1600: if (REGNO (X) == ARG_POINTER_REGNUM) \
1601: { fputs ("argp", FILE); break; } \
1602: if (STACK_TOP_P (X)) \
1603: { fputs ("st(0)", FILE); break; } \
1604: switch (GET_MODE_SIZE (GET_MODE (X))) \
1605: { \
1606: case 12: \
1607: case 8: \
1608: case 4: \
1609: if (! FP_REG_P (X)) fputs ("e", FILE); \
1610: case 2: \
1611: fputs (hi_name[REGNO (X)], FILE); \
1612: break; \
1613: case 1: \
1614: fputs (qi_name[REGNO (X)], FILE); \
1615: break; \
1616: } \
1617: } while (0)
1618:
1619: /* Output the prefix for an immediate operand, or for an offset operand. */
1620: #define PRINT_IMMED_PREFIX(FILE) fputs (IP, (FILE))
1621: #define PRINT_OFFSET_PREFIX(FILE) fputs (IP, (FILE))
1622:
1623: /* Routines in libgcc that return floats must return them in an fp reg,
1624: just as other functions do which return such values.
1625: These macros make that happen. */
1626:
1627: #define FLOAT_VALUE_TYPE float
1628: #define INTIFY(FLOATVAL) FLOATVAL
1629:
1630: /* Nonzero if INSN magically clobbers register REGNO. */
1631:
1632: /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) \
1633: (FP_REGNO_P (REGNO) \
1634: && (GET_CODE (INSN) == JUMP_INSN || GET_CODE (INSN) == BARRIER))
1635: */
1636:
1637: /* a letter which is not needed by the normal asm syntax, which
1638: we can use for operand syntax in the extended asm */
1639:
1640: #define ASM_OPERAND_LETTER '#'
1641:
1642: #define RET return ""
1643: #define AT_SP(mode) (gen_rtx (MEM, (mode), stack_pointer_rtx))
1644:
1645:
1646: /* Floating point precision control.
1647:
1648: Define this to a nonzero value if a fppc pass should be performed
1649: by default. -fno-fppc can then be used to turn off the extra pass.
1650: For i386, this pass assures full ieee compliance for floating point
1651: SF and DF operations, by setting the proper rounding mode to that of
1652: the insn (either single or double), and not extended as it will
1653: usually be. */
1654:
1655: /* #define DEFAULT_FPPC */
1656:
1657: /* These are the same order as the fppc attribute. */
1658: #define FPPC_STATES SINGLE, DOUBLE, CONFLICT
1659:
1660: /* Record the local variable used to manipulate the FPCR and the last insn
1661: that needs to have the precision control set to single precision. */
1662:
1663: #define FPPC_INFO struct { rtx var, insn; }
1664:
1665: #define FPPC_INFO_INIT(INFO, FIRST) \
1666: do { \
1667: if (FIRST) \
1668: (INFO).var = assign_stack_local (HImode, 2, 0); \
1669: (INFO).insn = 0; \
1670: } while (0)
1671:
1672: #define FPPC_CLASSIFY_INSN(INSN) \
1673: (recog_memoized (INSN) < 0 \
1674: ? NONE \
1675: : (enum fppc_state) ((int) get_attr_fppc (INSN) - FPPC_SINGLE + SINGLE))
1676:
1677: /* A transition to SINGLE records INSN as the last insn needing single
1678: precision. If the previous state wasn't SINGLE, make it so. Otherwise,
1679: a transition from SINGLE (to something else) switches the precision
1680: control after the last insn. */
1681: #define FPPC_SET_STATE(FROM_STATE, TO_STATE, INSN, INFO) \
1682: { \
1683: if (TO_STATE == SINGLE) \
1684: { \
1685: (INFO).insn = INSN; \
1686: if (FROM_STATE != SINGLE) \
1687: emit_insn_before (gen_fppc_switch ((INFO).var), INSN); \
1688: } \
1689: else if (FROM_STATE == SINGLE) \
1690: { \
1691: emit_insn_after (gen_fppc_switch ((INFO).var), (INFO).insn); \
1692: (INFO).insn = 0; \
1693: } \
1694: }
1695:
1696:
1697: /*
1698: Local variables:
1699: version-control: t
1700: End:
1701: */
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