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1.1 root 1: /* Definitions of target machine for GNU compiler, for Intel 860.
2: Copyright (C) 1989, 1991, 1993 Free Software Foundation, Inc.
3:
4: Written by Richard Stallman ([email protected]).
5:
6: Hacked substantially by Ron Guilmette ([email protected]) to cater to
7: the whims of the System V Release 4 assembler.
8:
9: This file is part of GNU CC.
10:
11: GNU CC is free software; you can redistribute it and/or modify
12: it under the terms of the GNU General Public License as published by
13: the Free Software Foundation; either version 2, or (at your option)
14: any later version.
15:
16: GNU CC is distributed in the hope that it will be useful,
17: but WITHOUT ANY WARRANTY; without even the implied warranty of
18: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19: GNU General Public License for more details.
20:
21: You should have received a copy of the GNU General Public License
22: along with GNU CC; see the file COPYING. If not, write to
23: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
24:
25:
26: /* Note that some other tm.h files include this one and then override
27: many of the definitions that relate to assembler syntax. */
28:
29:
30: /* Names to predefine in the preprocessor for this target machine. */
31:
32: #define CPP_PREDEFINES "-Di860 -Dunix -Asystem(unix) -Asystem(svr4) -Acpu(i860) -Amachine(i860)"
33:
34: /* Print subsidiary information on the compiler version in use. */
35: #define TARGET_VERSION fprintf (stderr, " (i860)");
36:
37: /* Run-time compilation parameters selecting different hardware subsets
38: or supersets.
39:
40: On the i860, we have one: TARGET_XP. This option allows gcc to generate
41: additional instructions available only on the newer i860 XP (but not on
42: the older i860 XR).
43: */
44:
45: extern int target_flags;
46:
47: /* Nonzero if we should generate code to use the fpu. */
48: #define TARGET_XP (target_flags & 1)
49:
50: /* Macro to define tables used to set the flags.
51: This is a list in braces of pairs in braces,
52: each pair being { "NAME", VALUE }
53: where VALUE is the bits to set or minus the bits to clear.
54: An empty string NAME is used to identify the default VALUE. */
55:
56: #define TARGET_SWITCHES \
57: { {"xp", 1}, \
58: {"noxp", -1}, \
59: {"xr", -1}, \
60: { "", TARGET_DEFAULT}}
61:
62: #define TARGET_DEFAULT 0
63:
64: /* target machine storage layout */
65:
66: /* Define this if most significant bit is lowest numbered
67: in instructions that operate on numbered bit-fields.
68: This is a moot question on the i860 due to the lack of bit-field insns. */
69: #define BITS_BIG_ENDIAN 0
70:
71: /* Define this if most significant byte of a word is the lowest numbered. */
72: /* That is not true on i860 in the mode we will use. */
73: #define BYTES_BIG_ENDIAN 0
74:
75: /* Define this if most significant word of a multiword number is the lowest
76: numbered. */
77: /* For the i860 this goes with BYTES_BIG_ENDIAN. */
78: /* NOTE: GCC probably cannot support a big-endian i860
79: because GCC fundamentally assumes that the order of words
80: in memory as the same as the order in registers.
81: That's not true for the big-endian i860.
82: The big-endian i860 isn't important enough to
83: justify the trouble of changing this assumption. */
84: #define WORDS_BIG_ENDIAN 0
85:
86: /* number of bits in an addressable storage unit */
87: #define BITS_PER_UNIT 8
88:
89: /* Width in bits of a "word", which is the contents of a machine register.
90: Note that this is not necessarily the width of data type `int';
91: if using 16-bit ints on a 68000, this would still be 32.
92: But on a machine with 16-bit registers, this would be 16. */
93: #define BITS_PER_WORD 32
94:
95: /* Width of a word, in units (bytes). */
96: #define UNITS_PER_WORD 4
97:
98: /* Width in bits of a pointer.
99: See also the macro `Pmode' defined below. */
100: #define POINTER_SIZE 32
101:
102: /* Allocation boundary (in *bits*) for storing arguments in argument list. */
103: #define PARM_BOUNDARY 32
104:
105: /* Boundary (in *bits*) on which stack pointer should be aligned. */
106: #define STACK_BOUNDARY 128
107:
108: /* Allocation boundary (in *bits*) for the code of a function. */
109: #define FUNCTION_BOUNDARY 64
110:
111: /* Alignment of field after `int : 0' in a structure. */
112: #define EMPTY_FIELD_BOUNDARY 32
113:
114: /* Every structure's size must be a multiple of this. */
115: #define STRUCTURE_SIZE_BOUNDARY 8
116:
117: /* Minimum size in bits of the largest boundary to which any
118: and all fundamental data types supported by the hardware
119: might need to be aligned. No data type wants to be aligned
120: rounder than this. The i860 supports 128-bit (long double)
121: floating point quantities, and the System V Release 4 i860
122: ABI requires these to be aligned to 16-byte (128-bit)
123: boundaries. */
124: #define BIGGEST_ALIGNMENT 128
125:
126: /* Set this nonzero if move instructions will actually fail to work
127: when given unaligned data. */
128: #define STRICT_ALIGNMENT 1
129:
130: /* If bit field type is int, dont let it cross an int,
131: and give entire struct the alignment of an int. */
132: #define PCC_BITFIELD_TYPE_MATTERS 1
133:
134: /* Standard register usage. */
135:
136: /* Number of actual hardware registers.
137: The hardware registers are assigned numbers for the compiler
138: from 0 to just below FIRST_PSEUDO_REGISTER.
139: All registers that the compiler knows about must be given numbers,
140: even those that are not normally considered general registers.
141:
142: i860 has 32 fullword registers and 32 floating point registers. */
143:
144: #define FIRST_PSEUDO_REGISTER 64
145:
146: /* 1 for registers that have pervasive standard uses
147: and are not available for the register allocator.
148: On the i860, this includes the always-0 registers
149: and fp, sp, arg pointer, and the return address.
150: Also r31, used for special purposes for constant addresses. */
151: #define FIXED_REGISTERS \
152: {1, 1, 1, 1, 0, 0, 0, 0, \
153: 0, 0, 0, 0, 0, 0, 0, 0, \
154: 0, 0, 0, 0, 0, 0, 0, 0, \
155: 0, 0, 0, 0, 0, 0, 0, 1, \
156: 1, 1, 0, 0, 0, 0, 0, 0, \
157: 0, 0, 0, 0, 0, 0, 0, 0, \
158: 0, 0, 0, 0, 0, 0, 0, 0, \
159: 0, 0, 0, 0, 0, 0, 0, 0}
160:
161: /* 1 for registers not available across function calls.
162: These must include the FIXED_REGISTERS and also any
163: registers that can be used without being saved.
164: On the i860, these are r0-r3, r16-r31, f0, f1, and f16-f31. */
165: #define CALL_USED_REGISTERS \
166: {1, 1, 1, 1, 0, 0, 0, 0, \
167: 0, 0, 0, 0, 0, 0, 0, 0, \
168: 1, 1, 1, 1, 1, 1, 1, 1, \
169: 1, 1, 1, 1, 1, 1, 1, 1, \
170: 1, 1, 0, 0, 0, 0, 0, 0, \
171: 1, 1, 1, 1, 1, 1, 1, 1, \
172: 1, 1, 1, 1, 1, 1, 1, 1, \
173: 1, 1, 1, 1, 1, 1, 1, 1}
174:
175: /* Try to get a non-preserved register before trying to get one we will
176: have to preserve. Try to get an FP register only *after* trying to
177: get a general register, because it is relatively expensive to move
178: into or out of an FP register. */
179:
180: #define REG_ALLOC_ORDER \
181: {31, 30, 29, 28, 27, 26, 25, 24, \
182: 23, 22, 21, 20, 19, 18, 17, 16, \
183: 15, 14, 13, 12, 11, 10, 9, 8, \
184: 7, 6, 5, 4, 3, 2, 1, 0, \
185: 63, 62, 61, 60, 59, 58, 57, 56, \
186: 55, 54, 53, 52, 51, 50, 49, 48, \
187: 47, 46, 45, 44, 43, 42, 41, 40, \
188: 39, 38, 37, 36, 35, 34, 33, 32}
189:
190: /* Return number of consecutive hard regs needed starting at reg REGNO
191: to hold something of mode MODE.
192: This is ordinarily the length in words of a value of mode MODE
193: but can be less for certain modes in special long registers.
194:
195: On the i860, all registers hold 32 bits worth. */
196: #define HARD_REGNO_NREGS(REGNO, MODE) \
197: (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
198:
199: #define REGNO_MODE_ALIGNED(REGNO, MODE) \
200: (((REGNO) % ((GET_MODE_UNIT_SIZE (MODE) + 3) / 4)) == 0)
201:
202: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
203:
204: On the i860, we allow anything to go into any registers, but we require
205: any sort of value going into the FP registers to be properly aligned
206: (based on its size) within the FP register set.
207: */
208: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
209: (((REGNO) < 32) \
210: || (MODE) == VOIDmode || (MODE) == BLKmode \
211: || REGNO_MODE_ALIGNED (REGNO, MODE))
212:
213: /* Value is 1 if it is a good idea to tie two pseudo registers
214: when one has mode MODE1 and one has mode MODE2.
215: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
216: for any hard reg, then this must be 0 for correct output. */
217: /* I think that is not always true; alignment restrictions for doubles
218: should not prevent tying them with singles. So try allowing that.
219: On the other hand, don't let fixed and floating be tied;
220: this restriction is not necessary, but may make better code. */
221: #define MODES_TIEABLE_P(MODE1, MODE2) \
222: ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
223: || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
224: == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
225: || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
226:
227: /* Specify the registers used for certain standard purposes.
228: The values of these macros are register numbers. */
229:
230: /* i860 pc isn't overloaded on a register that the compiler knows about. */
231: /* #define PC_REGNUM */
232:
233: /* Register to use for pushing function arguments. */
234: #define STACK_POINTER_REGNUM 2
235:
236: /* Base register for access to local variables of the function. */
237: #define FRAME_POINTER_REGNUM 3
238:
239: /* Value should be nonzero if functions must have frame pointers.
240: Zero means the frame pointer need not be set up (and parms
241: may be accessed via the stack pointer) in functions that seem suitable.
242: This is computed in `reload', in reload1.c. */
243: #define FRAME_POINTER_REQUIRED 1
244:
245: /* Base register for access to arguments of the function. */
246: #define ARG_POINTER_REGNUM 28
247:
248: /* Register in which static-chain is passed to a function. */
249: #define STATIC_CHAIN_REGNUM 29
250:
251: /* Register in which address to store a structure value
252: is passed to a function. */
253: #define STRUCT_VALUE_REGNUM 16
254:
255: /* Register to use when a source of a floating-point zero is needed. */
256: #define F0_REGNUM 32
257:
258: /* Define the classes of registers for register constraints in the
259: machine description. Also define ranges of constants.
260:
261: One of the classes must always be named ALL_REGS and include all hard regs.
262: If there is more than one class, another class must be named NO_REGS
263: and contain no registers.
264:
265: The name GENERAL_REGS must be the name of a class (or an alias for
266: another name such as ALL_REGS). This is the class of registers
267: that is allowed by "g" or "r" in a register constraint.
268: Also, registers outside this class are allocated only when
269: instructions express preferences for them.
270:
271: The classes must be numbered in nondecreasing order; that is,
272: a larger-numbered class must never be contained completely
273: in a smaller-numbered class.
274:
275: For any two classes, it is very desirable that there be another
276: class that represents their union. */
277:
278: /* The i860 has two kinds of registers, hence four classes. */
279:
280: enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES };
281:
282: #define N_REG_CLASSES (int) LIM_REG_CLASSES
283:
284: /* Give names of register classes as strings for dump file. */
285:
286: #define REG_CLASS_NAMES \
287: {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
288:
289: /* Define which registers fit in which classes.
290: This is an initializer for a vector of HARD_REG_SET
291: of length N_REG_CLASSES. */
292:
293: #define REG_CLASS_CONTENTS \
294: {{0, 0}, {0xffffffff, 0}, \
295: {0, 0xffffffff}, {0xffffffff, 0xffffffff}}
296:
297: /* The same information, inverted:
298: Return the class number of the smallest class containing
299: reg number REGNO. This could be a conditional expression
300: or could index an array. */
301:
302: #define REGNO_REG_CLASS(REGNO) \
303: ((REGNO) >= 32 ? FP_REGS : GENERAL_REGS)
304:
305: /* The class value for index registers, and the one for base regs. */
306: #define INDEX_REG_CLASS GENERAL_REGS
307: #define BASE_REG_CLASS GENERAL_REGS
308:
309: /* Get reg_class from a letter such as appears in the machine description. */
310:
311: #define REG_CLASS_FROM_LETTER(C) \
312: ((C) == 'f' ? FP_REGS : NO_REGS)
313:
314: /* The letters I, J, K, L and M in a register constraint string
315: can be used to stand for particular ranges of immediate operands.
316: This macro defines what the ranges are.
317: C is the letter, and VALUE is a constant value.
318: Return 1 if VALUE is in the range specified by C.
319:
320: For the i860, `I' is used for the range of constants
321: an add/subtract insn can actually contain.
322: But not including -0x8000, since we need
323: to negate the constant sometimes.
324: `J' is used for the range which is just zero (since that is R0).
325: `K' is used for the range allowed in bte.
326: `L' is used for the range allowed in logical insns. */
327:
328: #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x7fff) < 0xffff)
329:
330: #define LOGIC_INT(X) ((unsigned) INTVAL (X) < 0x10000)
331:
332: #define SMALL_INTVAL(X) ((unsigned) ((X) + 0x7fff) < 0xffff)
333:
334: #define LOGIC_INTVAL(X) ((unsigned) (X) < 0x10000)
335:
336: #define CONST_OK_FOR_LETTER_P(VALUE, C) \
337: ((C) == 'I' ? ((unsigned) (VALUE) + 0x7fff) < 0xffff \
338: : (C) == 'J' ? (VALUE) == 0 \
339: : (C) == 'K' ? (unsigned) (VALUE) < 0x20 \
340: : (C) == 'L' ? (unsigned) (VALUE) < 0x10000 \
341: : 0)
342:
343: /* Return non-zero if the given VALUE is acceptable for the
344: constraint letter C. For the i860, constraint letter 'G'
345: permits only a floating-point zero value. */
346: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
347: ((C) == 'G' && CONST_DOUBLE_LOW ((VALUE)) == 0 \
348: && CONST_DOUBLE_HIGH ((VALUE)) == 0)
349:
350: /* Given an rtx X being reloaded into a reg required to be
351: in class CLASS, return the class of reg to actually use.
352: In general this is just CLASS; but on some machines
353: in some cases it is preferable to use a more restrictive class.
354:
355: If we are trying to put an integer constant into some register, prefer an
356: integer register to an FP register. If we are trying to put a
357: non-zero floating-point constant into some register, use an integer
358: register if the constant is SFmode and GENERAL_REGS is one of our options.
359: Otherwise, put the constant into memory.
360:
361: When reloading something smaller than a word, use a general reg
362: rather than an FP reg. */
363:
364: #define PREFERRED_RELOAD_CLASS(X,CLASS) \
365: ((CLASS) == ALL_REGS && GET_CODE (X) == CONST_INT ? GENERAL_REGS \
366: : ((GET_MODE (X) == HImode || GET_MODE (X) == QImode) \
367: && (CLASS) == ALL_REGS) \
368: ? GENERAL_REGS \
369: : (GET_CODE (X) == CONST_DOUBLE \
370: && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
371: && ! CONST_DOUBLE_OK_FOR_LETTER_P (X, 'G')) \
372: ? ((CLASS) == ALL_REGS && GET_MODE (X) == SFmode ? GENERAL_REGS \
373: : (CLASS) == GENERAL_REGS && GET_MODE (X) == SFmode ? (CLASS) \
374: : NO_REGS) \
375: : (CLASS))
376:
377: /* Return the register class of a scratch register needed to copy IN into
378: a register in CLASS in MODE. If it can be done directly, NO_REGS is
379: returned. */
380:
381: #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
382: ((CLASS) == FP_REGS && CONSTANT_P (IN) ? GENERAL_REGS : NO_REGS)
383:
384: /* Return the maximum number of consecutive registers
385: needed to represent mode MODE in a register of class CLASS. */
386: /* On the i860, this is the size of MODE in words. */
387: #define CLASS_MAX_NREGS(CLASS, MODE) \
388: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
389:
390: /* Stack layout; function entry, exit and calling. */
391:
392: /* Define this if pushing a word on the stack
393: makes the stack pointer a smaller address. */
394: #define STACK_GROWS_DOWNWARD
395:
396: /* Define this if the nominal address of the stack frame
397: is at the high-address end of the local variables;
398: that is, each additional local variable allocated
399: goes at a more negative offset in the frame. */
400: #define FRAME_GROWS_DOWNWARD
401:
402: /* Offset within stack frame to start allocating local variables at.
403: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
404: first local allocated. Otherwise, it is the offset to the BEGINNING
405: of the first local allocated. */
406: #define STARTING_FRAME_OFFSET 0
407:
408: /* If we generate an insn to push BYTES bytes,
409: this says how many the stack pointer really advances by.
410: On the i860, don't define this because there are no push insns. */
411: /* #define PUSH_ROUNDING(BYTES) */
412:
413: /* Offset of first parameter from the argument pointer register value. */
414: #define FIRST_PARM_OFFSET(FNDECL) 0
415:
416: /* Value is the number of bytes of arguments automatically
417: popped when returning from a subroutine call.
418: FUNTYPE is the data type of the function (as a tree),
419: or for a library call it is an identifier node for the subroutine name.
420: SIZE is the number of bytes of arguments passed on the stack. */
421:
422: #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
423:
424: /* Define how to find the value returned by a function.
425: VALTYPE is the data type of the value (as a tree).
426: If the precise function being called is known, FUNC is its FUNCTION_DECL;
427: otherwise, FUNC is 0. */
428:
429: /* On the i860, the value register depends on the mode. */
430:
431: #define FUNCTION_VALUE(VALTYPE, FUNC) \
432: gen_rtx (REG, TYPE_MODE (VALTYPE), \
433: (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
434: ? 40 : 16))
435:
436: /* Define how to find the value returned by a library function
437: assuming the value has mode MODE. */
438:
439: #define LIBCALL_VALUE(MODE) \
440: gen_rtx (REG, MODE, \
441: (GET_MODE_CLASS ((MODE)) == MODE_FLOAT \
442: ? 40 : 16))
443:
444: /* 1 if N is a possible register number for a function value
445: as seen by the caller. */
446:
447: #define FUNCTION_VALUE_REGNO_P(N) ((N) == 40 || (N) == 16)
448:
449: /* 1 if N is a possible register number for function argument passing.
450: On the i860, these are r16-r27 and f8-f15. */
451:
452: #define FUNCTION_ARG_REGNO_P(N) \
453: (((N) < 28 && (N) > 15) || ((N) < 48 && (N) >= 40))
454:
455: /* Define a data type for recording info about an argument list
456: during the scan of that argument list. This data type should
457: hold all necessary information about the function itself
458: and about the args processed so far, enough to enable macros
459: such as FUNCTION_ARG to determine where the next arg should go.
460:
461: On the i860, we must count separately the number of general registers used
462: and the number of float registers used. */
463:
464: struct cumulative_args { int ints, floats; };
465: #define CUMULATIVE_ARGS struct cumulative_args
466:
467: /* Initialize a variable CUM of type CUMULATIVE_ARGS
468: for a call to a function whose data type is FNTYPE.
469: For a library call, FNTYPE is 0.
470:
471: On the i860, the general-reg offset normally starts at 0,
472: but starts at 4 bytes
473: when the function gets a structure-value-address as an
474: invisible first argument. */
475:
476: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
477: ((CUM).ints = ((FNTYPE) != 0 && aggregate_value_p (TREE_TYPE ((FNTYPE))) \
478: ? 4 : 0), \
479: (CUM).floats = 0)
480:
481: /* Machine-specific subroutines of the following macros. */
482: #define CEILING(X,Y) (((X) + (Y) - 1) / (Y))
483: #define ROUNDUP(X,Y) (CEILING ((X), (Y)) * (Y))
484:
485: /* Update the data in CUM to advance over an argument
486: of mode MODE and data type TYPE.
487: (TYPE is null for libcalls where that information may not be available.)
488: Floats, and doubleword ints, are returned in f regs;
489: other ints, in r regs.
490: Aggregates, even short ones, are passed in memory. */
491:
492: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
493: ((TYPE) != 0 && (TREE_CODE ((TYPE)) == RECORD_TYPE \
494: || TREE_CODE ((TYPE)) == UNION_TYPE) \
495: ? 0 \
496: : GET_MODE_CLASS ((MODE)) == MODE_FLOAT || (MODE) == DImode \
497: ? ((CUM).floats = (ROUNDUP ((CUM).floats, GET_MODE_SIZE ((MODE))) \
498: + ROUNDUP (GET_MODE_SIZE (MODE), 4))) \
499: : GET_MODE_CLASS ((MODE)) == MODE_INT \
500: ? ((CUM).ints = (ROUNDUP ((CUM).ints, GET_MODE_SIZE ((MODE))) \
501: + ROUNDUP (GET_MODE_SIZE (MODE), 4))) \
502: : 0)
503:
504: /* Determine where to put an argument to a function.
505: Value is zero to push the argument on the stack,
506: or a hard register in which to store the argument.
507:
508: MODE is the argument's machine mode.
509: TYPE is the data type of the argument (as a tree).
510: This is null for libcalls where that information may
511: not be available.
512: CUM is a variable of type CUMULATIVE_ARGS which gives info about
513: the preceding args and about the function being called.
514: NAMED is nonzero if this argument is a named parameter
515: (otherwise it is an extra parameter matching an ellipsis). */
516:
517: /* On the i860, the first 12 words of integer arguments go in r16-r27,
518: and the first 8 words of floating arguments go in f8-f15.
519: DImode values are treated as floats. */
520:
521: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
522: ((TYPE) != 0 && (TREE_CODE ((TYPE)) == RECORD_TYPE \
523: || TREE_CODE ((TYPE)) == UNION_TYPE) \
524: ? 0 \
525: : GET_MODE_CLASS ((MODE)) == MODE_FLOAT || (MODE) == DImode \
526: ? (ROUNDUP ((CUM).floats, GET_MODE_SIZE ((MODE))) < 32 \
527: ? gen_rtx (REG, (MODE), \
528: 40+(ROUNDUP ((CUM).floats, \
529: GET_MODE_SIZE ((MODE))) \
530: / 4)) \
531: : 0) \
532: : GET_MODE_CLASS ((MODE)) == MODE_INT \
533: ? (ROUNDUP ((CUM).ints, GET_MODE_SIZE ((MODE))) < 48 \
534: ? gen_rtx (REG, (MODE), \
535: 16+(ROUNDUP ((CUM).ints, \
536: GET_MODE_SIZE ((MODE))) \
537: / 4)) \
538: : 0) \
539: : 0)
540:
541: /* For an arg passed partly in registers and partly in memory,
542: this is the number of registers used.
543: For args passed entirely in registers or entirely in memory, zero. */
544:
545: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
546:
547: /* If defined, a C expression that gives the alignment boundary, in
548: bits, of an argument with the specified mode and type. If it is
549: not defined, `PARM_BOUNDARY' is used for all arguments. */
550:
551: #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
552: (((TYPE) != 0) \
553: ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
554: ? PARM_BOUNDARY \
555: : TYPE_ALIGN(TYPE)) \
556: : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
557: ? PARM_BOUNDARY \
558: : GET_MODE_ALIGNMENT(MODE)))
559:
560: /* This macro generates the assembly code for function entry.
561:
562: FILE is a stdio stream to output the code to.
563: SIZE is an int: how many units of temporary storage to allocate.
564: */
565:
566: #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue ((FILE), (SIZE))
567:
568: /* Output a no-op just before the beginning of the function,
569: to ensure that there does not appear to be a delayed branch there.
570: Such a thing would confuse interrupt recovery. */
571: #define ASM_OUTPUT_FUNCTION_PREFIX(FILE,NAME) \
572: fprintf (FILE, "\tnop\n")
573:
574: /* Output assembler code to FILE to increment profiler label # LABELNO
575: for profiling a function entry. */
576:
577: #define FUNCTION_PROFILER(FILE, LABELNO) \
578: abort ();
579:
580: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
581: the stack pointer does not matter. The value is tested only in
582: functions that have frame pointers.
583: No definition is equivalent to always zero. */
584:
585: #define EXIT_IGNORE_STACK 1
586:
587: /* This macro generates the assembly code for function exit.
588:
589: FILE is a stdio stream to output the code to.
590: SIZE is an int: how many units of temporary storage to allocate.
591:
592: The function epilogue should not depend on the current stack pointer!
593: It should use the frame pointer only. This is mandatory because
594: of alloca; we also take advantage of it to omit stack adjustments
595: before returning.
596: */
597:
598: #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue ((FILE), (SIZE))
599:
600: /* Store in the variable DEPTH the initial difference between the
601: frame pointer reg contents and the stack pointer reg contents,
602: as of the start of the function body. This depends on the layout
603: of the fixed parts of the stack frame and on how registers are saved.
604:
605: On the i860, FRAME_POINTER_REQUIRED is always 1, so the definition of this
606: macro doesn't matter. But it must be defined. */
607:
608: #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
609: do { (DEPTH) = 0; } while (0)
610:
611: /* Output assembler code for a block containing the constant parts
612: of a trampoline, leaving space for the variable parts. */
613:
614: /* On the i860, the trampoline contains five instructions:
615: orh #TOP_OF_FUNCTION,r0,r31
616: or #BOTTOM_OF_FUNCTION,r31,r31
617: orh #TOP_OF_STATIC,r0,r29
618: bri r31
619: or #BOTTOM_OF_STATIC,r29,r29 */
620: #define TRAMPOLINE_TEMPLATE(FILE) \
621: { \
622: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xec1f0000)); \
623: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xe7ff0000)); \
624: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xec1d0000)); \
625: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x4000f800)); \
626: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xe7bd0000)); \
627: }
628:
629: /* Length in units of the trampoline for entering a nested function. */
630:
631: #define TRAMPOLINE_SIZE 20
632:
633: /* Emit RTL insns to initialize the variable parts of a trampoline.
634: FNADDR is an RTX for the address of the function's pure code.
635: CXT is an RTX for the static chain value for the function.
636:
637: Store hi function at +0, low function at +4,
638: hi static at +8, low static at +16 */
639:
640: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
641: { \
642: rtx cxt = force_reg (Pmode, CXT); \
643: rtx fn = force_reg (Pmode, FNADDR); \
644: rtx hi_cxt = expand_shift (RSHIFT_EXPR, SImode, cxt, \
645: size_int (16), 0, 0); \
646: rtx hi_fn = expand_shift (RSHIFT_EXPR, SImode, fn, \
647: size_int (16), 0, 0); \
648: emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 16)), \
649: gen_lowpart (HImode, cxt)); \
650: emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 4)), \
651: gen_lowpart (HImode, fn)); \
652: emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 8)), \
653: gen_lowpart (HImode, hi_cxt)); \
654: emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 0)), \
655: gen_lowpart (HImode, hi_fn)); \
656: }
657:
658: /* Addressing modes, and classification of registers for them. */
659:
660: /* #define HAVE_POST_INCREMENT */
661: /* #define HAVE_POST_DECREMENT */
662:
663: /* #define HAVE_PRE_DECREMENT */
664: /* #define HAVE_PRE_INCREMENT */
665:
666: /* Macros to check register numbers against specific register classes. */
667:
668: /* These assume that REGNO is a hard or pseudo reg number.
669: They give nonzero only if REGNO is a hard reg of the suitable class
670: or a pseudo reg currently allocated to a suitable hard reg.
671: Since they use reg_renumber, they are safe only once reg_renumber
672: has been allocated, which happens in local-alloc.c. */
673:
674: #define REGNO_OK_FOR_INDEX_P(REGNO) \
675: ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
676: #define REGNO_OK_FOR_BASE_P(REGNO) \
677: ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
678: #define REGNO_OK_FOR_FP_P(REGNO) \
679: (((REGNO) ^ 0x20) < 32 || (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32)
680:
681: /* Now macros that check whether X is a register and also,
682: strictly, whether it is in a specified class.
683:
684: These macros are specific to the i860, and may be used only
685: in code for printing assembler insns and in conditions for
686: define_optimization. */
687:
688: /* 1 if X is an fp register. */
689:
690: #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
691:
692: /* Maximum number of registers that can appear in a valid memory address. */
693:
694: #define MAX_REGS_PER_ADDRESS 2
695:
696: /* Recognize any constant value that is a valid address. */
697:
698: #define CONSTANT_ADDRESS_P(X) \
699: (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
700: || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
701: || GET_CODE (X) == HIGH)
702:
703: /* Nonzero if the constant value X is a legitimate general operand.
704: It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
705:
706: On the Sparc, this is anything but a CONST_DOUBLE.
707: Let's try permitting CONST_DOUBLEs and see what happens. */
708:
709: #define LEGITIMATE_CONSTANT_P(X) 1
710:
711: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
712: and check its validity for a certain class.
713: We have two alternate definitions for each of them.
714: The usual definition accepts all pseudo regs; the other rejects
715: them unless they have been allocated suitable hard regs.
716: The symbol REG_OK_STRICT causes the latter definition to be used.
717:
718: Most source files want to accept pseudo regs in the hope that
719: they will get allocated to the class that the insn wants them to be in.
720: Source files for reload pass need to be strict.
721: After reload, it makes no difference, since pseudo regs have
722: been eliminated by then. */
723:
724: #ifndef REG_OK_STRICT
725:
726: /* Nonzero if X is a hard reg that can be used as an index
727: or if it is a pseudo reg. */
728: #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 14)
729: /* Nonzero if X is a hard reg that can be used as a base reg
730: or if it is a pseudo reg. */
731: #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 14)
732:
733: #else
734:
735: /* Nonzero if X is a hard reg that can be used as an index. */
736: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
737: /* Nonzero if X is a hard reg that can be used as a base reg. */
738: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
739:
740: #endif
741:
742: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
743: that is a valid memory address for an instruction.
744: The MODE argument is the machine mode for the MEM expression
745: that wants to use this address.
746:
747: On the i860, the actual addresses must be REG+REG or REG+SMALLINT.
748: But we can treat a SYMBOL_REF as legitimate if it is part of this
749: function's constant-pool, because such addresses can actually
750: be output as REG+SMALLINT.
751:
752: The displacement in an address must be a multiple of the alignment.
753:
754: Try making SYMBOL_REF (and other things which are CONSTANT_ADDRESS_P)
755: a legitimate address, regardless. Because the only insns which can use
756: memory are load or store insns, the added hair in the machine description
757: is not that bad. It should also speed up the compiler by halving the number
758: of insns it must manage for each (MEM (SYMBOL_REF ...)) involved. */
759:
760: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
761: { if (GET_CODE (X) == REG) \
762: { if (REG_OK_FOR_BASE_P (X)) goto ADDR; } \
763: else if (GET_CODE (X) == PLUS) \
764: { \
765: if (GET_CODE (XEXP (X, 0)) == REG \
766: && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
767: { \
768: if (GET_CODE (XEXP (X, 1)) == CONST_INT \
769: && INTVAL (XEXP (X, 1)) >= -0x8000 \
770: && INTVAL (XEXP (X, 1)) < 0x8000 \
771: && (INTVAL (XEXP (X, 1)) & (GET_MODE_SIZE (MODE) - 1)) == 0) \
772: goto ADDR; \
773: } \
774: else if (GET_CODE (XEXP (X, 1)) == REG \
775: && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
776: { \
777: if (GET_CODE (XEXP (X, 0)) == CONST_INT \
778: && INTVAL (XEXP (X, 0)) >= -0x8000 \
779: && INTVAL (XEXP (X, 0)) < 0x8000 \
780: && (INTVAL (XEXP (X, 0)) & (GET_MODE_SIZE (MODE) - 1)) == 0) \
781: goto ADDR; \
782: } \
783: } \
784: else if (CONSTANT_ADDRESS_P (X)) \
785: goto ADDR; \
786: }
787:
788: /* Try machine-dependent ways of modifying an illegitimate address
789: to be legitimate. If we find one, return the new, valid address.
790: This macro is used in only one place: `memory_address' in explow.c.
791:
792: OLDX is the address as it was before break_out_memory_refs was called.
793: In some cases it is useful to look at this to decide what needs to be done.
794:
795: MODE and WIN are passed so that this macro can use
796: GO_IF_LEGITIMATE_ADDRESS.
797:
798: It is always safe for this macro to do nothing. It exists to recognize
799: opportunities to optimize the output. */
800:
801: /* On the i860, change COMPLICATED + CONSTANT to REG+CONSTANT.
802: Also change a symbolic constant to a REG,
803: though that may not be necessary. */
804:
805: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
806: { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
807: (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \
808: force_operand (XEXP (X, 0), 0)); \
809: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
810: (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \
811: force_operand (XEXP (X, 1), 0)); \
812: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
813: (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \
814: force_operand (XEXP (X, 0), 0)); \
815: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
816: (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \
817: force_operand (XEXP (X, 1), 0)); \
818: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) != REG \
819: && GET_CODE (XEXP (X, 0)) != CONST_INT) \
820: (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \
821: copy_to_mode_reg (SImode, XEXP (X, 0))); \
822: if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) != REG \
823: && GET_CODE (XEXP (X, 1)) != CONST_INT) \
824: (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \
825: copy_to_mode_reg (SImode, XEXP (X, 1))); \
826: if (GET_CODE (x) == SYMBOL_REF) \
827: (X) = copy_to_reg (X); \
828: if (GET_CODE (x) == CONST) \
829: (X) = copy_to_reg (X); \
830: if (memory_address_p (MODE, X)) \
831: goto WIN; }
832:
833: /* Go to LABEL if ADDR (a legitimate address expression)
834: has an effect that depends on the machine mode it is used for.
835: On the i860 this is never true.
836: There are some addresses that are invalid in wide modes
837: but valid for narrower modes, but they shouldn't affect
838: the places that use this macro. */
839:
840: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
841:
842: /* Specify the machine mode that this machine uses
843: for the index in the tablejump instruction. */
844: #define CASE_VECTOR_MODE SImode
845:
846: /* Define this if the tablejump instruction expects the table
847: to contain offsets from the address of the table.
848: Do not define this if the table should contain absolute addresses. */
849: /* #define CASE_VECTOR_PC_RELATIVE */
850:
851: /* Specify the tree operation to be used to convert reals to integers. */
852: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
853:
854: /* This is the kind of divide that is easiest to do in the general case. */
855: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
856:
857: /* Must pass floats to libgcc functions as doubles. */
858: #define LIBGCC_NEEDS_DOUBLE 1
859:
860: #define DIVSI3_LIBCALL "*.div"
861: #define UDIVSI3_LIBCALL "*.udiv"
862: #define REMSI3_LIBCALL "*.rem"
863: #define UREMSI3_LIBCALL "*.urem"
864:
865: /* Define this as 1 if `char' should by default be signed; else as 0. */
866: #define DEFAULT_SIGNED_CHAR 1
867:
868: /* Max number of bytes we can move from memory to memory
869: in one reasonably fast instruction. */
870: #define MOVE_MAX 16
871:
872: /* Nonzero if access to memory by bytes is slow and undesirable. */
873: #define SLOW_BYTE_ACCESS 0
874:
875: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
876: is done just by pretending it is already truncated. */
877: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
878:
879: /* Value is 1 if it generates better code to perform an unsigned comparison
880: on the given literal integer value in the given mode when we are only
881: looking for an equal/non-equal result. */
882: /* For the i860, if the immediate value has its high-order 27 bits zero,
883: then we want to engineer an unsigned comparison for EQ/NE because
884: such values can fit in the 5-bit immediate field of a bte or btne
885: instruction (which gets zero extended before comparing). For all
886: other immediate values on the i860, we will use signed compares
887: because that avoids the need for doing explicit xor's to zero_extend
888: the non-constant operand in cases where it was (mem:QI ...) or a
889: (mem:HI ...) which always gets automatically sign-extended by the
890: hardware upon loading. */
891:
892: #define LITERAL_COMPARE_BETTER_UNSIGNED(intval, mode) \
893: (((unsigned) (intval) & 0x1f) == (unsigned) (intval))
894:
895: /* Specify the machine mode that pointers have.
896: After generation of rtl, the compiler makes no further distinction
897: between pointers and any other objects of this machine mode. */
898: #define Pmode SImode
899:
900: /* A function address in a call instruction
901: is a byte address (for indexing purposes)
902: so give the MEM rtx a byte's mode. */
903: #define FUNCTION_MODE SImode
904:
905: /* Define this if addresses of constant functions
906: shouldn't be put through pseudo regs where they can be cse'd.
907: Desirable on machines where ordinary constants are expensive
908: but a CALL with constant address is cheap. */
909: #define NO_FUNCTION_CSE
910:
911: /* Compute the cost of computing a constant rtl expression RTX
912: whose rtx-code is CODE. The body of this macro is a portion
913: of a switch statement. If the code is computed here,
914: return it with a return statement. Otherwise, break from the switch. */
915:
916: #define CONST_COSTS(RTX,CODE, OUTER_CODE) \
917: case CONST_INT: \
918: if (INTVAL (RTX) == 0) \
919: return 0; \
920: if (INTVAL (RTX) < 0x2000 && INTVAL (RTX) >= -0x2000) return 1; \
921: case CONST: \
922: case LABEL_REF: \
923: case SYMBOL_REF: \
924: return 4; \
925: case CONST_DOUBLE: \
926: return 6;
927:
928: /* Specify the cost of a branch insn; roughly the number of extra insns that
929: should be added to avoid a branch.
930:
931: Set this to 3 on the i860 since branches may often take three cycles. */
932:
933: #define BRANCH_COST 3
934:
935: /* Tell final.c how to eliminate redundant test instructions. */
936:
937: /* Here we define machine-dependent flags and fields in cc_status
938: (see `conditions.h'). */
939:
940: /* This holds the value sourcing h%r31. We keep this info
941: around so that mem/mem ops, such as increment and decrement,
942: etc, can be performed reasonably. */
943: #define CC_STATUS_MDEP rtx
944:
945: #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0)
946:
947: #define CC_NEGATED 01000
948:
949: /* We use this macro in those places in the i860.md file where we would
950: normally just do a CC_STATUS_INIT (for other machines). This macro
951: differs from CC_STATUS_INIT in that it doesn't mess with the special
952: bits or fields which describe what is currently in the special r31
953: scratch register, but it does clear out everything that actually
954: relates to the condition code bit of the i860. */
955:
956: #define CC_STATUS_PARTIAL_INIT \
957: (cc_status.flags &= (CC_KNOW_HI_R31 | CC_HI_R31_ADJ), \
958: cc_status.value1 = 0, \
959: cc_status.value2 = 0)
960:
961: /* Nonzero if we know the value of h%r31. */
962: #define CC_KNOW_HI_R31 0100000
963:
964: /* Nonzero if h%r31 is actually ha%something, rather than h%something. */
965: #define CC_HI_R31_ADJ 0200000
966:
967: /* Store in cc_status the expressions
968: that the condition codes will describe
969: after execution of an instruction whose pattern is EXP.
970: Do not alter them if the instruction would not alter the cc's. */
971:
972: /* On the i860, only compare insns set a useful condition code. */
973:
974: #define NOTICE_UPDATE_CC(EXP, INSN) \
975: { cc_status.flags &= (CC_KNOW_HI_R31 | CC_HI_R31_ADJ); \
976: cc_status.value1 = 0; cc_status.value2 = 0; }
977:
978: /* Control the assembler format that we output. */
979:
980: /* Assembler pseudos to introduce constants of various size. */
981:
982: #define ASM_BYTE_OP "\t.byte"
983: #define ASM_SHORT "\t.short"
984: #define ASM_LONG "\t.long"
985: #define ASM_DOUBLE "\t.double"
986:
987: /* Output at beginning of assembler file. */
988: /* The .file command should always begin the output. */
989:
990: #define ASM_FILE_START(FILE)
991: #if 0
992: #define ASM_FILE_START(FILE) \
993: do { output_file_directive ((FILE), main_input_filename); \
994: if (optimize) ASM_FILE_START_1 (FILE); \
995: } while (0)
996: #endif
997:
998: #define ASM_FILE_START_1(FILE)
999:
1000: /* Output to assembler file text saying following lines
1001: may contain character constants, extra white space, comments, etc. */
1002:
1003: #define ASM_APP_ON ""
1004:
1005: /* Output to assembler file text saying following lines
1006: no longer contain unusual constructs. */
1007:
1008: #define ASM_APP_OFF ""
1009:
1010: /* Output before read-only data. */
1011:
1012: #define TEXT_SECTION_ASM_OP ".text"
1013:
1014: /* Output before writable data. */
1015:
1016: #define DATA_SECTION_ASM_OP ".data"
1017:
1018: /* How to refer to registers in assembler output.
1019: This sequence is indexed by compiler's hard-register-number (see above). */
1020:
1021: #define REGISTER_NAMES \
1022: {"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7", "r8", "r9", \
1023: "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
1024: "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
1025: "r30", "r31", \
1026: "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
1027: "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
1028: "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
1029: "f30", "f31" }
1030:
1031: /* How to renumber registers for dbx and gdb. */
1032:
1033: #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1034:
1035: /* This is how to output the definition of a user-level label named NAME,
1036: such as the label on a static function or variable NAME. */
1037:
1038: #define ASM_OUTPUT_LABEL(FILE,NAME) \
1039: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1040:
1041: /* This is how to output a command to make the user-level label named NAME
1042: defined for reference from other files. */
1043:
1044: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1045: do { fputs (".globl ", FILE); \
1046: assemble_name (FILE, NAME); \
1047: fputs ("\n", FILE); \
1048: } while (0)
1049:
1050: /* This is how to output a reference to a user-level label named NAME.
1051: `assemble_name' uses this.
1052:
1053: This definition is overridden in i860v4.h because under System V
1054: Release 4, user-level symbols are *not* prefixed with underscores in
1055: the generated assembly code. */
1056:
1057: #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1058: fprintf (FILE, "_%s", NAME)
1059:
1060: /* This is how to output an internal numbered label where
1061: PREFIX is the class of label and NUM is the number within the class. */
1062:
1063: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1064: fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
1065:
1066: /* This is how to output an internal numbered label which
1067: labels a jump table. */
1068:
1069: #undef ASM_OUTPUT_CASE_LABEL
1070: #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
1071: do { ASM_OUTPUT_ALIGN ((FILE), 2); \
1072: ASM_OUTPUT_INTERNAL_LABEL ((FILE), PREFIX, NUM); \
1073: } while (0)
1074:
1075: /* Output at the end of a jump table. */
1076:
1077: #define ASM_OUTPUT_CASE_END(FILE,NUM,INSN) \
1078: fprintf (FILE, ".text\n")
1079:
1080: /* This is how to store into the string LABEL
1081: the symbol_ref name of an internal numbered label where
1082: PREFIX is the class of label and NUM is the number within the class.
1083: This is suitable for output with `assemble_name'. */
1084:
1085: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1086: sprintf (LABEL, "*.%s%d", PREFIX, NUM)
1087:
1088: /* This is how to output an assembler line defining a `double' constant. */
1089:
1090: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1091: fprintf (FILE, "\t.double %.20e\n", (VALUE))
1092:
1093: /* This is how to output an assembler line defining a `float' constant. */
1094:
1095: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1096: fprintf (FILE, "\t.float %.12e\n", (VALUE))
1097:
1098: /* This is how to output an assembler line defining an `int' constant. */
1099:
1100: #define ASM_OUTPUT_INT(FILE,VALUE) \
1101: ( fprintf (FILE, "\t.long "), \
1102: output_addr_const (FILE, (VALUE)), \
1103: fprintf (FILE, "\n"))
1104:
1105: /* Likewise for `char' and `short' constants. */
1106:
1107: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1108: ( fprintf (FILE, "\t.short "), \
1109: output_addr_const (FILE, (VALUE)), \
1110: fprintf (FILE, "\n"))
1111:
1112: #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1113: ( fprintf (FILE, "\t.byte "), \
1114: output_addr_const (FILE, (VALUE)), \
1115: fprintf (FILE, "\n"))
1116:
1117: /* This is how to output an assembler line for a numeric constant byte. */
1118:
1119: #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1120: fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1121:
1122: /* This is how to output code to push a register on the stack.
1123: It need not be very fast code. */
1124:
1125: #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1126: fprintf (FILE, "\taddu -16,%ssp,%ssp\n\t%sst.l %s%s,0(%ssp)\n", \
1127: i860_reg_prefix, i860_reg_prefix, \
1128: ((REGNO) < 32 ? "" : "f"), \
1129: i860_reg_prefix, reg_names[REGNO], \
1130: i860_reg_prefix)
1131:
1132: /* This is how to output an insn to pop a register from the stack.
1133: It need not be very fast code. */
1134:
1135: #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1136: fprintf (FILE, "\t%sld.l 0(%ssp),%s%s\n\taddu 16,%ssp,%ssp\n", \
1137: ((REGNO) < 32 ? "" : "f"), \
1138: i860_reg_prefix, \
1139: i860_reg_prefix, reg_names[REGNO], \
1140: i860_reg_prefix, i860_reg_prefix)
1141:
1142: /* This is how to output an element of a case-vector that is absolute. */
1143:
1144: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1145: fprintf (FILE, "\t.long .L%d\n", VALUE)
1146:
1147: /* This is how to output an element of a case-vector that is relative.
1148: (The i860 does not use such vectors,
1149: but we must define this macro anyway.) */
1150:
1151: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1152: fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
1153:
1154: /* This is how to output an assembler line
1155: that says to advance the location counter
1156: to a multiple of 2**LOG bytes. */
1157:
1158: #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1159: if ((LOG) != 0) \
1160: fprintf (FILE, "\t.align %d\n", 1 << (LOG))
1161:
1162: #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1163: fprintf (FILE, "\t.blkb %u\n", (SIZE))
1164:
1165: /* This says how to output an assembler line
1166: to define a global common symbol. */
1167:
1168: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1169: ( fputs (".comm ", (FILE)), \
1170: assemble_name ((FILE), (NAME)), \
1171: fprintf ((FILE), ",%u\n", (ROUNDED)))
1172:
1173: /* This says how to output an assembler line
1174: to define a local common symbol. */
1175:
1176: #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1177: ( fputs (".lcomm ", (FILE)), \
1178: assemble_name ((FILE), (NAME)), \
1179: fprintf ((FILE), ",%u\n", (ROUNDED)))
1180:
1181: /* Store in OUTPUT a string (made with alloca) containing
1182: an assembler-name for a local static variable named NAME.
1183: LABELNO is an integer which is different for each call. */
1184:
1185: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1186: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1187: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1188:
1189: /* Define the parentheses used to group arithmetic operations
1190: in assembler code. */
1191:
1192: #define ASM_OPEN_PAREN "("
1193: #define ASM_CLOSE_PAREN ")"
1194:
1195: /* Define results of standard character escape sequences. */
1196: #define TARGET_BELL 007
1197: #define TARGET_BS 010
1198: #define TARGET_TAB 011
1199: #define TARGET_NEWLINE 012
1200: #define TARGET_VT 013
1201: #define TARGET_FF 014
1202: #define TARGET_CR 015
1203:
1204: /* Print operand X (an rtx) in assembler syntax to file FILE.
1205: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1206: For `%' followed by punctuation, CODE is the punctuation and X is null.
1207:
1208: In the following comments, the term "constant address" is used frequently.
1209: For an exact definition of what constitutes a "constant address" see the
1210: output_addr_const routine in final.c
1211:
1212: On the i860, the following target-specific special codes are recognized:
1213:
1214: `r' The operand can be anything, but if is is an immediate zero
1215: value (either integer or floating point) then it will be
1216: represented as `r0' or as `f0' (respectively).
1217:
1218: `m' The operand is a memory ref (to a constant address) but print
1219: its address as a constant.
1220:
1221: `L' The operand is a numeric constant, a constant address, or
1222: a memory ref to a constant address. Print the correct
1223: notation to yield the low part of the given value or
1224: address or the low part of the address of the referred
1225: to memory object.
1226:
1227: `H' The operand is a numeric constant, a constant address, or
1228: a memory ref to a constant address. Print the correct
1229: notation to yield the high part of the given value or
1230: address or the high part of the address of the referred
1231: to memory object.
1232:
1233: `h' The operand is a numeric constant, a constant address, or
1234: a memory ref to a constant address. Either print the
1235: correct notation to yield the plain high part of the
1236: given value or address (or the plain high part of the
1237: address of the memory object) or else print the correct
1238: notation to yield the "adjusted" high part of the given
1239: address (or of the address of the referred to memory object).
1240:
1241: The choice of what to print depends upon whether the address
1242: in question is relocatable or not. If it is relocatable,
1243: print the notation to get the adjusted high part. Otherwise
1244: just print the notation to get the plain high part. Note
1245: that "adjusted" high parts are generally used *only* when
1246: the next following instruction uses the low part of the
1247: address as an offset, as in `offset(reg)'.
1248:
1249: `R' The operand is a floating-pointer register. Print the
1250: name of the next following (32-bit) floating-point register.
1251: (This is used when moving a value into just the most
1252: significant part of a floating-point register pair.)
1253:
1254: `?' (takes no operand) Substitute the value of i860_reg_prefix
1255: at this point. The value of i860_reg_prefix is typically
1256: a null string for most i860 targets, but for System V
1257: Release 4 the i860 assembler syntax requires that all
1258: names of registers be prefixed with a percent-sign, so
1259: for SVR4, the value of i860_reg_prefix is initialized to
1260: "%" in i860.c.
1261: */
1262:
1263: extern char *i860_reg_prefix;
1264: extern unsigned long sfmode_constant_to_ulong ();
1265:
1266: #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '?')
1267:
1268: /* The following macro definition is overridden in i860v4.h
1269: because the svr4 i860 assembler required a different syntax
1270: for getting parts of constant/relocatable values. */
1271:
1272: #define PRINT_OPERAND_PART(FILE, X, PART_CODE) \
1273: do { fprintf (FILE, "%s%%", PART_CODE); \
1274: output_address (X); \
1275: } while (0)
1276:
1277: #define OPERAND_LOW_PART "l"
1278: #define OPERAND_HIGH_PART "h"
1279: /* NOTE: All documentation available for the i860 sez that you must
1280: use "ha" to get the relocated high part of a relocatable, but
1281: reality sez different. */
1282: #define OPERAND_HIGH_ADJ_PART "ha"
1283:
1284: #define PRINT_OPERAND(FILE, X, CODE) \
1285: { if ((CODE) == '?') \
1286: fprintf (FILE, "%s", i860_reg_prefix); \
1287: else if (CODE == 'R') \
1288: fprintf (FILE, "%s%s", i860_reg_prefix, reg_names[REGNO (X) + 1]); \
1289: else if (GET_CODE (X) == REG) \
1290: fprintf (FILE, "%s%s", i860_reg_prefix, reg_names[REGNO (X)]); \
1291: else if ((CODE) == 'm') \
1292: output_address (XEXP (X, 0)); \
1293: else if ((CODE) == 'L') \
1294: { \
1295: if (GET_CODE (X) == MEM) \
1296: PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_LOW_PART); \
1297: else \
1298: PRINT_OPERAND_PART (FILE, X, OPERAND_LOW_PART); \
1299: } \
1300: else if ((CODE) == 'H') \
1301: { \
1302: if (GET_CODE (X) == MEM) \
1303: PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_PART); \
1304: else \
1305: PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_PART); \
1306: } \
1307: else if ((CODE) == 'h') \
1308: { \
1309: if (GET_CODE (X) == MEM) \
1310: PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_ADJ_PART); \
1311: else \
1312: PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_ADJ_PART); \
1313: } \
1314: else if (GET_CODE (X) == MEM) \
1315: output_address (XEXP (X, 0)); \
1316: else if ((CODE) == 'r' && (X) == const0_rtx) \
1317: fprintf (FILE, "%sr0", i860_reg_prefix); \
1318: else if ((CODE) == 'r' && (X) == CONST0_RTX (GET_MODE (X))) \
1319: fprintf (FILE, "%sf0", i860_reg_prefix); \
1320: else if (GET_CODE (X) == CONST_DOUBLE) \
1321: fprintf (FILE, "0x%x", sfmode_constant_to_ulong (X)); \
1322: else \
1323: output_addr_const (FILE, X); }
1324:
1325: /* Print a memory address as an operand to reference that memory location. */
1326:
1327: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1328: { register rtx base, index = 0; \
1329: int offset = 0; \
1330: register rtx addr = ADDR; \
1331: if (GET_CODE (addr) == REG) \
1332: { \
1333: fprintf (FILE, "0(%s%s)", \
1334: i860_reg_prefix, reg_names[REGNO (addr)]); \
1335: } \
1336: else if (GET_CODE (addr) == CONST_DOUBLE \
1337: && GET_MODE (addr) == SFmode) \
1338: fprintf (FILE, "0x%x", sfmode_constant_to_ulong (addr)); \
1339: else if (GET_CODE (addr) == PLUS) \
1340: { \
1341: if ((GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1342: && (GET_CODE (XEXP (addr, 1)) == REG)) \
1343: fprintf (FILE, "%d(%s%s)", INTVAL (XEXP (addr, 0)), \
1344: i860_reg_prefix, reg_names[REGNO (XEXP (addr, 1))]);\
1345: else if ((GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1346: && (GET_CODE (XEXP (addr, 0)) == REG)) \
1347: fprintf (FILE, "%d(%s%s)", INTVAL (XEXP (addr, 1)), \
1348: i860_reg_prefix, reg_names[REGNO (XEXP (addr, 0))]);\
1349: else if ((GET_CODE (XEXP (addr, 0)) == REG) \
1350: && (GET_CODE (XEXP (addr, 1)) == REG)) \
1351: fprintf (FILE, "%s%s(%s%s)", \
1352: i860_reg_prefix, reg_names[REGNO (XEXP (addr, 0))], \
1353: i860_reg_prefix, reg_names[REGNO (XEXP (addr, 1))]);\
1354: else \
1355: output_addr_const (FILE, addr); \
1356: } \
1357: else \
1358: { \
1359: output_addr_const (FILE, addr); \
1360: } \
1361: }
1362:
1363: /* The following #defines are used when compiling the routines in
1364: libgcc1.c. Since the i860 calling conventions require single
1365: precision floats to be passed in the floating-point registers
1366: (rather than in the general registers) we have to build the
1367: libgcc1.c routines in such a way that they know the actual types
1368: of their formal arguments and the actual types of their return
1369: values. Otherwise, gcc will generate calls to the libgcc1.c
1370: routines, passing arguments in the floating-point registers,
1371: but the libgcc1.c routines will expect their arguments on the
1372: stack (where the i860 calling conventions require structs &
1373: unions to be passed). */
1374:
1375: #define FLOAT_TYPE_VALUE float
1376: #define INTIFY(FLOATVAL) (FLOATVAL)
1377: #define FLOATIFY(INTVAL) (INTVAL)
1378: #define FLOAT_ARG_TYPE float
1379:
1380:
1381: /* Optionally define this if you have added predicates to
1382: `MACHINE.c'. This macro is called within an initializer of an
1383: array of structures. The first field in the structure is the
1384: name of a predicate and the second field is an array of rtl
1385: codes. For each predicate, list all rtl codes that can be in
1386: expressions matched by the predicate. The list should have a
1387: trailing comma. Here is an example of two entries in the list
1388: for a typical RISC machine:
1389:
1390: #define PREDICATE_CODES \
1391: {"gen_reg_rtx_operand", {SUBREG, REG}}, \
1392: {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
1393:
1394: Defining this macro does not affect the generated code (however,
1395: incorrect definitions that omit an rtl code that may be matched
1396: by the predicate can cause the compiler to malfunction).
1397: Instead, it allows the table built by `genrecog' to be more
1398: compact and efficient, thus speeding up the compiler. The most
1399: important predicates to include in the list specified by this
1400: macro are thoses used in the most insn patterns. */
1401:
1402: #define PREDICATE_CODES \
1403: {"reg_or_0_operand", {REG, SUBREG, CONST_INT}}, \
1404: {"arith_operand", {REG, SUBREG, CONST_INT}}, \
1405: {"logic_operand", {REG, SUBREG, CONST_INT}}, \
1406: {"shift_operand", {REG, SUBREG, CONST_INT}}, \
1407: {"compare_operand", {REG, SUBREG, CONST_INT}}, \
1408: {"arith_const_operand", {CONST_INT}}, \
1409: {"logic_const_operand", {CONST_INT}}, \
1410: {"bte_operand", {REG, SUBREG, CONST_INT}}, \
1411: {"indexed_operand", {MEM}}, \
1412: {"load_operand", {MEM}}, \
1413: {"small_int", {CONST_INT}}, \
1414: {"logic_int", {CONST_INT}}, \
1415: {"call_insn_operand", {MEM}},
1416:
1417: /* Define the information needed to generate branch insns. This is stored
1418: from the compare operation. Note that we can't use "rtx" here since it
1419: hasn't been defined! */
1420:
1421: extern struct rtx_def *i860_compare_op0, *i860_compare_op1;
1422:
1423: /* Declare things which are defined in i860.c but called from
1424: insn-output.c. */
1425:
1426: extern unsigned long sfmode_constant_to_ulong ();
1427: extern char *output_load ();
1428: extern char *output_store ();
1429: extern char *output_move_double ();
1430: extern char *output_fp_move_double ();
1431: extern char *output_block_move ();
1432: extern char *output_delay_insn ();
1433: extern char *output_delayed_branch ();
1434: extern void output_load_address ();
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