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1.1 root 1: /* Definitions of target machine for GNU compiler, for Intel 80960
2: Copyright (C) 1992, 1993 Free Software Foundation, Inc.
3: Contributed by Steven McGeady, Intel Corp.
4: Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5: Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
6:
7: This file is part of GNU CC.
8:
9: GNU CC is free software; you can redistribute it and/or modify
10: it under the terms of the GNU General Public License as published by
11: the Free Software Foundation; either version 2, or (at your option)
12: any later version.
13:
14: GNU CC is distributed in the hope that it will be useful,
15: but WITHOUT ANY WARRANTY; without even the implied warranty of
16: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17: GNU General Public License for more details.
18:
19: You should have received a copy of the GNU General Public License
20: along with GNU CC; see the file COPYING. If not, write to
21: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22:
23: /* Note that some other tm.h files may include this one and then override
24: many of the definitions that relate to assembler syntax. */
25:
26: /* Names to predefine in the preprocessor for this target machine. */
27: #define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960 -Acpu(i960) -Amachine(i960)"
28:
29: /* Name to predefine in the preprocessor for processor variations. */
30: #define CPP_SPEC "%{mic*:-D__i960\
31: %{mka:-D__i960KA}%{mkb:-D__i960KB}\
32: %{msa:-D__i960SA}%{msb:-D__i960SB}\
33: %{mmc:-D__i960MC}\
34: %{mca:-D__i960CA}%{mcc:-D__i960CC}\
35: %{mcf:-D__i960CF}}\
36: %{mka:-D__i960KA__ -D__i960_KA__}\
37: %{mkb:-D__i960KB__ -D__i960_KB__}\
38: %{msa:-D__i960SA__ -D__i960_SA__}\
39: %{msb:-D__i960SB__ -D__i960_SB__}\
40: %{mmc:-D__i960MC__ -D__i960_MC__}\
41: %{mca:-D__i960CA__ -D__i960_CA__}\
42: %{mcc:-D__i960CC__ -D__i960_CC__}\
43: %{mcf:-D__i960CF__ -D__i960_CF__}\
44: %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:\
45: %{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}"
46:
47: /* -mic* options make characters signed by default. */
48: #define SIGNED_CHAR_SPEC \
49: (DEFAULT_SIGNED_CHAR ? "%{funsigned-char:-D__CHAR_UNSIGNED__}" \
50: : "%{!fsigned-char:%{!mic*:-D__CHAR_UNSIGNED__}}")
51:
52: /* Specs for the compiler, to handle processor variations. */
53: #define CC1_SPEC \
54: "%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-mkb}}}}}}}}\
55: %{mbout:%{g*:-gstabs}}\
56: %{mcoff:%{g*:-gcoff}}\
57: %{!mbout:%{!mcoff:%{g*:-gstabs}}}"
58:
59: /* Specs for the assembler, to handle processor variations.
60: For compatibility with Intel's gnu960 tool chain, pass -A options to
61: the assembler. */
62: #define ASM_SPEC \
63: "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
64: %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
65: %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-AKB}}}}}}}}\
66: %{mlink-relax:-linkrelax}"
67:
68: /* Specs for the linker, to handle processor variations.
69: For compatibility with Intel's gnu960 tool chain, pass -F and -A options
70: to the linker. */
71: #define LINK_SPEC \
72: "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
73: %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
74: %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-AKB}}}}}}}}\
75: %{mbout:-Fbout}%{mcoff:-Fcoff}\
76: %{mlink-relax:-relax}"
77:
78: /* Specs for the libraries to link with, to handle processor variations.
79: Compatible with Intel's gnu960 tool chain. */
80: #define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\
81: %{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}"
82:
83: /* Omit frame pointer at -O2. Inline functions at -O3. */
84: #define OPTIMIZATION_OPTIONS(LEVEL) \
85: { \
86: if ((LEVEL) >= 2) \
87: { \
88: flag_omit_frame_pointer = 1; \
89: target_flags |= TARGET_FLAG_LEAFPROC; \
90: target_flags |= TARGET_FLAG_TAILCALL; \
91: } \
92: }
93:
94: /* Print subsidiary information on the compiler version in use. */
95: #define TARGET_VERSION fprintf (stderr," (intel 80960)");
96:
97: /* Generate DBX debugging information. */
98: #define DBX_DEBUGGING_INFO
99:
100: /* Generate SDB style debugging information. */
101: #define SDB_DEBUGGING_INFO
102:
103: /* Generate DBX_DEBUGGING_INFO by default. */
104: #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
105:
106: /* Redefine this to print in hex like iC960. */
107: #define PUT_SDB_TYPE(A) fprintf (asm_out_file, "\t.type\t0x%x;", A)
108:
109: /* Run-time compilation parameters selecting different hardware subsets. */
110:
111: /* 960 architecture with floating-point. */
112: #define TARGET_FLAG_NUMERICS 0x01
113: #define TARGET_NUMERICS (target_flags & TARGET_FLAG_NUMERICS)
114:
115: /* 960 architecture with memory management. */
116: /* ??? Not used currently. */
117: #define TARGET_FLAG_PROTECTED 0x02
118: #define TARGET_PROTECTED (target_flags & TARGET_FLAG_PROTECTED)
119:
120: /* The following three are mainly used to provide a little sanity checking
121: against the -mARCH flags given. */
122:
123: /* Nonzero if we should generate code for the KA and similar processors.
124: No FPU, no microcode instructions. */
125: #define TARGET_FLAG_K_SERIES 0x04
126: #define TARGET_K_SERIES (target_flags & TARGET_FLAG_K_SERIES)
127:
128: /* Nonzero if we should generate code for the MC processor.
129: Not really different from KB for our purposes. */
130: #define TARGET_FLAG_MC 0x08
131: #define TARGET_MC (target_flags & TARGET_FLAG_MC)
132:
133: /* Nonzero if we should generate code for the CA processor.
134: Enables different optimization strategies. */
135: #define TARGET_FLAG_C_SERIES 0x10
136: #define TARGET_C_SERIES (target_flags & TARGET_FLAG_C_SERIES)
137:
138: /* Nonzero if we should generate leaf-procedures when we find them.
139: You may not want to do this because leaf-proc entries are
140: slower when not entered via BAL - this would be true when
141: a linker not supporting the optimization is used. */
142: #define TARGET_FLAG_LEAFPROC 0x20
143: #define TARGET_LEAFPROC (target_flags & TARGET_FLAG_LEAFPROC)
144:
145: /* Nonzero if we should perform tail-call optimizations when we find them.
146: You may not want to do this because the detection of cases where
147: this is not valid is not totally complete. */
148: #define TARGET_FLAG_TAILCALL 0x40
149: #define TARGET_TAILCALL (target_flags & TARGET_FLAG_TAILCALL)
150:
151: /* Nonzero if use of a complex addressing mode is a win on this implementation.
152: Complex addressing modes are probably not worthwhile on the K-series,
153: but they definitely are on the C-series. */
154: #define TARGET_FLAG_COMPLEX_ADDR 0x80
155: #define TARGET_COMPLEX_ADDR (target_flags & TARGET_FLAG_COMPLEX_ADDR)
156:
157: /* Align code to 8 byte boundaries for faster fetching. */
158: #define TARGET_FLAG_CODE_ALIGN 0x100
159: #define TARGET_CODE_ALIGN (target_flags & TARGET_FLAG_CODE_ALIGN)
160:
161: /* Append branch prediction suffixes to branch opcodes. */
162: /* ??? Not used currently. */
163: #define TARGET_FLAG_BRANCH_PREDICT 0x200
164: #define TARGET_BRANCH_PREDICT (target_flags & TARGET_FLAG_BRANCH_PREDICT)
165:
166: /* Forces prototype and return promotions. */
167: /* ??? This does not work. */
168: #define TARGET_FLAG_CLEAN_LINKAGE 0x400
169: #define TARGET_CLEAN_LINKAGE (target_flags & TARGET_FLAG_CLEAN_LINKAGE)
170:
171: /* For compatibility with iC960 v3.0. */
172: #define TARGET_FLAG_IC_COMPAT3_0 0x800
173: #define TARGET_IC_COMPAT3_0 (target_flags & TARGET_FLAG_IC_COMPAT3_0)
174:
175: /* For compatibility with iC960 v2.0. */
176: #define TARGET_FLAG_IC_COMPAT2_0 0x1000
177: #define TARGET_IC_COMPAT2_0 (target_flags & TARGET_FLAG_IC_COMPAT2_0)
178:
179: /* If no unaligned accesses are to be permitted. */
180: #define TARGET_FLAG_STRICT_ALIGN 0x2000
181: #define TARGET_STRICT_ALIGN (target_flags & TARGET_FLAG_STRICT_ALIGN)
182:
183: /* For compatibility with iC960 assembler. */
184: #define TARGET_FLAG_ASM_COMPAT 0x4000
185: #define TARGET_ASM_COMPAT (target_flags & TARGET_FLAG_ASM_COMPAT)
186:
187: /* For compatibility with the gcc960 v1.2 compiler. Use the old structure
188: alignment rules. Also, turns on STRICT_ALIGNMENT. */
189: #define TARGET_FLAG_OLD_ALIGN 0x8000
190: #define TARGET_OLD_ALIGN (target_flags & TARGET_FLAG_OLD_ALIGN)
191:
192: extern int target_flags;
193:
194: /* Macro to define tables used to set the flags.
195: This is a list in braces of pairs in braces,
196: each pair being { "NAME", VALUE }
197: where VALUE is the bits to set or minus the bits to clear.
198: An empty string NAME is used to identify the default VALUE. */
199:
200: /* ??? Not all ten of these architecture variations actually exist, but I
201: am not sure which are real and which aren't. */
202:
203: #define TARGET_SWITCHES \
204: { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
205: {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
206: TARGET_FLAG_COMPLEX_ADDR)},\
207: /* {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
208: TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
209: {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
210: {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
211: TARGET_FLAG_COMPLEX_ADDR)},\
212: /* {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
213: TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
214: {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
215: TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\
216: {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
217: TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
218: /* {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES|\
219: TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN)},\
220: {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
221: TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
222: TARGET_FLAG_CODE_ALIGN)}, */ \
223: {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
224: TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
225: {"numerics", (TARGET_FLAG_NUMERICS)}, \
226: {"soft-float", -(TARGET_FLAG_NUMERICS)}, \
227: {"leaf-procedures", TARGET_FLAG_LEAFPROC}, \
228: {"no-leaf-procedures",-(TARGET_FLAG_LEAFPROC)}, \
229: {"tail-call",TARGET_FLAG_TAILCALL}, \
230: {"no-tail-call",-(TARGET_FLAG_TAILCALL)}, \
231: {"complex-addr",TARGET_FLAG_COMPLEX_ADDR}, \
232: {"no-complex-addr",-(TARGET_FLAG_COMPLEX_ADDR)}, \
233: {"code-align",TARGET_FLAG_CODE_ALIGN}, \
234: {"no-code-align",-(TARGET_FLAG_CODE_ALIGN)}, \
235: {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE)}, \
236: {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE)}, \
237: {"ic-compat", TARGET_FLAG_IC_COMPAT2_0}, \
238: {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0}, \
239: {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0}, \
240: {"asm-compat",TARGET_FLAG_ASM_COMPAT}, \
241: {"intel-asm",TARGET_FLAG_ASM_COMPAT}, \
242: {"strict-align", TARGET_FLAG_STRICT_ALIGN}, \
243: {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN)}, \
244: {"old-align", TARGET_FLAG_OLD_ALIGN}, \
245: {"no-old-align", -(TARGET_FLAG_OLD_ALIGN)}, \
246: {"link-relax", 0}, \
247: {"no-link-relax", 0}, \
248: { "", TARGET_DEFAULT}}
249:
250: /* Override conflicting target switch options.
251: Doesn't actually detect if more than one -mARCH option is given, but
252: does handle the case of two blatantly conflicting -mARCH options. */
253: #define OVERRIDE_OPTIONS \
254: { \
255: if (TARGET_K_SERIES && TARGET_C_SERIES) \
256: { \
257: warning ("conflicting architectures defined - using C series", 0); \
258: target_flags &= ~TARGET_FLAG_K_SERIES; \
259: } \
260: if (TARGET_K_SERIES && TARGET_MC) \
261: { \
262: warning ("conflicting architectures defined - using K series", 0); \
263: target_flags &= ~TARGET_FLAG_MC; \
264: } \
265: if (TARGET_C_SERIES && TARGET_MC) \
266: { \
267: warning ("conflicting architectures defined - using C series", 0);\
268: target_flags &= ~TARGET_FLAG_MC; \
269: } \
270: if (TARGET_IC_COMPAT3_0) \
271: { \
272: flag_short_enums = 1; \
273: flag_signed_char = 1; \
274: target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
275: if (TARGET_IC_COMPAT2_0) \
276: { \
277: warning ("iC2.0 and iC3.0 are incompatible - using iC3.0", 0); \
278: target_flags &= ~TARGET_FLAG_IC_COMPAT2_0; \
279: } \
280: } \
281: if (TARGET_IC_COMPAT2_0) \
282: { \
283: flag_signed_char = 1; \
284: target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
285: } \
286: i960_initialize (); \
287: }
288:
289: /* Don't enable anything by default. The user is expected to supply a -mARCH
290: option. If none is given, then -mkb is added by CC1_SPEC. */
291: #define TARGET_DEFAULT 0
292:
293: /* Target machine storage layout. */
294:
295: /* Define this if most significant bit is lowest numbered
296: in instructions that operate on numbered bit-fields. */
297: #define BITS_BIG_ENDIAN 0
298:
299: /* Define this if most significant byte of a word is the lowest numbered.
300: The i960 case be either big endian or little endian. We only support
301: little endian, which is the most common. */
302: #define BYTES_BIG_ENDIAN 0
303:
304: /* Define this if most significant word of a multiword number is lowest
305: numbered. */
306: #define WORDS_BIG_ENDIAN 0
307:
308: /* Number of bits in an addressable storage unit. */
309: #define BITS_PER_UNIT 8
310:
311: /* Bitfields cannot cross word boundaries. */
312: #define BITFIELD_NBYTES_LIMITED 1
313:
314: /* Width in bits of a "word", which is the contents of a machine register.
315: Note that this is not necessarily the width of data type `int';
316: if using 16-bit ints on a 68000, this would still be 32.
317: But on a machine with 16-bit registers, this would be 16. */
318: #define BITS_PER_WORD 32
319:
320: /* Width of a word, in units (bytes). */
321: #define UNITS_PER_WORD 4
322:
323: /* Width in bits of a pointer. See also the macro `Pmode' defined below. */
324: #define POINTER_SIZE 32
325:
326: /* Width in bits of a long double. Identical to double for now. */
327: #define LONG_DOUBLE_TYPE_SIZE 64
328:
329: /* Allocation boundary (in *bits*) for storing pointers in memory. */
330: #define POINTER_BOUNDARY 32
331:
332: /* Allocation boundary (in *bits*) for storing arguments in argument list. */
333: #define PARM_BOUNDARY 32
334:
335: /* Boundary (in *bits*) on which stack pointer should be aligned. */
336: #define STACK_BOUNDARY 128
337:
338: /* Allocation boundary (in *bits*) for the code of a function. */
339: #define FUNCTION_BOUNDARY 128
340:
341: /* Alignment of field after `int : 0' in a structure. */
342: #define EMPTY_FIELD_BOUNDARY 32
343:
344: /* This makes zero-length anonymous fields lay the next field
345: at a word boundary. It also makes the whole struct have
346: at least word alignment if there are any bitfields at all. */
347: #define PCC_BITFIELD_TYPE_MATTERS 1
348:
349: /* Every structure's size must be a multiple of this. */
350: #define STRUCTURE_SIZE_BOUNDARY 8
351:
352: /* No data type wants to be aligned rounder than this.
353: Extended precision floats gets 4-word alignment. */
354: #define BIGGEST_ALIGNMENT 128
355:
356: /* Define this if move instructions will actually fail to work
357: when given unaligned data.
358: 80960 will work even with unaligned data, but it is slow. */
359: #define STRICT_ALIGNMENT TARGET_OLD_ALIGN
360:
361: /* Specify alignment for string literals (which might be higher than the
362: base type's minimal alignment requirement. This allows strings to be
363: aligned on word boundaries, and optimizes calls to the str* and mem*
364: library functions. */
365: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
366: (TREE_CODE (EXP) == STRING_CST \
367: && i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (ALIGN) \
368: ? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \
369: : (ALIGN))
370:
371: /* Macros to determine size of aggregates (structures and unions
372: in C). Normally, these may be defined to simply return the maximum
373: alignment and simple rounded-up size, but on some machines (like
374: the i960), the total size of a structure is based on a non-trivial
375: rounding method. */
376:
377: #define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \
378: ((!TARGET_OLD_ALIGN && TREE_CODE (TYPE) == RECORD_TYPE) \
379: ? i960_round_align ((SPECIFIED), TYPE_SIZE (TYPE)) \
380: : MAX ((COMPUTED), (SPECIFIED)))
381:
382: #define ROUND_TYPE_SIZE(TYPE, SIZE, ALIGN) \
383: ((!TARGET_OLD_ALIGN && TREE_CODE (TYPE) == RECORD_TYPE) \
384: ? (tree) i960_round_size (SIZE) \
385: : round_up ((SIZE), (ALIGN)))
386:
387: /* Standard register usage. */
388:
389: /* Number of actual hardware registers.
390: The hardware registers are assigned numbers for the compiler
391: from 0 to just below FIRST_PSEUDO_REGISTER.
392: All registers that the compiler knows about must be given numbers,
393: even those that are not normally considered general registers.
394:
395: Registers 0-15 are the global registers (g0-g15).
396: Registers 16-31 are the local registers (r0-r15).
397: Register 32-35 are the fp registers (fp0-fp3).
398: Register 36 is the condition code register.
399: Register 37 is unused. */
400:
401: #define FIRST_PSEUDO_REGISTER 38
402:
403: /* 1 for registers that have pervasive standard uses and are not available
404: for the register allocator. On 80960, this includes the frame pointer
405: (g15), the previous FP (r0), the stack pointer (r1), the return
406: instruction pointer (r2), and the argument pointer (g14). */
407: #define FIXED_REGISTERS \
408: {0, 0, 0, 0, 0, 0, 0, 0, \
409: 0, 0, 0, 0, 0, 0, 1, 1, \
410: 1, 1, 1, 0, 0, 0, 0, 0, \
411: 0, 0, 0, 0, 0, 0, 0, 0, \
412: 0, 0, 0, 0, 1, 1}
413:
414: /* 1 for registers not available across function calls.
415: These must include the FIXED_REGISTERS and also any
416: registers that can be used without being saved.
417: The latter must include the registers where values are returned
418: and the register where structure-value addresses are passed.
419: Aside from that, you can include as many other registers as you like. */
420:
421: /* On the 80960, note that:
422: g0..g3 are used for return values,
423: g0..g7 may always be used for parameters,
424: g8..g11 may be used for parameters, but are preserved if they aren't,
425: g12 is always preserved, but otherwise unused,
426: g13 is the struct return ptr if used, or temp, but may be trashed,
427: g14 is the leaf return ptr or the arg block ptr otherwise zero,
428: must be reset to zero before returning if it was used,
429: g15 is the frame pointer,
430: r0 is the previous FP,
431: r1 is the stack pointer,
432: r2 is the return instruction pointer,
433: r3-r15 are always available,
434: r3 is clobbered by calls in functions that use the arg pointer
435: r4-r11 may be clobbered by the mcount call when profiling
436: r4-r15 if otherwise unused may be used for preserving global registers
437: fp0..fp3 are never available. */
438: #define CALL_USED_REGISTERS \
439: {1, 1, 1, 1, 1, 1, 1, 1, \
440: 0, 0, 0, 0, 0, 1, 1, 1, \
441: 1, 1, 1, 0, 0, 0, 0, 0, \
442: 0, 0, 0, 0, 0, 0, 0, 0, \
443: 1, 1, 1, 1, 1, 1}
444:
445: /* If no fp unit, make all of the fp registers fixed so that they can't
446: be used. */
447: #define CONDITIONAL_REGISTER_USAGE \
448: if (! TARGET_NUMERICS) { \
449: fixed_regs[32] = fixed_regs[33] = fixed_regs[34] = fixed_regs[35] = 1;\
450: } \
451:
452: /* Return number of consecutive hard regs needed starting at reg REGNO
453: to hold something of mode MODE.
454: This is ordinarily the length in words of a value of mode MODE
455: but can be less for certain modes in special long registers.
456:
457: On 80960, ordinary registers hold 32 bits worth, but can be ganged
458: together to hold double or extended precision floating point numbers,
459: and the floating point registers hold any size floating point number */
460: #define HARD_REGNO_NREGS(REGNO, MODE) \
461: ((REGNO) < 32 \
462: ? (((MODE) == VOIDmode) \
463: ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
464: : ((REGNO) < FIRST_PSEUDO_REGISTER) ? 1 : 0)
465:
466: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
467: On 80960, the cpu registers can hold any mode but the float registers
468: can only hold SFmode, DFmode, or TFmode. */
469: extern unsigned int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
470: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
471: ((hard_regno_mode_ok[REGNO] & (1 << (int) (MODE))) != 0)
472:
473: /* Value is 1 if it is a good idea to tie two pseudo registers
474: when one has mode MODE1 and one has mode MODE2.
475: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
476: for any hard reg, then this must be 0 for correct output. */
477:
478: #define MODES_TIEABLE_P(MODE1, MODE2) \
479: ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
480:
481: /* Specify the registers used for certain standard purposes.
482: The values of these macros are register numbers. */
483:
484: /* 80960 pc isn't overloaded on a register that the compiler knows about. */
485: /* #define PC_REGNUM */
486:
487: /* Register to use for pushing function arguments. */
488: #define STACK_POINTER_REGNUM 17
489:
490: /* Actual top-of-stack address is same as
491: the contents of the stack pointer register. */
492: #define STACK_POINTER_OFFSET (-current_function_outgoing_args_size)
493:
494: /* Base register for access to local variables of the function. */
495: #define FRAME_POINTER_REGNUM 15
496:
497: /* Value should be nonzero if functions must have frame pointers.
498: Zero means the frame pointer need not be set up (and parms
499: may be accessed via the stack pointer) in functions that seem suitable.
500: This is computed in `reload', in reload1.c. */
501: /* ??? It isn't clear to me why this is here. Perhaps because of a bug (since
502: fixed) in the definition of INITIAL_FRAME_POINTER_OFFSET which would have
503: caused this to fail. */
504: #define FRAME_POINTER_REQUIRED (! leaf_function_p ())
505:
506: /* C statement to store the difference between the frame pointer
507: and the stack pointer values immediately after the function prologue.
508:
509: Since the stack grows upward on the i960, this must be a negative number.
510: This includes the 64 byte hardware register save area and the size of
511: the frame. */
512:
513: #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
514: do { (VAR) = - (64 + compute_frame_size (get_frame_size ())); } while (0)
515:
516: /* Base register for access to arguments of the function. */
517: #define ARG_POINTER_REGNUM 14
518:
519: /* Register in which static-chain is passed to a function.
520: On i960, we use r3. */
521: #define STATIC_CHAIN_REGNUM 19
522:
523: /* Functions which return large structures get the address
524: to place the wanted value at in g13. */
525:
526: #define STRUCT_VALUE_REGNUM 13
527:
528: /* The order in which to allocate registers. */
529:
530: #define REG_ALLOC_ORDER \
531: { 4, 5, 6, 7, 0, 1, 2, 3, 13, /* g4, g5, g6, g7, g0, g1, g2, g3, g13 */ \
532: 20, 21, 22, 23, 24, 25, 26, 27,/* r4, r5, r6, r7, r8, r9, r10, r11 */ \
533: 28, 29, 30, 31, 19, 8, 9, 10, /* r12, r13, r14, r15, r3, g8, g9, g10 */ \
534: 11, 12, /* g11, g12 */ \
535: 32, 33, 34, 35, /* fp0, fp1, fp2, fp3 */ \
536: /* We can't actually allocate these. */ \
537: 16, 17, 18, 14, 15, 36, 37} /* r0, r1, r2, g14, g15, cc */
538:
539: /* Define the classes of registers for register constraints in the
540: machine description. Also define ranges of constants.
541:
542: One of the classes must always be named ALL_REGS and include all hard regs.
543: If there is more than one class, another class must be named NO_REGS
544: and contain no registers.
545:
546: The name GENERAL_REGS must be the name of a class (or an alias for
547: another name such as ALL_REGS). This is the class of registers
548: that is allowed by "g" or "r" in a register constraint.
549: Also, registers outside this class are allocated only when
550: instructions express preferences for them.
551:
552: The classes must be numbered in nondecreasing order; that is,
553: a larger-numbered class must never be contained completely
554: in a smaller-numbered class.
555:
556: For any two classes, it is very desirable that there be another
557: class that represents their union. */
558:
559: /* The 80960 has four kinds of registers, global, local, floating point,
560: and condition code. The cc register is never allocated, so no class
561: needs to be defined for it. */
562:
563: enum reg_class { NO_REGS, GLOBAL_REGS, LOCAL_REGS, LOCAL_OR_GLOBAL_REGS,
564: FP_REGS, ALL_REGS, LIM_REG_CLASSES };
565:
566: /* 'r' includes floating point registers if TARGET_NUMERICS. 'd' never
567: does. */
568: #define GENERAL_REGS ((TARGET_NUMERICS) ? ALL_REGS : LOCAL_OR_GLOBAL_REGS)
569:
570: #define N_REG_CLASSES (int) LIM_REG_CLASSES
571:
572: /* Give names of register classes as strings for dump file. */
573:
574: #define REG_CLASS_NAMES \
575: { "NO_REGS", "GLOBAL_REGS", "LOCAL_REGS", "LOCAL_OR_GLOBAL_REGS", \
576: "FP_REGS", "ALL_REGS" }
577:
578: /* Define which registers fit in which classes.
579: This is an initializer for a vector of HARD_REG_SET
580: of length N_REG_CLASSES. */
581:
582: #define REG_CLASS_CONTENTS \
583: { {0, 0}, {0x0ffff, 0}, {0xffff0000, 0}, {-1,0}, {0, -1}, {-1,-1}}
584:
585: /* The same information, inverted:
586: Return the class number of the smallest class containing
587: reg number REGNO. This could be a conditional expression
588: or could index an array. */
589:
590: #define REGNO_REG_CLASS(REGNO) \
591: ((REGNO) < 16 ? GLOBAL_REGS \
592: : (REGNO) < 32 ? LOCAL_REGS \
593: : (REGNO) < 36 ? FP_REGS \
594: : NO_REGS)
595:
596: /* The class value for index registers, and the one for base regs.
597: There is currently no difference between base and index registers on the
598: i960, but this distinction may one day be useful. */
599: #define INDEX_REG_CLASS LOCAL_OR_GLOBAL_REGS
600: #define BASE_REG_CLASS LOCAL_OR_GLOBAL_REGS
601:
602: /* Get reg_class from a letter such as appears in the machine description.
603: 'f' is a floating point register (fp0..fp3)
604: 'l' is a local register (r0-r15)
605: 'b' is a global register (g0-g15)
606: 'd' is any local or global register
607: 'r' or 'g' are pre-defined to the class GENERAL_REGS. */
608: /* 'l' and 'b' are probably never used. Note that 'd' and 'r' are *not*
609: the same thing, since 'r' may include the fp registers. */
610: #define REG_CLASS_FROM_LETTER(C) \
611: (((C) == 'f') && (TARGET_NUMERICS) ? FP_REGS : ((C) == 'l' ? LOCAL_REGS : \
612: (C) == 'b' ? GLOBAL_REGS : ((C) == 'd' ? LOCAL_OR_GLOBAL_REGS : NO_REGS)))
613:
614: /* The letters I, J, K, L and M in a register constraint string
615: can be used to stand for particular ranges of immediate operands.
616: This macro defines what the ranges are.
617: C is the letter, and VALUE is a constant value.
618: Return 1 if VALUE is in the range specified by C.
619:
620: For 80960:
621: 'I' is used for literal values 0..31
622: 'J' means literal 0
623: 'K' means 0..-31. */
624:
625: #define CONST_OK_FOR_LETTER_P(VALUE, C) \
626: ((C) == 'I' ? (((unsigned) (VALUE)) <= 31) \
627: : (C) == 'J' ? ((VALUE) == 0) \
628: : (C) == 'K' ? ((VALUE) > -32 && (VALUE) <= 0) \
629: : 0)
630:
631: /* Similar, but for floating constants, and defining letters G and H.
632: Here VALUE is the CONST_DOUBLE rtx itself.
633: For the 80960, G is 0.0 and H is 1.0. */
634:
635: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
636: ((TARGET_NUMERICS) && \
637: (((C) == 'G' && ((VALUE) == CONST0_RTX (DFmode) \
638: || (VALUE) == CONST0_RTX (SFmode))) \
639: || ((C) == 'H' && ((VALUE) == CONST1_RTX (DFmode) \
640: || (VALUE) == CONST1_RTX (SFmode)))))
641:
642: /* Given an rtx X being reloaded into a reg required to be
643: in class CLASS, return the class of reg to actually use.
644: In general this is just CLASS; but on some machines
645: in some cases it is preferable to use a more restrictive class. */
646:
647: /* On 960, can't load constant into floating-point reg except
648: 0.0 or 1.0.
649:
650: Any hard reg is ok as a src operand of a reload insn. */
651:
652: #define PREFERRED_RELOAD_CLASS(X,CLASS) \
653: (GET_CODE (X) == REG && REGNO (X) < FIRST_PSEUDO_REGISTER \
654: ? (CLASS) \
655: : ((CLASS) == FP_REGS && CONSTANT_P (X) \
656: && (X) != CONST0_RTX (DFmode) && (X) != CONST1_RTX (DFmode)\
657: && (X) != CONST0_RTX (SFmode) && (X) != CONST1_RTX (SFmode)\
658: ? NO_REGS \
659: : (CLASS) == ALL_REGS ? LOCAL_OR_GLOBAL_REGS : (CLASS)))
660:
661: #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
662: secondary_reload_class (CLASS, MODE, IN)
663:
664: /* Return the maximum number of consecutive registers
665: needed to represent mode MODE in a register of class CLASS. */
666: /* On 80960, this is the size of MODE in words,
667: except in the FP regs, where a single reg is always enough. */
668: #define CLASS_MAX_NREGS(CLASS, MODE) \
669: ((CLASS) == FP_REGS ? 1 : HARD_REGNO_NREGS (0, (MODE)))
670:
671: /* Stack layout; function entry, exit and calling. */
672:
673: /* Define this if pushing a word on the stack
674: makes the stack pointer a smaller address. */
675: /* #define STACK_GROWS_DOWNWARD */
676:
677: /* Define this if the nominal address of the stack frame
678: is at the high-address end of the local variables;
679: that is, each additional local variable allocated
680: goes at a more negative offset in the frame. */
681: /* #define FRAME_GROWS_DOWNWARD */
682:
683: /* Offset within stack frame to start allocating local variables at.
684: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
685: first local allocated. Otherwise, it is the offset to the BEGINNING
686: of the first local allocated.
687:
688: The i960 has a 64 byte register save area, plus possibly some extra
689: bytes allocated for varargs functions. */
690: #define STARTING_FRAME_OFFSET 64
691:
692: /* If we generate an insn to push BYTES bytes,
693: this says how many the stack pointer really advances by.
694: On 80960, don't define this because there are no push insns. */
695: /* #define PUSH_ROUNDING(BYTES) BYTES */
696:
697: /* Offset of first parameter from the argument pointer register value. */
698: #define FIRST_PARM_OFFSET(FNDECL) 0
699:
700: /* When a parameter is passed in a register, no stack space is
701: allocated for it. However, when args are passed in the
702: stack, space is allocated for every register parameter. */
703: #define MAYBE_REG_PARM_STACK_SPACE 48
704: #define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE) \
705: i960_final_reg_parm_stack_space (CONST_SIZE, VAR_SIZE);
706: #define REG_PARM_STACK_SPACE(DECL) i960_reg_parm_stack_space (DECL)
707: #define OUTGOING_REG_PARM_STACK_SPACE
708:
709: /* Keep the stack pointer constant throughout the function. */
710: #define ACCUMULATE_OUTGOING_ARGS
711:
712: /* Value is 1 if returning from a function call automatically
713: pops the arguments described by the number-of-args field in the call.
714: FUNTYPE is the data type of the function (as a tree),
715: or for a library call it is an identifier node for the subroutine name. */
716:
717: #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
718:
719: /* Define how to find the value returned by a library function
720: assuming the value has mode MODE. */
721:
722: #define LIBCALL_VALUE(MODE) gen_rtx ((REG), (MODE), 0)
723:
724: /* 1 if N is a possible register number for a function value
725: as seen by the caller.
726: On 80960, returns are in g0..g3 */
727:
728: #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
729:
730: /* 1 if N is a possible register number for function argument passing.
731: On 80960, parameters are passed in g0..g11 */
732:
733: #define FUNCTION_ARG_REGNO_P(N) ((N) < 12)
734:
735: /* Perform any needed actions needed for a function that is receiving a
736: variable number of arguments.
737:
738: CUM is as above.
739:
740: MODE and TYPE are the mode and type of the current parameter.
741:
742: PRETEND_SIZE is a variable that should be set to the amount of stack
743: that must be pushed by the prolog to pretend that our caller pushed
744: it.
745:
746: Normally, this macro will push all remaining incoming registers on the
747: stack and set PRETEND_SIZE to the length of the registers pushed. */
748:
749: #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
750: i960_setup_incoming_varargs(&CUM,MODE,TYPE,&PRETEND_SIZE,NO_RTL)
751:
752: /* Define a data type for recording info about an argument list
753: during the scan of that argument list. This data type should
754: hold all necessary information about the function itself
755: and about the args processed so far, enough to enable macros
756: such as FUNCTION_ARG to determine where the next arg should go.
757:
758: On 80960, this is two integers, which count the number of register
759: parameters and the number of stack parameters seen so far. */
760:
761: struct cum_args { int ca_nregparms; int ca_nstackparms; };
762:
763: #define CUMULATIVE_ARGS struct cum_args
764:
765: /* Define the number of registers that can hold parameters.
766: This macro is used only in macro definitions below and/or i960.c. */
767: #define NPARM_REGS 12
768:
769: /* Define how to round to the next parameter boundary.
770: This macro is used only in macro definitions below and/or i960.c. */
771: #define ROUND_PARM(X, MULTIPLE_OF) \
772: ((((X) + (MULTIPLE_OF) - 1) / (MULTIPLE_OF)) * MULTIPLE_OF)
773:
774: /* Initialize a variable CUM of type CUMULATIVE_ARGS
775: for a call to a function whose data type is FNTYPE.
776: For a library call, FNTYPE is 0.
777:
778: On 80960, the offset always starts at 0; the first parm reg is g0. */
779:
780: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
781: ((CUM).ca_nregparms = 0, (CUM).ca_nstackparms = 0)
782:
783: /* Update the data in CUM to advance over an argument
784: of mode MODE and data type TYPE.
785: CUM should be advanced to align with the data type accessed and
786: also the size of that data type in # of regs.
787: (TYPE is null for libcalls where that information may not be available.) */
788:
789: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
790: i960_function_arg_advance(&CUM, MODE, TYPE, NAMED)
791:
792: /* Indicate the alignment boundary for an argument of the specified mode and
793: type. */
794: #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
795: (((TYPE) != 0) \
796: ? ((TYPE_ALIGN (TYPE) <= PARM_BOUNDARY) \
797: ? PARM_BOUNDARY \
798: : TYPE_ALIGN (TYPE)) \
799: : ((GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY) \
800: ? PARM_BOUNDARY \
801: : GET_MODE_ALIGNMENT (MODE)))
802:
803: /* Determine where to put an argument to a function.
804: Value is zero to push the argument on the stack,
805: or a hard register in which to store the argument.
806:
807: MODE is the argument's machine mode.
808: TYPE is the data type of the argument (as a tree).
809: This is null for libcalls where that information may
810: not be available.
811: CUM is a variable of type CUMULATIVE_ARGS which gives info about
812: the preceding args and about the function being called.
813: NAMED is nonzero if this argument is a named parameter
814: (otherwise it is an extra parameter matching an ellipsis). */
815:
816: extern struct rtx_def *i960_function_arg ();
817: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
818: i960_function_arg(&CUM, MODE, TYPE, NAMED)
819:
820: /* Define how to find the value returned by a function.
821: VALTYPE is the data type of the value (as a tree).
822: If the precise function being called is known, FUNC is its FUNCTION_DECL;
823: otherwise, FUNC is 0. */
824:
825: #define FUNCTION_VALUE(TYPE, FUNC) \
826: gen_rtx (REG, TYPE_MODE (TYPE), 0)
827:
828: /* Force aggregates and objects larger than 16 bytes to be returned in memory,
829: since we only have 4 registers available for return values. */
830:
831: #define RETURN_IN_MEMORY(TYPE) \
832: (TYPE_MODE (TYPE) == BLKmode || int_size_in_bytes (TYPE) > 16)
833:
834: /* Don't default to pcc-struct-return, because we have already specified
835: exactly how to return structures in the RETURN_IN_MEMORY macro. */
836: #define DEFAULT_PCC_STRUCT_RETURN 0
837:
838: /* For an arg passed partly in registers and partly in memory,
839: this is the number of registers used.
840: This never happens on 80960. */
841:
842: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
843:
844: /* Output the label for a function definition.
845: This handles leaf functions and a few other things for the i960. */
846:
847: #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
848: i960_function_name_declare (FILE, NAME, DECL)
849:
850: /* This macro generates the assembly code for function entry.
851: FILE is a stdio stream to output the code to.
852: SIZE is an int: how many units of temporary storage to allocate.
853: Refer to the array `regs_ever_live' to determine which registers
854: to save; `regs_ever_live[I]' is nonzero if register number I
855: is ever used in the function. This macro is responsible for
856: knowing which registers should not be saved even if used. */
857:
858: #define FUNCTION_PROLOGUE(FILE, SIZE) i960_function_prologue ((FILE), (SIZE))
859:
860: /* Output assembler code to FILE to increment profiler label # LABELNO
861: for profiling a function entry. */
862:
863: #define FUNCTION_PROFILER(FILE, LABELNO) \
864: output_function_profiler ((FILE), (LABELNO));
865:
866: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
867: the stack pointer does not matter. The value is tested only in
868: functions that have frame pointers.
869: No definition is equivalent to always zero. */
870:
871: #define EXIT_IGNORE_STACK 1
872:
873: /* This macro generates the assembly code for function exit,
874: on machines that need it. If FUNCTION_EPILOGUE is not defined
875: then individual return instructions are generated for each
876: return statement. Args are same as for FUNCTION_PROLOGUE.
877:
878: The function epilogue should not depend on the current stack pointer!
879: It should use the frame pointer only. This is mandatory because
880: of alloca; we also take advantage of it to omit stack adjustments
881: before returning. */
882:
883: #define FUNCTION_EPILOGUE(FILE, SIZE) i960_function_epilogue (FILE, SIZE)
884:
885: /* Addressing modes, and classification of registers for them. */
886:
887: /* #define HAVE_POST_INCREMENT */
888: /* #define HAVE_POST_DECREMENT */
889:
890: /* #define HAVE_PRE_DECREMENT */
891: /* #define HAVE_PRE_INCREMENT */
892:
893: /* Macros to check register numbers against specific register classes. */
894:
895: /* These assume that REGNO is a hard or pseudo reg number.
896: They give nonzero only if REGNO is a hard reg of the suitable class
897: or a pseudo reg currently allocated to a suitable hard reg.
898: Since they use reg_renumber, they are safe only once reg_renumber
899: has been allocated, which happens in local-alloc.c. */
900:
901: #define REGNO_OK_FOR_INDEX_P(REGNO) \
902: ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
903: #define REGNO_OK_FOR_BASE_P(REGNO) \
904: ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
905: #define REGNO_OK_FOR_FP_P(REGNO) \
906: ((REGNO) < 36 || (unsigned) reg_renumber[REGNO] < 36)
907:
908: /* Now macros that check whether X is a register and also,
909: strictly, whether it is in a specified class.
910:
911: These macros are specific to the 960, and may be used only
912: in code for printing assembler insns and in conditions for
913: define_optimization. */
914:
915: /* 1 if X is an fp register. */
916:
917: #define FP_REG_P(X) (REGNO (X) >= 32 && REGNO (X) < 36)
918:
919: /* Maximum number of registers that can appear in a valid memory address. */
920: #define MAX_REGS_PER_ADDRESS 2
921:
922: #define CONSTANT_ADDRESS_P(X) \
923: (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
924: || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
925: || GET_CODE (X) == HIGH)
926:
927: /* LEGITIMATE_CONSTANT_P is nonzero if the constant value X
928: is a legitimate general operand.
929: It is given that X satisfies CONSTANT_P.
930:
931: Anything but a CONST_DOUBLE can be made to work, excepting 0.0 and 1.0. */
932:
933: #define LEGITIMATE_CONSTANT_P(X) \
934: ((GET_CODE (X) != CONST_DOUBLE) || fp_literal ((X), VOIDmode))
935:
936: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
937: and check its validity for a certain class.
938: We have two alternate definitions for each of them.
939: The usual definition accepts all pseudo regs; the other rejects
940: them unless they have been allocated suitable hard regs.
941: The symbol REG_OK_STRICT causes the latter definition to be used.
942:
943: Most source files want to accept pseudo regs in the hope that
944: they will get allocated to the class that the insn wants them to be in.
945: Source files for reload pass need to be strict.
946: After reload, it makes no difference, since pseudo regs have
947: been eliminated by then. */
948:
949: #ifndef REG_OK_STRICT
950:
951: /* Nonzero if X is a hard reg that can be used as an index
952: or if it is a pseudo reg. */
953: #define REG_OK_FOR_INDEX_P(X) \
954: (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
955: /* Nonzero if X is a hard reg that can be used as a base reg
956: or if it is a pseudo reg. */
957: #define REG_OK_FOR_BASE_P(X) \
958: (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
959:
960: #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
961: #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X))
962:
963: #else
964:
965: /* Nonzero if X is a hard reg that can be used as an index. */
966: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
967: /* Nonzero if X is a hard reg that can be used as a base reg. */
968: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
969:
970: #endif
971:
972: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
973: that is a valid memory address for an instruction.
974: The MODE argument is the machine mode for the MEM expression
975: that wants to use this address.
976:
977: On 80960, legitimate addresses are:
978: base ld (g0),r0
979: disp (12 or 32 bit) ld foo,r0
980: base + index ld (g0)[g1*1],r0
981: base + displ ld 0xf00(g0),r0
982: base + index*scale + displ ld 0xf00(g0)[g1*4],r0
983: index*scale + base ld (g0)[g1*4],r0
984: index*scale + displ ld 0xf00[g1*4],r0
985: index*scale ld [g1*4],r0
986: index + base + displ ld 0xf00(g0)[g1*1],r0
987:
988: In each case, scale can be 1, 2, 4, 8, or 16. */
989:
990: /* Returns 1 if the scale factor of an index term is valid. */
991: #define SCALE_TERM_P(X) \
992: (GET_CODE (X) == CONST_INT \
993: && (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 \
994: || INTVAL(X) == 8 || INTVAL (X) == 16))
995:
996:
997: #ifdef REG_OK_STRICT
998: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
999: { if (legitimate_address_p (MODE, X, 1)) goto ADDR; }
1000: #else
1001: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1002: { if (legitimate_address_p (MODE, X, 0)) goto ADDR; }
1003: #endif
1004:
1005: /* Try machine-dependent ways of modifying an illegitimate address
1006: to be legitimate. If we find one, return the new, valid address.
1007: This macro is used in only one place: `memory_address' in explow.c.
1008:
1009: OLDX is the address as it was before break_out_memory_refs was called.
1010: In some cases it is useful to look at this to decide what needs to be done.
1011:
1012: MODE and WIN are passed so that this macro can use
1013: GO_IF_LEGITIMATE_ADDRESS.
1014:
1015: It is always safe for this macro to do nothing. It exists to recognize
1016: opportunities to optimize the output. */
1017:
1018: /* On 80960, convert non-canonical addresses to canonical form. */
1019:
1020: extern struct rtx_def *legitimize_address ();
1021: #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1022: { rtx orig_x = (X); \
1023: (X) = legitimize_address (X, OLDX, MODE); \
1024: if ((X) != orig_x && memory_address_p (MODE, X)) \
1025: goto WIN; }
1026:
1027: /* Go to LABEL if ADDR (a legitimate address expression)
1028: has an effect that depends on the machine mode it is used for.
1029: On the 960 this is never true. */
1030:
1031: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1032:
1033: /* Specify the machine mode that this machine uses
1034: for the index in the tablejump instruction. */
1035: #define CASE_VECTOR_MODE SImode
1036:
1037: /* Define this if the tablejump instruction expects the table
1038: to contain offsets from the address of the table.
1039: Do not define this if the table should contain absolute addresses. */
1040: /* #define CASE_VECTOR_PC_RELATIVE */
1041:
1042: /* Specify the tree operation to be used to convert reals to integers. */
1043: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1044:
1045: /* This is the kind of divide that is easiest to do in the general case. */
1046: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1047:
1048: /* Define this as 1 if `char' should by default be signed; else as 0. */
1049: #define DEFAULT_SIGNED_CHAR 0
1050:
1051: /* Allow and ignore #sccs directives. */
1052: #define SCCS_DIRECTIVE
1053:
1054: /* Max number of bytes we can move from memory to memory
1055: in one reasonably fast instruction. */
1056: #define MOVE_MAX 16
1057:
1058: /* Define if operations between registers always perform the operation
1059: on the full register even if a narrower mode is specified. */
1060: #define WORD_REGISTER_OPERATIONS
1061:
1062: /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1063: will either zero-extend or sign-extend. The value of this macro should
1064: be the code that says which one of the two operations is implicitly
1065: done, NIL if none. */
1066: #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1067:
1068: /* Nonzero if access to memory by bytes is no faster than for words.
1069: Defining this results in worse code on the i960. */
1070:
1071: #define SLOW_BYTE_ACCESS 0
1072:
1073: /* We assume that the store-condition-codes instructions store 0 for false
1074: and some other value for true. This is the value stored for true. */
1075:
1076: #define STORE_FLAG_VALUE 1
1077:
1078: /* Define this to be nonzero if shift instructions ignore all but the low-order
1079: few bits. */
1080: #define SHIFT_COUNT_TRUNCATED 1
1081:
1082: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1083: is done just by pretending it is already truncated. */
1084: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1085:
1086: /* Specify the machine mode that pointers have.
1087: After generation of rtl, the compiler makes no further distinction
1088: between pointers and any other objects of this machine mode. */
1089: #define Pmode SImode
1090:
1091: /* Specify the widest mode that BLKmode objects can be promoted to */
1092: #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1093:
1094: /* These global variables are used to pass information between
1095: cc setter and cc user at insn emit time. */
1096:
1097: extern struct rtx_def *i960_compare_op0, *i960_compare_op1;
1098:
1099: /* Define the function that build the compare insn for scc and bcc. */
1100:
1101: extern struct rtx_def *gen_compare_reg ();
1102:
1103: /* Add any extra modes needed to represent the condition code.
1104:
1105: Also, signed and unsigned comparisons are distinguished, as
1106: are operations which are compatible with chkbit insns. */
1107: #define EXTRA_CC_MODES CC_UNSmode, CC_CHKmode
1108:
1109: /* Define the names for the modes specified above. */
1110: #define EXTRA_CC_NAMES "CC_UNS", "CC_CHK"
1111:
1112: /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1113: return the mode to be used for the comparison. For floating-point, CCFPmode
1114: should be used. CC_NOOVmode should be used when the first operand is a
1115: PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1116: needed. */
1117: #define SELECT_CC_MODE(OP,X,Y) select_cc_mode (OP, X)
1118:
1119: /* A function address in a call instruction is a byte address
1120: (for indexing purposes) so give the MEM rtx a byte's mode. */
1121: #define FUNCTION_MODE SImode
1122:
1123: /* Define this if addresses of constant functions
1124: shouldn't be put through pseudo regs where they can be cse'd.
1125: Desirable on machines where ordinary constants are expensive
1126: but a CALL with constant address is cheap. */
1127: #define NO_FUNCTION_CSE
1128:
1129: /* Use memcpy, etc. instead of bcopy. */
1130:
1131: #ifndef WIND_RIVER
1132: #define TARGET_MEM_FUNCTIONS 1
1133: #endif
1134:
1135: /* Compute the cost of computing a constant rtl expression RTX
1136: whose rtx-code is CODE. The body of this macro is a portion
1137: of a switch statement. If the code is computed here,
1138: return it with a return statement. Otherwise, break from the switch. */
1139:
1140: /* Constants that can be (non-ldconst) insn operands are cost 0. Constants
1141: that can be non-ldconst operands in rare cases are cost 1. Other constants
1142: have higher costs. */
1143:
1144: #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1145: case CONST_INT: \
1146: if ((INTVAL (RTX) >= 0 && INTVAL (RTX) < 32) \
1147: || power2_operand (RTX, VOIDmode)) \
1148: return 0; \
1149: else if (INTVAL (RTX) >= -31 && INTVAL (RTX) < 0) \
1150: return 1; \
1151: case CONST: \
1152: case LABEL_REF: \
1153: case SYMBOL_REF: \
1154: return (TARGET_FLAG_C_SERIES ? 6 : 8); \
1155: case CONST_DOUBLE: \
1156: if ((RTX) == CONST0_RTX (DFmode) || (RTX) == CONST0_RTX (SFmode) \
1157: || (RTX) == CONST1_RTX (DFmode) || (RTX) == CONST1_RTX (SFmode))\
1158: return 1; \
1159: return 12;
1160:
1161: /* The i960 offers addressing modes which are "as cheap as a register".
1162: See i960.c (or gcc.texinfo) for details. */
1163:
1164: #define ADDRESS_COST(RTX) \
1165: (GET_CODE (RTX) == REG ? 1 : i960_address_cost (RTX))
1166:
1167: /* Control the assembler format that we output. */
1168:
1169: /* Output at beginning of assembler file. */
1170:
1171: #define ASM_FILE_START(file)
1172:
1173: /* Output to assembler file text saying following lines
1174: may contain character constants, extra white space, comments, etc. */
1175:
1176: #define ASM_APP_ON ""
1177:
1178: /* Output to assembler file text saying following lines
1179: no longer contain unusual constructs. */
1180:
1181: #define ASM_APP_OFF ""
1182:
1183: /* Output before read-only data. */
1184:
1185: #define TEXT_SECTION_ASM_OP ".text"
1186:
1187: /* Output before writable data. */
1188:
1189: #define DATA_SECTION_ASM_OP ".data"
1190:
1191: /* How to refer to registers in assembler output.
1192: This sequence is indexed by compiler's hard-register-number (see above). */
1193:
1194: #define REGISTER_NAMES { \
1195: "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \
1196: "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", \
1197: "pfp","sp", "rip", "r3", "r4", "r5", "r6", "r7", \
1198: "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1199: "fp0","fp1","fp2", "fp3", "cc", "fake" }
1200:
1201: /* How to renumber registers for dbx and gdb.
1202: In the 960 encoding, g0..g15 are registers 16..31. */
1203:
1204: #define DBX_REGISTER_NUMBER(REGNO) \
1205: (((REGNO) < 16) ? (REGNO) + 16 \
1206: : (((REGNO) > 31) ? (REGNO) : (REGNO) - 16))
1207:
1208: /* Don't emit dbx records longer than this. This is an arbitrary value. */
1209: #define DBX_CONTIN_LENGTH 1500
1210:
1211: /* This is how to output a note to DBX telling it the line number
1212: to which the following sequence of instructions corresponds. */
1213:
1214: #define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \
1215: { if (write_symbols == SDB_DEBUG) { \
1216: fprintf ((FILE), "\t.ln %d\n", \
1217: (sdb_begin_function_line \
1218: ? (LINE) - sdb_begin_function_line : 1)); \
1219: } else if (write_symbols == DBX_DEBUG) { \
1220: fprintf((FILE),"\t.stabd 68,0,%d\n",(LINE)); \
1221: } }
1222:
1223: /* This is how to output the definition of a user-level label named NAME,
1224: such as the label on a static function or variable NAME. */
1225:
1226: #define ASM_OUTPUT_LABEL(FILE,NAME) \
1227: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1228:
1229: /* This is how to output a command to make the user-level label named NAME
1230: defined for reference from other files. */
1231:
1232: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1233: { fputs ("\t.globl ", FILE); \
1234: assemble_name (FILE, NAME); \
1235: fputs ("\n", FILE); }
1236:
1237: /* This is how to output a reference to a user-level label named NAME.
1238: `assemble_name' uses this. */
1239:
1240: #define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "_%s", NAME)
1241:
1242: /* This is how to output an internal numbered label where
1243: PREFIX is the class of label and NUM is the number within the class. */
1244:
1245: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1246: fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1247:
1248: /* This is how to store into the string LABEL
1249: the symbol_ref name of an internal numbered label where
1250: PREFIX is the class of label and NUM is the number within the class.
1251: This is suitable for output with `assemble_name'. */
1252:
1253: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1254: sprintf (LABEL, "*%s%d", PREFIX, NUM)
1255:
1256: /* This is how to output an assembler line defining a `double' constant. */
1257:
1258: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) i960_output_double(FILE, VALUE)
1259:
1260: /* This is how to output an assembler line defining a `float' constant. */
1261:
1262: #define ASM_OUTPUT_FLOAT(FILE,VALUE) i960_output_float(FILE, VALUE)
1263:
1264: /* This is how to output an assembler line defining an `int' constant. */
1265:
1266: #define ASM_OUTPUT_INT(FILE,VALUE) \
1267: ( fprintf (FILE, "\t.word "), \
1268: output_addr_const (FILE, (VALUE)), \
1269: fprintf (FILE, "\n"))
1270:
1271: /* Likewise for `char' and `short' constants. */
1272:
1273: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1274: ( fprintf (FILE, "\t.short "), \
1275: output_addr_const (FILE, (VALUE)), \
1276: fprintf (FILE, "\n"))
1277:
1278: #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1279: ( fprintf (FILE, "\t.byte "), \
1280: output_addr_const (FILE, (VALUE)), \
1281: fprintf (FILE, "\n"))
1282:
1283: /* This is how to output an assembler line for a numeric constant byte. */
1284:
1285: #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1286: fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1287:
1288: #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1289: fprintf (FILE, "\tst\t%s,(sp)\n\taddo\t4,sp,sp\n", reg_names[REGNO])
1290:
1291: /* This is how to output an insn to pop a register from the stack.
1292: It need not be very fast code. */
1293:
1294: #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1295: fprintf (FILE, "\tsubo\t4,sp,sp\n\tld\t(sp),%s\n", reg_names[REGNO])
1296:
1297: /* This is how to output an element of a case-vector that is absolute. */
1298:
1299: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1300: fprintf (FILE, "\t.word L%d\n", VALUE)
1301:
1302: /* This is how to output an element of a case-vector that is relative. */
1303:
1304: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1305: fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
1306:
1307: /* This is how to output an assembler line that says to advance the
1308: location counter to a multiple of 2**LOG bytes. */
1309:
1310: #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1311: fprintf (FILE, "\t.align %d\n", (LOG))
1312:
1313: #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1314: fprintf (FILE, "\t.space %d\n", (SIZE))
1315:
1316: /* This says how to output an assembler line
1317: to define a global common symbol. */
1318:
1319: /* For common objects, output unpadded size... gld960 & lnk960 both
1320: have code to align each common object at link time. Also, if size
1321: is 0, treat this as a declaration, not a definition - i.e.,
1322: do nothing at all. */
1323:
1324: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1325: { if ((SIZE) != 0) \
1326: { \
1327: fputs (".globl ", (FILE)), \
1328: assemble_name ((FILE), (NAME)), \
1329: fputs ("\n.comm ", (FILE)), \
1330: assemble_name ((FILE), (NAME)), \
1331: fprintf ((FILE), ",%d\n", (SIZE)); \
1332: } \
1333: }
1334:
1335: /* This says how to output an assembler line to define a local common symbol.
1336: Output unpadded size, with request to linker to align as requested.
1337: 0 size should not be possible here. */
1338:
1339: #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1340: ( fputs (".bss\t", (FILE)), \
1341: assemble_name ((FILE), (NAME)), \
1342: fprintf ((FILE), ",%d,%d\n", (SIZE), \
1343: ((ALIGN) <= 8 ? 0 \
1344: : ((ALIGN) <= 16 ? 1 \
1345: : ((ALIGN) <= 32 ? 2 \
1346: : ((ALIGN <= 64 ? 3 : 4)))))))
1347:
1348: /* Output text for an #ident directive. */
1349: #define ASM_OUTPUT_IDENT(FILE, STR) fprintf(FILE, "\t# %s\n", STR);
1350:
1351: /* Align code to 8 byte boundary if TARGET_CODE_ALIGN is true. */
1352:
1353: #define ASM_OUTPUT_ALIGN_CODE(FILE) \
1354: { if (TARGET_CODE_ALIGN) fputs("\t.align 3\n",FILE); }
1355:
1356: /* Store in OUTPUT a string (made with alloca) containing
1357: an assembler-name for a local static variable named NAME.
1358: LABELNO is an integer which is different for each call. */
1359:
1360: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1361: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1362: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1363:
1364: /* Define the parentheses used to group arithmetic operations
1365: in assembler code. */
1366:
1367: #define ASM_OPEN_PAREN "("
1368: #define ASM_CLOSE_PAREN ")"
1369:
1370: /* Define results of standard character escape sequences. */
1371: #define TARGET_BELL 007
1372: #define TARGET_BS 010
1373: #define TARGET_TAB 011
1374: #define TARGET_NEWLINE 012
1375: #define TARGET_VT 013
1376: #define TARGET_FF 014
1377: #define TARGET_CR 015
1378:
1379: /* Output assembler code to FILE to initialize this source file's
1380: basic block profiling info, if that has not already been done. */
1381:
1382: #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1383: { fprintf (FILE, "\tld LPBX0,g12\n"); \
1384: fprintf (FILE, "\tcmpobne 0,g12,LPY%d\n",LABELNO);\
1385: fprintf (FILE, "\tlda LPBX0,g12\n"); \
1386: fprintf (FILE, "\tcall ___bb_init_func\n"); \
1387: fprintf (FILE, "LPY%d:\n",LABELNO); }
1388:
1389: /* Output assembler code to FILE to increment the entry-count for
1390: the BLOCKNO'th basic block in this source file. */
1391:
1392: #define BLOCK_PROFILER(FILE, BLOCKNO) \
1393: { int blockn = (BLOCKNO); \
1394: fprintf (FILE, "\tld LPBX2+%d,g12\n", 4 * blockn); \
1395: fprintf (FILE, "\taddo g12,1,g12\n"); \
1396: fprintf (FILE, "\tst g12,LPBX2+%d\n", 4 * blockn); }
1397:
1398: /* Print operand X (an rtx) in assembler syntax to file FILE.
1399: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1400: For `%' followed by punctuation, CODE is the punctuation and X is null. */
1401:
1402: #define PRINT_OPERAND(FILE, X, CODE) \
1403: i960_print_operand (FILE, X, CODE);
1404:
1405: /* Print a memory address as an operand to reference that memory location. */
1406:
1407: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1408: i960_print_operand_addr (FILE, ADDR)
1409:
1410: /* Output assembler code for a block containing the constant parts
1411: of a trampoline, leaving space for the variable parts. */
1412:
1413: /* On the i960, the trampoline contains three instructions:
1414: ldconst _function, r4
1415: ldconst static addr, r3
1416: jump (r4) */
1417:
1418: #define TRAMPOLINE_TEMPLATE(FILE) \
1419: { \
1420: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C203000)); \
1421: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1422: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C183000)); \
1423: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1424: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x84212000)); \
1425: }
1426:
1427: /* Length in units of the trampoline for entering a nested function. */
1428:
1429: #define TRAMPOLINE_SIZE 20
1430:
1431: /* Emit RTL insns to initialize the variable parts of a trampoline.
1432: FNADDR is an RTX for the address of the function's pure code.
1433: CXT is an RTX for the static chain value for the function. */
1434:
1435: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1436: { \
1437: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), \
1438: FNADDR); \
1439: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)), \
1440: CXT); \
1441: }
1442:
1443: #if 0
1444: /* Promote char and short arguments to ints, when want compatibility with
1445: the iC960 compilers. */
1446:
1447: /* ??? In order for this to work, all users would need to be changed
1448: to test the value of the macro at run time. */
1449: #define PROMOTE_PROTOTYPES TARGET_CLEAN_LINKAGE
1450: /* ??? This does not exist. */
1451: #define PROMOTE_RETURN TARGET_CLEAN_LINKAGE
1452: #endif
1453:
1454: /* Instruction type definitions. Used to alternate instructions types for
1455: better performance on the C series chips. */
1456:
1457: enum insn_types { I_TYPE_REG, I_TYPE_MEM, I_TYPE_CTRL };
1458:
1459: /* Holds the insn type of the last insn output to the assembly file. */
1460:
1461: extern enum insn_types i960_last_insn_type;
1462:
1463: /* Parse opcodes, and set the insn last insn type based on them. */
1464:
1465: #define ASM_OUTPUT_OPCODE(FILE, INSN) i960_scan_opcode (INSN)
1466:
1467: /* Table listing what rtl codes each predicate in i960.c will accept. */
1468:
1469: #define PREDICATE_CODES \
1470: {"fpmove_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
1471: LABEL_REF, SUBREG, REG, MEM}}, \
1472: {"arith_operand", {SUBREG, REG, CONST_INT}}, \
1473: {"fp_arith_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1474: {"signed_arith_operand", {SUBREG, REG, CONST_INT}}, \
1475: {"literal", {CONST_INT}}, \
1476: {"fp_literal_one", {CONST_DOUBLE}}, \
1477: {"fp_literal_double", {CONST_DOUBLE}}, \
1478: {"fp_literal", {CONST_DOUBLE}}, \
1479: {"signed_literal", {CONST_INT}}, \
1480: {"symbolic_memory_operand", {SUBREG, MEM}}, \
1481: {"eq_or_neq", {EQ, NE}}, \
1482: {"arith32_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST_INT, \
1483: CONST_DOUBLE, CONST}}, \
1484: {"power2_operand", {CONST_INT}}, \
1485: {"cmplpower2_operand", {CONST_INT}},
1486:
1487: /* Define functions in i960.c and used in insn-output.c. */
1488:
1489: extern char *i960_output_ldconst ();
1490: extern char *i960_output_call_insn ();
1491: extern char *i960_output_ret_insn ();
1492:
1493: /* Defined in reload.c, and used in insn-recog.c. */
1494:
1495: extern int rtx_equal_function_value_matters;
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