![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to ns32k.md CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Apple XNU] / GNUtools / cc / config / ns32k|
Return to ns32k.md CVS log | Up to [Apple XNU] / GNUtools / cc / config / ns32k |
1.1 root 1: ; BUGS:
2: ;; Insert no-op between an insn with memory read-write operands
3: ;; following by a scale-indexing operation.
4: ;; The Sequent assembler does not allow addresses to be used
5: ;; except in insns which explicitly compute an effective address.
6: ;; I.e., one cannot say "cmpd _p,@_x"
7: ;; Implement unsigned multiplication??
8:
9: ;;- Machine description for GNU compiler
10: ;;- ns32000 Version
11: ;; Copyright (C) 1988 Free Software Foundation, Inc.
12: ;; Contributed by Michael Tiemann ([email protected])
13:
14: ;; This file is part of GNU CC.
15:
16: ;; GNU CC is free software; you can redistribute it and/or modify
17: ;; it under the terms of the GNU General Public License as published by
18: ;; the Free Software Foundation; either version 2, or (at your option)
19: ;; any later version.
20:
21: ;; GNU CC is distributed in the hope that it will be useful,
22: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
23: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24: ;; GNU General Public License for more details.
25:
26: ;; You should have received a copy of the GNU General Public License
27: ;; along with GNU CC; see the file COPYING. If not, write to
28: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
29:
30:
31: ;;- Instruction patterns. When multiple patterns apply,
32: ;;- the first one in the file is chosen.
33: ;;-
34: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
35: ;;-
36: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
37: ;;- updates for most instructions.
38:
39: ;; We don't want to allow a constant operand for test insns because
40: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
41: ;; be folded while optimizing anyway.
42:
43: (define_insn "tstsi"
44: [(set (cc0)
45: (match_operand:SI 0 "nonimmediate_operand" "rm"))]
46: ""
47: "*
48: { cc_status.flags |= CC_REVERSED;
49: operands[1] = const0_rtx;
50: return \"cmpqd %1,%0\"; }")
51:
52: (define_insn "tsthi"
53: [(set (cc0)
54: (match_operand:HI 0 "nonimmediate_operand" "g"))]
55: ""
56: "*
57: { cc_status.flags |= CC_REVERSED;
58: operands[1] = const0_rtx;
59: return \"cmpqw %1,%0\"; }")
60:
61: (define_insn "tstqi"
62: [(set (cc0)
63: (match_operand:QI 0 "nonimmediate_operand" "g"))]
64: ""
65: "*
66: { cc_status.flags |= CC_REVERSED;
67: operands[1] = const0_rtx;
68: return \"cmpqb %1,%0\"; }")
69:
70: (define_insn "tstdf"
71: [(set (cc0)
72: (match_operand:DF 0 "general_operand" "fmF"))]
73: "TARGET_32081"
74: "*
75: { cc_status.flags |= CC_REVERSED;
76: operands[1] = CONST0_RTX (DFmode);
77: return \"cmpl %1,%0\"; }")
78:
79: (define_insn "tstsf"
80: [(set (cc0)
81: (match_operand:SF 0 "general_operand" "fmF"))]
82: "TARGET_32081"
83: "*
84: { cc_status.flags |= CC_REVERSED;
85: operands[1] = CONST0_RTX (SFmode);
86: return \"cmpf %1,%0\"; }")
87:
88: (define_insn "cmpsi"
89: [(set (cc0)
90: (compare (match_operand:SI 0 "nonimmediate_operand" "rmn")
91: (match_operand:SI 1 "general_operand" "rmn")))]
92: ""
93: "*
94: {
95: if (GET_CODE (operands[1]) == CONST_INT)
96: {
97: int i = INTVAL (operands[1]);
98: if (i <= 7 && i >= -8)
99: {
100: cc_status.flags |= CC_REVERSED;
101: return \"cmpqd %1,%0\";
102: }
103: }
104: cc_status.flags &= ~CC_REVERSED;
105: if (GET_CODE (operands[0]) == CONST_INT)
106: {
107: int i = INTVAL (operands[0]);
108: if (i <= 7 && i >= -8)
109: return \"cmpqd %0,%1\";
110: }
111: return \"cmpd %0,%1\";
112: }")
113:
114: (define_insn "cmphi"
115: [(set (cc0)
116: (compare (match_operand:HI 0 "nonimmediate_operand" "g")
117: (match_operand:HI 1 "general_operand" "g")))]
118: ""
119: "*
120: {
121: if (GET_CODE (operands[1]) == CONST_INT)
122: {
123: short i = INTVAL (operands[1]);
124: if (i <= 7 && i >= -8)
125: {
126: cc_status.flags |= CC_REVERSED;
127: if (INTVAL (operands[1]) > 7)
128: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
129: return \"cmpqw %1,%0\";
130: }
131: }
132: cc_status.flags &= ~CC_REVERSED;
133: if (GET_CODE (operands[0]) == CONST_INT)
134: {
135: short i = INTVAL (operands[0]);
136: if (i <= 7 && i >= -8)
137: {
138: if (INTVAL (operands[0]) > 7)
139: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
140: return \"cmpqw %0,%1\";
141: }
142: }
143: return \"cmpw %0,%1\";
144: }")
145:
146: (define_insn "cmpqi"
147: [(set (cc0)
148: (compare (match_operand:QI 0 "nonimmediate_operand" "g")
149: (match_operand:QI 1 "general_operand" "g")))]
150: ""
151: "*
152: {
153: if (GET_CODE (operands[1]) == CONST_INT)
154: {
155: char i = INTVAL (operands[1]);
156: if (i <= 7 && i >= -8)
157: {
158: cc_status.flags |= CC_REVERSED;
159: if (INTVAL (operands[1]) > 7)
160: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
161: return \"cmpqb %1,%0\";
162: }
163: }
164: cc_status.flags &= ~CC_REVERSED;
165: if (GET_CODE (operands[0]) == CONST_INT)
166: {
167: char i = INTVAL (operands[0]);
168: if (i <= 7 && i >= -8)
169: {
170: if (INTVAL (operands[0]) > 7)
171: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
172: return \"cmpqb %0,%1\";
173: }
174: }
175: return \"cmpb %0,%1\";
176: }")
177:
178: (define_insn "cmpdf"
179: [(set (cc0)
180: (compare (match_operand:DF 0 "general_operand" "fmF")
181: (match_operand:DF 1 "general_operand" "fmF")))]
182: "TARGET_32081"
183: "cmpl %0,%1")
184:
185: (define_insn "cmpsf"
186: [(set (cc0)
187: (compare (match_operand:SF 0 "general_operand" "fmF")
188: (match_operand:SF 1 "general_operand" "fmF")))]
189: "TARGET_32081"
190: "cmpf %0,%1")
191:
192: (define_insn "movdf"
193: [(set (match_operand:DF 0 "general_operand" "=fg<")
194: (match_operand:DF 1 "general_operand" "fFg"))]
195: ""
196: "*
197: {
198: if (FP_REG_P (operands[0]))
199: {
200: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
201: return \"movl %1,%0\";
202: if (REG_P (operands[1]))
203: {
204: rtx xoperands[2];
205: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
206: output_asm_insn (\"movd %1,tos\", xoperands);
207: output_asm_insn (\"movd %1,tos\", operands);
208: return \"movl tos,%0\";
209: }
210: return \"movl %1,%0\";
211: }
212: else if (FP_REG_P (operands[1]))
213: {
214: if (REG_P (operands[0]))
215: {
216: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
217: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
218: return \"movd tos,%0\";
219: }
220: else
221: return \"movl %1,%0\";
222: }
223: return output_move_double (operands);
224: }")
225:
226: (define_insn "movsf"
227: [(set (match_operand:SF 0 "general_operand" "=fg<")
228: (match_operand:SF 1 "general_operand" "fFg"))]
229: ""
230: "*
231: {
232: if (FP_REG_P (operands[0]))
233: {
234: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
235: return \"movd %1,tos\;movf tos,%0\";
236: else
237: return \"movf %1,%0\";
238: }
239: else if (FP_REG_P (operands[1]))
240: {
241: if (REG_P (operands[0]))
242: return \"movf %1,tos\;movd tos,%0\";
243: return \"movf %1,%0\";
244: }
245: #if 0 /* Someone suggested this for the Sequent. Is it needed? */
246: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
247: return \"movf %1,%0\";
248: #endif
249: /* There was a #if 0 around this, but that was erroneous
250: for many machines -- rms. */
251: #ifndef MOVD_FLOAT_OK
252: /* GAS understands floating constants in ordinary movd instructions
253: but other assemblers might object. */
254: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
255: {
256: union {int i[2]; float f; double d;} convrt;
257: convrt.i[0] = CONST_DOUBLE_LOW (operands[1]);
258: convrt.i[1] = CONST_DOUBLE_HIGH (operands[1]);
259: convrt.f = convrt.d;
260:
261: /* Is there a better machine-independent way to to this? */
262: operands[1] = gen_rtx (CONST_INT, VOIDmode, convrt.i[0]);
263: return \"movd %1,%0\";
264: }
265: #endif
266: else return \"movd %1,%0\";
267: }")
268:
269: (define_insn ""
270: [(set (match_operand:TI 0 "memory_operand" "=m")
271: (match_operand:TI 1 "memory_operand" "m"))]
272: ""
273: "movmd %1,%0,4")
274:
275: (define_insn "movdi"
276: [(set (match_operand:DI 0 "general_operand" "=g<,*f,g")
277: (match_operand:DI 1 "general_operand" "gF,g,*f"))]
278: ""
279: "*
280: {
281: if (FP_REG_P (operands[0]))
282: {
283: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
284: return \"movl %1,%0\";
285: if (REG_P (operands[1]))
286: {
287: rtx xoperands[2];
288: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
289: output_asm_insn (\"movd %1,tos\", xoperands);
290: output_asm_insn (\"movd %1,tos\", operands);
291: return \"movl tos,%0\";
292: }
293: return \"movl %1,%0\";
294: }
295: else if (FP_REG_P (operands[1]))
296: {
297: if (REG_P (operands[0]))
298: {
299: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
300: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
301: return \"movd tos,%0\";
302: }
303: else
304: return \"movl %1,%0\";
305: }
306: return output_move_double (operands);
307: }")
308:
309: ;; This special case must precede movsi.
310: (define_insn ""
311: [(set (reg:SI 17)
312: (match_operand:SI 0 "general_operand" "rmn"))]
313: ""
314: "lprd sp,%0")
315:
316: (define_insn "movsi"
317: [(set (match_operand:SI 0 "general_operand" "=g<,g<,*f,g,x")
318: (match_operand:SI 1 "general_operand" "g,?xy,g,*f,rmn"))]
319: ""
320: "*
321: {
322: if (FP_REG_P (operands[0]))
323: {
324: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
325: return \"movd %1,tos\;movf tos,%0\";
326: else
327: return \"movf %1,%0\";
328: }
329: else if (FP_REG_P (operands[1]))
330: {
331: if (REG_P (operands[0]))
332: return \"movf %1,tos\;movd tos,%0\";
333: return \"movf %1,%0\";
334: }
335: if (GET_CODE (operands[0]) == REG
336: && REGNO (operands[0]) == FRAME_POINTER_REGNUM)
337: return \"lprd fp,%1\";
338: if (GET_CODE (operands[1]) == CONST_DOUBLE)
339: operands[1]
340: = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (operands[1]));
341: if (GET_CODE (operands[1]) == CONST_INT)
342: {
343: int i = INTVAL (operands[1]);
344: if (i <= 7 && i >= -8)
345: return \"movqd %1,%0\";
346: if (i < 0x4000 && i >= -0x4000 && ! TARGET_32532)
347: #if defined (GNX_V3) || defined (UTEK_ASM)
348: return \"addr %c1,%0\";
349: #else
350: return \"addr @%c1,%0\";
351: #endif
352: return \"movd %1,%0\";
353: }
354: else if (GET_CODE (operands[1]) == REG)
355: {
356: if (REGNO (operands[1]) < 16)
357: return \"movd %1,%0\";
358: else if (REGNO (operands[1]) == FRAME_POINTER_REGNUM)
359: {
360: if (GET_CODE(operands[0]) == REG)
361: return \"sprd fp,%0\";
362: else
363: return \"addr 0(fp),%0\" ;
364: }
365: else if (REGNO (operands[1]) == STACK_POINTER_REGNUM)
366: {
367: if (GET_CODE(operands[0]) == REG)
368: return \"sprd sp,%0\";
369: else
370: return \"addr 0(sp),%0\" ;
371: }
372: else abort ();
373: }
374: else if (GET_CODE (operands[1]) == MEM)
375: return \"movd %1,%0\";
376: /* Check if this effective address can be
377: calculated faster by pulling it apart. */
378: if (REG_P (operands[0])
379: && GET_CODE (operands[1]) == MULT
380: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
381: && (INTVAL (XEXP (operands[1], 1)) == 2
382: || INTVAL (XEXP (operands[1], 1)) == 4))
383: {
384: rtx xoperands[3];
385: xoperands[0] = operands[0];
386: xoperands[1] = XEXP (operands[1], 0);
387: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
388: return output_shift_insn (xoperands);
389: }
390: return \"addr %a1,%0\";
391: }")
392:
393: (define_insn "movhi"
394: [(set (match_operand:HI 0 "general_operand" "=g<,*f,g")
395: (match_operand:HI 1 "general_operand" "g,g,*f"))]
396: ""
397: "*
398: {
399: if (GET_CODE (operands[1]) == CONST_INT)
400: {
401: short i = INTVAL (operands[1]);
402: if (i <= 7 && i >= -8)
403: {
404: if (INTVAL (operands[1]) > 7)
405: operands[1] =
406: gen_rtx (CONST_INT, VOIDmode, i);
407: return \"movqw %1,%0\";
408: }
409: return \"movw %1,%0\";
410: }
411: else if (FP_REG_P (operands[0]))
412: {
413: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
414: return \"movwf %1,tos\;movf tos,%0\";
415: else
416: return \"movwf %1,%0\";
417: }
418: else if (FP_REG_P (operands[1]))
419: {
420: if (REG_P (operands[0]))
421: return \"movf %1,tos\;movd tos,%0\";
422: return \"movf %1,%0\";
423: }
424: else
425: return \"movw %1,%0\";
426: }")
427:
428: (define_insn "movstricthi"
429: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
430: (match_operand:HI 1 "general_operand" "g"))]
431: ""
432: "*
433: {
434: if (GET_CODE (operands[1]) == CONST_INT
435: && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
436: return \"movqw %1,%0\";
437: return \"movw %1,%0\";
438: }")
439:
440: (define_insn "movqi"
441: [(set (match_operand:QI 0 "general_operand" "=g<,*f,g")
442: (match_operand:QI 1 "general_operand" "g,g,*f"))]
443: ""
444: "*
445: { if (GET_CODE (operands[1]) == CONST_INT)
446: {
447: char char_val = (char)INTVAL (operands[1]);
448: if (char_val <= 7 && char_val >= -8)
449: {
450: if (INTVAL (operands[1]) > 7)
451: operands[1] =
452: gen_rtx (CONST_INT, VOIDmode, char_val);
453: return \"movqb %1,%0\";
454: }
455: return \"movb %1,%0\";
456: }
457: else if (FP_REG_P (operands[0]))
458: {
459: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
460: return \"movbf %1,tos\;movf tos,%0\";
461: else
462: return \"movbf %1,%0\";
463: }
464: else if (FP_REG_P (operands[1]))
465: {
466: if (REG_P (operands[0]))
467: return \"movf %1,tos\;movd tos,%0\";
468: return \"movf %1,%0\";
469: }
470: else
471: return \"movb %1,%0\";
472: }")
473:
474: (define_insn "movstrictqi"
475: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
476: (match_operand:QI 1 "general_operand" "g"))]
477: ""
478: "*
479: {
480: if (GET_CODE (operands[1]) == CONST_INT
481: && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
482: return \"movqb %1,%0\";
483: return \"movb %1,%0\";
484: }")
485:
486: ;; This is here to accept 4 arguments and pass the first 3 along
487: ;; to the movstrsi1 pattern that really does the work.
488: (define_expand "movstrsi"
489: [(set (match_operand:BLK 0 "general_operand" "=g")
490: (match_operand:BLK 1 "general_operand" "g"))
491: (use (match_operand:SI 2 "general_operand" "rmn"))
492: (match_operand 3 "" "")]
493: ""
494: "
495: emit_insn (gen_movstrsi1 (operands[0], operands[1], operands[2]));
496: DONE;
497: ")
498:
499: ;; The definition of this insn does not really explain what it does,
500: ;; but it should suffice
501: ;; that anything generated as this insn will be recognized as one
502: ;; and that it won't successfully combine with anything.
503: (define_insn "movstrsi1"
504: [(set (match_operand:BLK 0 "general_operand" "=g")
505: (match_operand:BLK 1 "general_operand" "g"))
506: (use (match_operand:SI 2 "general_operand" "rmn"))
507: (clobber (reg:SI 0))
508: (clobber (reg:SI 1))
509: (clobber (reg:SI 2))]
510: ""
511: "*
512: {
513: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
514: abort ();
515: operands[0] = XEXP (operands[0], 0);
516: operands[1] = XEXP (operands[1], 0);
517: if (GET_CODE (operands[0]) == MEM)
518: if (GET_CODE (operands[1]) == MEM)
519: output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands);
520: else
521: output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands);
522: else if (GET_CODE (operands[1]) == MEM)
523: output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands);
524: else
525: output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands);
526:
527: #ifdef UTEK_ASM
528: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
529: {
530: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
531: if ((unsigned) INTVAL (operands[2]) <= 7)
532: return \"movqd %2,r0\;movsd $0\";
533: else
534: return \"movd %2,r0\;movsd $0\";
535: }
536: else
537: {
538: return \"movd %2,r0\;movsb $0\";
539: }
540: #else
541: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
542: {
543: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
544: if ((unsigned) INTVAL (operands[2]) <= 7)
545: return \"movqd %2,r0\;movsd\";
546: else
547: return \"movd %2,r0\;movsd\";
548: }
549: else
550: {
551: return \"movd %2,r0\;movsb\";
552: }
553: #endif
554: }")
555:
556: ;; Extension and truncation insns.
557: ;; Those for integer source operand
558: ;; are ordered widest source type first.
559:
560: (define_insn "truncsiqi2"
561: [(set (match_operand:QI 0 "general_operand" "=g<")
562: (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "rmn")))]
563: ""
564: "movb %1,%0")
565:
566: (define_insn "truncsihi2"
567: [(set (match_operand:HI 0 "general_operand" "=g<")
568: (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "rmn")))]
569: ""
570: "movw %1,%0")
571:
572: (define_insn "trunchiqi2"
573: [(set (match_operand:QI 0 "general_operand" "=g<")
574: (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
575: ""
576: "movb %1,%0")
577:
578: (define_insn "extendhisi2"
579: [(set (match_operand:SI 0 "general_operand" "=g<")
580: (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
581: ""
582: "movxwd %1,%0")
583:
584: (define_insn "extendqihi2"
585: [(set (match_operand:HI 0 "general_operand" "=g<")
586: (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
587: ""
588: "movxbw %1,%0")
589:
590: (define_insn "extendqisi2"
591: [(set (match_operand:SI 0 "general_operand" "=g<")
592: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
593: ""
594: "movxbd %1,%0")
595:
596: (define_insn "extendsfdf2"
597: [(set (match_operand:DF 0 "general_operand" "=fm<")
598: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
599: "TARGET_32081"
600: "movfl %1,%0")
601:
602: (define_insn "truncdfsf2"
603: [(set (match_operand:SF 0 "general_operand" "=fm<")
604: (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))]
605: "TARGET_32081"
606: "movlf %1,%0")
607:
608: (define_insn "zero_extendhisi2"
609: [(set (match_operand:SI 0 "general_operand" "=g<")
610: (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
611: ""
612: "movzwd %1,%0")
613:
614: (define_insn "zero_extendqihi2"
615: [(set (match_operand:HI 0 "general_operand" "=g<")
616: (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
617: ""
618: "movzbw %1,%0")
619:
620: (define_insn "zero_extendqisi2"
621: [(set (match_operand:SI 0 "general_operand" "=g<")
622: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
623: ""
624: "movzbd %1,%0")
625:
626: ;; Fix-to-float conversion insns.
627: ;; Note that the ones that start with SImode come first.
628: ;; That is so that an operand that is a CONST_INT
629: ;; (and therefore lacks a specific machine mode).
630: ;; will be recognized as SImode (which is always valid)
631: ;; rather than as QImode or HImode.
632:
633: ;; Rumor has it that the National part does not correctly convert
634: ;; constant ints to floats. This conversion is therefore disabled.
635: ;; A register must be used to perform the conversion.
636:
637: (define_insn "floatsisf2"
638: [(set (match_operand:SF 0 "general_operand" "=fm<")
639: (float:SF (match_operand:SI 1 "general_operand" "rm")))]
640: "TARGET_32081"
641: "movdf %1,%0")
642:
643: (define_insn "floatsidf2"
644: [(set (match_operand:DF 0 "general_operand" "=fm<")
645: (float:DF (match_operand:SI 1 "general_operand" "rm")))]
646: "TARGET_32081"
647: "movdl %1,%0")
648:
649: (define_insn "floathisf2"
650: [(set (match_operand:SF 0 "general_operand" "=fm<")
651: (float:SF (match_operand:HI 1 "general_operand" "rm")))]
652: "TARGET_32081"
653: "movwf %1,%0")
654:
655: (define_insn "floathidf2"
656: [(set (match_operand:DF 0 "general_operand" "=fm<")
657: (float:DF (match_operand:HI 1 "general_operand" "rm")))]
658: "TARGET_32081"
659: "movwl %1,%0")
660:
661: (define_insn "floatqisf2"
662: [(set (match_operand:SF 0 "general_operand" "=fm<")
663: (float:SF (match_operand:QI 1 "general_operand" "rm")))]
664: "TARGET_32081"
665: "movbf %1,%0")
666:
667: ; Some assemblers warn that this insn doesn't work.
668: ; Maybe they know something we don't.
669: ;(define_insn "floatqidf2"
670: ; [(set (match_operand:DF 0 "general_operand" "=fm<")
671: ; (float:DF (match_operand:QI 1 "general_operand" "rm")))]
672: ; "TARGET_32081"
673: ; "movbl %1,%0")
674:
675: ;; Float-to-fix conversion insns.
676: ;; The sequent compiler always generates "trunc" insns.
677:
678: (define_insn "fixsfqi2"
679: [(set (match_operand:QI 0 "general_operand" "=g<")
680: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
681: "TARGET_32081"
682: "truncfb %1,%0")
683:
684: (define_insn "fixsfhi2"
685: [(set (match_operand:HI 0 "general_operand" "=g<")
686: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
687: "TARGET_32081"
688: "truncfw %1,%0")
689:
690: (define_insn "fixsfsi2"
691: [(set (match_operand:SI 0 "general_operand" "=g<")
692: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
693: "TARGET_32081"
694: "truncfd %1,%0")
695:
696: (define_insn "fixdfqi2"
697: [(set (match_operand:QI 0 "general_operand" "=g<")
698: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
699: "TARGET_32081"
700: "trunclb %1,%0")
701:
702: (define_insn "fixdfhi2"
703: [(set (match_operand:HI 0 "general_operand" "=g<")
704: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
705: "TARGET_32081"
706: "trunclw %1,%0")
707:
708: (define_insn "fixdfsi2"
709: [(set (match_operand:SI 0 "general_operand" "=g<")
710: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
711: "TARGET_32081"
712: "truncld %1,%0")
713:
714: ;; Unsigned
715:
716: (define_insn "fixunssfqi2"
717: [(set (match_operand:QI 0 "general_operand" "=g<")
718: (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
719: "TARGET_32081"
720: "truncfb %1,%0")
721:
722: (define_insn "fixunssfhi2"
723: [(set (match_operand:HI 0 "general_operand" "=g<")
724: (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
725: "TARGET_32081"
726: "truncfw %1,%0")
727:
728: (define_insn "fixunssfsi2"
729: [(set (match_operand:SI 0 "general_operand" "=g<")
730: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
731: "TARGET_32081"
732: "truncfd %1,%0")
733:
734: (define_insn "fixunsdfqi2"
735: [(set (match_operand:QI 0 "general_operand" "=g<")
736: (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
737: "TARGET_32081"
738: "trunclb %1,%0")
739:
740: (define_insn "fixunsdfhi2"
741: [(set (match_operand:HI 0 "general_operand" "=g<")
742: (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
743: "TARGET_32081"
744: "trunclw %1,%0")
745:
746: (define_insn "fixunsdfsi2"
747: [(set (match_operand:SI 0 "general_operand" "=g<")
748: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
749: "TARGET_32081"
750: "truncld %1,%0")
751:
752: ;;; These are not yet used by GCC
753: (define_insn "fix_truncsfqi2"
754: [(set (match_operand:QI 0 "general_operand" "=g<")
755: (fix:QI (match_operand:SF 1 "general_operand" "fm")))]
756: "TARGET_32081"
757: "truncfb %1,%0")
758:
759: (define_insn "fix_truncsfhi2"
760: [(set (match_operand:HI 0 "general_operand" "=g<")
761: (fix:HI (match_operand:SF 1 "general_operand" "fm")))]
762: "TARGET_32081"
763: "truncfw %1,%0")
764:
765: (define_insn "fix_truncsfsi2"
766: [(set (match_operand:SI 0 "general_operand" "=g<")
767: (fix:SI (match_operand:SF 1 "general_operand" "fm")))]
768: "TARGET_32081"
769: "truncfd %1,%0")
770:
771: (define_insn "fix_truncdfqi2"
772: [(set (match_operand:QI 0 "general_operand" "=g<")
773: (fix:QI (match_operand:DF 1 "general_operand" "fm")))]
774: "TARGET_32081"
775: "trunclb %1,%0")
776:
777: (define_insn "fix_truncdfhi2"
778: [(set (match_operand:HI 0 "general_operand" "=g<")
779: (fix:HI (match_operand:DF 1 "general_operand" "fm")))]
780: "TARGET_32081"
781: "trunclw %1,%0")
782:
783: (define_insn "fix_truncdfsi2"
784: [(set (match_operand:SI 0 "general_operand" "=g<")
785: (fix:SI (match_operand:DF 1 "general_operand" "fm")))]
786: "TARGET_32081"
787: "truncld %1,%0")
788:
789: ;;- All kinds of add instructions.
790:
791: (define_insn "adddf3"
792: [(set (match_operand:DF 0 "general_operand" "=fm")
793: (plus:DF (match_operand:DF 1 "general_operand" "%0")
794: (match_operand:DF 2 "general_operand" "fmF")))]
795: "TARGET_32081"
796: "addl %2,%0")
797:
798:
799: (define_insn "addsf3"
800: [(set (match_operand:SF 0 "general_operand" "=fm")
801: (plus:SF (match_operand:SF 1 "general_operand" "%0")
802: (match_operand:SF 2 "general_operand" "fmF")))]
803: "TARGET_32081"
804: "addf %2,%0")
805:
806: (define_insn ""
807: [(set (reg:SI 17)
808: (plus:SI (reg:SI 17)
809: (match_operand:SI 0 "immediate_operand" "i")))]
810: "GET_CODE (operands[0]) == CONST_INT"
811: "*
812: {
813: #ifndef SEQUENT_ADJUST_STACK
814: if (TARGET_32532)
815: if (INTVAL (operands[0]) == 8)
816: return \"cmpd tos,tos\";
817: if (TARGET_32532 || TARGET_32332)
818: if (INTVAL (operands[0]) == 4)
819: return \"cmpqd %$0,tos\";
820: #endif
821: if (! TARGET_32532)
822: {
823: if (INTVAL (operands[0]) < 64 && INTVAL (operands[0]) > -64)
824: return \"adjspb %$%n0\";
825: else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
826: return \"adjspw %$%n0\";
827: }
828: return \"adjspd %$%n0\";
829: }")
830:
831: (define_insn ""
832: [(set (match_operand:SI 0 "general_operand" "=g<")
833: (plus:SI (reg:SI 16)
834: (match_operand:SI 1 "immediate_operand" "i")))]
835: "GET_CODE (operands[1]) == CONST_INT"
836: "addr %c1(fp),%0")
837:
838: (define_insn ""
839: [(set (match_operand:SI 0 "general_operand" "=g<")
840: (plus:SI (reg:SI 17)
841: (match_operand:SI 1 "immediate_operand" "i")))]
842: "GET_CODE (operands[1]) == CONST_INT"
843: "addr %c1(sp),%0")
844:
845: (define_insn "addsi3"
846: [(set (match_operand:SI 0 "general_operand" "=g,=g&<")
847: (plus:SI (match_operand:SI 1 "general_operand" "%0,r")
848: (match_operand:SI 2 "general_operand" "rmn,n")))]
849: ""
850: "*
851: {
852: if (which_alternative == 1)
853: {
854: int i = INTVAL (operands[2]);
855: if (NS32K_DISPLACEMENT_P (i))
856: return \"addr %c2(%1),%0\";
857: else
858: return \"movd %1,%0\;addd %2,%0\";
859: }
860: if (GET_CODE (operands[2]) == CONST_INT)
861: {
862: int i = INTVAL (operands[2]);
863:
864: if (i <= 7 && i >= -8)
865: return \"addqd %2,%0\";
866: else if (GET_CODE (operands[0]) == REG
867: && i < 0x4000 && i >= -0x4000 && ! TARGET_32532)
868: return \"addr %c2(%0),%0\";
869: }
870: return \"addd %2,%0\";
871: }")
872:
873: (define_insn "addhi3"
874: [(set (match_operand:HI 0 "general_operand" "=g")
875: (plus:HI (match_operand:HI 1 "general_operand" "%0")
876: (match_operand:HI 2 "general_operand" "g")))]
877: ""
878: "*
879: { if (GET_CODE (operands[2]) == CONST_INT)
880: {
881: int i = INTVAL (operands[2]);
882: if (i <= 7 && i >= -8)
883: return \"addqw %2,%0\";
884: }
885: return \"addw %2,%0\";
886: }")
887:
888: (define_insn ""
889: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
890: (plus:HI (match_operand:HI 1 "general_operand" "0")
891: (match_operand:HI 2 "general_operand" "g")))]
892: ""
893: "*
894: {
895: if (GET_CODE (operands[1]) == CONST_INT
896: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
897: return \"addqw %2,%0\";
898: return \"addw %2,%0\";
899: }")
900:
901: (define_insn "addqi3"
902: [(set (match_operand:QI 0 "general_operand" "=g")
903: (plus:QI (match_operand:QI 1 "general_operand" "%0")
904: (match_operand:QI 2 "general_operand" "g")))]
905: ""
906: "*
907: { if (GET_CODE (operands[2]) == CONST_INT)
908: {
909: int i = INTVAL (operands[2]);
910: if (i <= 7 && i >= -8)
911: return \"addqb %2,%0\";
912: }
913: return \"addb %2,%0\";
914: }")
915:
916: (define_insn ""
917: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
918: (plus:QI (match_operand:QI 1 "general_operand" "0")
919: (match_operand:QI 2 "general_operand" "g")))]
920: ""
921: "*
922: {
923: if (GET_CODE (operands[1]) == CONST_INT
924: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
925: return \"addqb %2,%0\";
926: return \"addb %2,%0\";
927: }")
928:
929: ;;- All kinds of subtract instructions.
930:
931: (define_insn "subdf3"
932: [(set (match_operand:DF 0 "general_operand" "=fm")
933: (minus:DF (match_operand:DF 1 "general_operand" "0")
934: (match_operand:DF 2 "general_operand" "fmF")))]
935: "TARGET_32081"
936: "subl %2,%0")
937:
938: (define_insn "subsf3"
939: [(set (match_operand:SF 0 "general_operand" "=fm")
940: (minus:SF (match_operand:SF 1 "general_operand" "0")
941: (match_operand:SF 2 "general_operand" "fmF")))]
942: "TARGET_32081"
943: "subf %2,%0")
944:
945: (define_insn ""
946: [(set (reg:SI 17)
947: (minus:SI (reg:SI 17)
948: (match_operand:SI 0 "immediate_operand" "i")))]
949: "GET_CODE (operands[0]) == CONST_INT"
950: "*
951: {
952: if (GET_CODE(operands[0]) == CONST_INT && INTVAL(operands[0]) < 64
953: && INTVAL(operands[0]) > -64 && ! TARGET_32532)
954: return \"adjspb %$%0\";
955: return \"adjspd %$%0\";
956: }")
957:
958: (define_insn "subsi3"
959: [(set (match_operand:SI 0 "general_operand" "=g")
960: (minus:SI (match_operand:SI 1 "general_operand" "0")
961: (match_operand:SI 2 "general_operand" "rmn")))]
962: ""
963: "*
964: { if (GET_CODE (operands[2]) == CONST_INT)
965: {
966: int i = INTVAL (operands[2]);
967:
968: if (i <= 8 && i >= -7)
969: return \"addqd %$%n2,%0\";
970: }
971: return \"subd %2,%0\";
972: }")
973:
974: (define_insn "subhi3"
975: [(set (match_operand:HI 0 "general_operand" "=g")
976: (minus:HI (match_operand:HI 1 "general_operand" "0")
977: (match_operand:HI 2 "general_operand" "g")))]
978: ""
979: "*
980: { if (GET_CODE (operands[2]) == CONST_INT)
981: {
982: int i = INTVAL (operands[2]);
983:
984: if (i <= 8 && i >= -7)
985: return \"addqw %$%n2,%0\";
986: }
987: return \"subw %2,%0\";
988: }")
989:
990: (define_insn ""
991: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
992: (minus:HI (match_operand:HI 1 "general_operand" "0")
993: (match_operand:HI 2 "general_operand" "g")))]
994: ""
995: "*
996: {
997: if (GET_CODE (operands[1]) == CONST_INT
998: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
999: return \"addqw %$%n2,%0\";
1000: return \"subw %2,%0\";
1001: }")
1002:
1003: (define_insn "subqi3"
1004: [(set (match_operand:QI 0 "general_operand" "=g")
1005: (minus:QI (match_operand:QI 1 "general_operand" "0")
1006: (match_operand:QI 2 "general_operand" "g")))]
1007: ""
1008: "*
1009: { if (GET_CODE (operands[2]) == CONST_INT)
1010: {
1011: int i = INTVAL (operands[2]);
1012:
1013: if (i <= 8 && i >= -7)
1014: return \"addqb %$%n2,%0\";
1015: }
1016: return \"subb %2,%0\";
1017: }")
1018:
1019: (define_insn ""
1020: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
1021: (minus:QI (match_operand:QI 1 "general_operand" "0")
1022: (match_operand:QI 2 "general_operand" "g")))]
1023: ""
1024: "*
1025: {
1026: if (GET_CODE (operands[1]) == CONST_INT
1027: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
1028: return \"addqb %$%n2,%0\";
1029: return \"subb %2,%0\";
1030: }")
1031:
1032: ;;- Multiply instructions.
1033:
1034: (define_insn "muldf3"
1035: [(set (match_operand:DF 0 "general_operand" "=fm")
1036: (mult:DF (match_operand:DF 1 "general_operand" "%0")
1037: (match_operand:DF 2 "general_operand" "fmF")))]
1038: "TARGET_32081"
1039: "mull %2,%0")
1040:
1041: (define_insn "mulsf3"
1042: [(set (match_operand:SF 0 "general_operand" "=fm")
1043: (mult:SF (match_operand:SF 1 "general_operand" "%0")
1044: (match_operand:SF 2 "general_operand" "fmF")))]
1045: "TARGET_32081"
1046: "mulf %2,%0")
1047:
1048: (define_insn "mulsi3"
1049: [(set (match_operand:SI 0 "general_operand" "=g")
1050: (mult:SI (match_operand:SI 1 "general_operand" "%0")
1051: (match_operand:SI 2 "general_operand" "rmn")))]
1052: ""
1053: "muld %2,%0")
1054:
1055: (define_insn "mulhi3"
1056: [(set (match_operand:HI 0 "general_operand" "=g")
1057: (mult:HI (match_operand:HI 1 "general_operand" "%0")
1058: (match_operand:HI 2 "general_operand" "g")))]
1059: ""
1060: "mulw %2,%0")
1061:
1062: (define_insn "mulqi3"
1063: [(set (match_operand:QI 0 "general_operand" "=g")
1064: (mult:QI (match_operand:QI 1 "general_operand" "%0")
1065: (match_operand:QI 2 "general_operand" "g")))]
1066: ""
1067: "mulb %2,%0")
1068:
1069: (define_insn "umulsidi3"
1070: [(set (match_operand:DI 0 "general_operand" "=g")
1071: (mult:DI (zero_extend:DI
1072: (match_operand:SI 1 "nonimmediate_operand" "0"))
1073: (zero_extend:DI
1074: (match_operand:SI 2 "nonimmediate_operand" "rmn"))))]
1075: ""
1076: "meid %2,%0")
1077:
1078: ;;- Divide instructions.
1079:
1080: (define_insn "divdf3"
1081: [(set (match_operand:DF 0 "general_operand" "=fm")
1082: (div:DF (match_operand:DF 1 "general_operand" "0")
1083: (match_operand:DF 2 "general_operand" "fmF")))]
1084: "TARGET_32081"
1085: "divl %2,%0")
1086:
1087: (define_insn "divsf3"
1088: [(set (match_operand:SF 0 "general_operand" "=fm")
1089: (div:SF (match_operand:SF 1 "general_operand" "0")
1090: (match_operand:SF 2 "general_operand" "fmF")))]
1091: "TARGET_32081"
1092: "divf %2,%0")
1093:
1094: (define_insn "divsi3"
1095: [(set (match_operand:SI 0 "general_operand" "=g")
1096: (div:SI (match_operand:SI 1 "general_operand" "0")
1097: (match_operand:SI 2 "general_operand" "rmn")))]
1098: ""
1099: "quod %2,%0")
1100:
1101: (define_insn "divhi3"
1102: [(set (match_operand:HI 0 "general_operand" "=g")
1103: (div:HI (match_operand:HI 1 "general_operand" "0")
1104: (match_operand:HI 2 "general_operand" "g")))]
1105: ""
1106: "quow %2,%0")
1107:
1108: (define_insn "divqi3"
1109: [(set (match_operand:QI 0 "general_operand" "=g")
1110: (div:QI (match_operand:QI 1 "general_operand" "0")
1111: (match_operand:QI 2 "general_operand" "g")))]
1112: ""
1113: "quob %2,%0")
1114:
1115: (define_insn "udivsi3"
1116: [(set (match_operand:SI 0 "register_operand" "=r")
1117: (udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1118: (match_operand:SI 2 "general_operand" "rmn")))]
1119: ""
1120: "*
1121: {
1122: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1123: return \"deid %2,%0\;movd %1,%0\";
1124: }")
1125:
1126: (define_insn "udivhi3"
1127: [(set (match_operand:HI 0 "register_operand" "=r")
1128: (udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1129: (match_operand:HI 2 "general_operand" "g")))]
1130: ""
1131: "*
1132: {
1133: operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1);
1134: return \"deiw %2,%0\;movw %1,%0\";
1135: }")
1136:
1137: (define_insn "udivqi3"
1138: [(set (match_operand:QI 0 "register_operand" "=r")
1139: (udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1140: (match_operand:QI 2 "general_operand" "g")))]
1141: ""
1142: "*
1143: {
1144: operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1);
1145: return \"deib %2,%0\;movb %1,%0\";
1146: }")
1147:
1148: ;; Remainder instructions.
1149:
1150: (define_insn "modsi3"
1151: [(set (match_operand:SI 0 "general_operand" "=g")
1152: (mod:SI (match_operand:SI 1 "general_operand" "0")
1153: (match_operand:SI 2 "general_operand" "rmn")))]
1154: ""
1155: "remd %2,%0")
1156:
1157: (define_insn "modhi3"
1158: [(set (match_operand:HI 0 "general_operand" "=g")
1159: (mod:HI (match_operand:HI 1 "general_operand" "0")
1160: (match_operand:HI 2 "general_operand" "g")))]
1161: ""
1162: "remw %2,%0")
1163:
1164: (define_insn "modqi3"
1165: [(set (match_operand:QI 0 "general_operand" "=g")
1166: (mod:QI (match_operand:QI 1 "general_operand" "0")
1167: (match_operand:QI 2 "general_operand" "g")))]
1168: ""
1169: "remb %2,%0")
1170:
1171: (define_insn "umodsi3"
1172: [(set (match_operand:SI 0 "register_operand" "=r")
1173: (umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1174: (match_operand:SI 2 "general_operand" "rmn")))]
1175: ""
1176: "deid %2,%0")
1177:
1178: (define_insn "umodhi3"
1179: [(set (match_operand:HI 0 "register_operand" "=r")
1180: (umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1181: (match_operand:HI 2 "general_operand" "g")))]
1182: ""
1183: "deiw %2,%0")
1184:
1185: (define_insn "umodqi3"
1186: [(set (match_operand:QI 0 "register_operand" "=r")
1187: (umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1188: (match_operand:QI 2 "general_operand" "g")))]
1189: ""
1190: "deib %2,%0")
1191:
1192: ; This isn't be usable in its current form.
1193: ;(define_insn "udivmoddisi4"
1194: ; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1)
1195: ; (udiv:SI (match_operand:DI 1 "general_operand" "0")
1196: ; (match_operand:SI 2 "general_operand" "rmn")))
1197: ; (set (subreg:SI (match_dup 0) 0)
1198: ; (umod:SI (match_dup 1) (match_dup 2)))]
1199: ; ""
1200: ; "deid %2,%0")
1201:
1202: ;;- Logical Instructions: AND
1203:
1204: (define_insn "andsi3"
1205: [(set (match_operand:SI 0 "general_operand" "=g")
1206: (and:SI (match_operand:SI 1 "general_operand" "%0")
1207: (match_operand:SI 2 "general_operand" "rmn")))]
1208: ""
1209: "*
1210: {
1211: if (GET_CODE (operands[2]) == CONST_INT)
1212: {
1213: if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
1214: {
1215: if (INTVAL (operands[2]) == 0xffffff00)
1216: return \"movqb %$0,%0\";
1217: else
1218: {
1219: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1220: INTVAL (operands[2]) & 0xff);
1221: return \"andb %2,%0\";
1222: }
1223: }
1224: if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
1225: {
1226: if (INTVAL (operands[2]) == 0xffff0000)
1227: return \"movqw %$0,%0\";
1228: else
1229: {
1230: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1231: INTVAL (operands[2]) & 0xffff);
1232: return \"andw %2,%0\";
1233: }
1234: }
1235: }
1236: return \"andd %2,%0\";
1237: }")
1238:
1239: (define_insn "andhi3"
1240: [(set (match_operand:HI 0 "general_operand" "=g")
1241: (and:HI (match_operand:HI 1 "general_operand" "%0")
1242: (match_operand:HI 2 "general_operand" "g")))]
1243: ""
1244: "*
1245: {
1246: if (GET_CODE (operands[2]) == CONST_INT
1247: && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
1248: {
1249: if (INTVAL (operands[2]) == 0xffffff00)
1250: return \"movqb %$0,%0\";
1251: else
1252: {
1253: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1254: INTVAL (operands[2]) & 0xff);
1255: return \"andb %2,%0\";
1256: }
1257: }
1258: return \"andw %2,%0\";
1259: }")
1260:
1261: (define_insn "andqi3"
1262: [(set (match_operand:QI 0 "general_operand" "=g")
1263: (and:QI (match_operand:QI 1 "general_operand" "%0")
1264: (match_operand:QI 2 "general_operand" "g")))]
1265: ""
1266: "andb %2,%0")
1267:
1268: (define_insn ""
1269: [(set (match_operand:SI 0 "general_operand" "=g")
1270: (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn"))
1271: (match_operand:SI 2 "general_operand" "0")))]
1272: ""
1273: "bicd %1,%0")
1274:
1275: (define_insn ""
1276: [(set (match_operand:HI 0 "general_operand" "=g")
1277: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1278: (match_operand:HI 2 "general_operand" "0")))]
1279: ""
1280: "bicw %1,%0")
1281:
1282: (define_insn ""
1283: [(set (match_operand:QI 0 "general_operand" "=g")
1284: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1285: (match_operand:QI 2 "general_operand" "0")))]
1286: ""
1287: "bicb %1,%0")
1288:
1289: ;;- Bit set instructions.
1290:
1291: (define_insn "iorsi3"
1292: [(set (match_operand:SI 0 "general_operand" "=g")
1293: (ior:SI (match_operand:SI 1 "general_operand" "%0")
1294: (match_operand:SI 2 "general_operand" "rmn")))]
1295: ""
1296: "*
1297: {
1298: if (GET_CODE (operands[2]) == CONST_INT) {
1299: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1300: return \"orb %2,%0\";
1301: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1302: return \"orw %2,%0\";
1303: }
1304: return \"ord %2,%0\";
1305: }")
1306:
1307: (define_insn "iorhi3"
1308: [(set (match_operand:HI 0 "general_operand" "=g")
1309: (ior:HI (match_operand:HI 1 "general_operand" "%0")
1310: (match_operand:HI 2 "general_operand" "g")))]
1311: ""
1312: "*
1313: {
1314: if (GET_CODE(operands[2]) == CONST_INT &&
1315: (INTVAL(operands[2]) & 0xffffff00) == 0)
1316: return \"orb %2,%0\";
1317: return \"orw %2,%0\";
1318: }")
1319:
1320: (define_insn "iorqi3"
1321: [(set (match_operand:QI 0 "general_operand" "=g")
1322: (ior:QI (match_operand:QI 1 "general_operand" "%0")
1323: (match_operand:QI 2 "general_operand" "g")))]
1324: ""
1325: "orb %2,%0")
1326:
1327: ;;- xor instructions.
1328:
1329: (define_insn "xorsi3"
1330: [(set (match_operand:SI 0 "general_operand" "=g")
1331: (xor:SI (match_operand:SI 1 "general_operand" "%0")
1332: (match_operand:SI 2 "general_operand" "rmn")))]
1333: ""
1334: "*
1335: {
1336: if (GET_CODE (operands[2]) == CONST_INT) {
1337: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1338: return \"xorb %2,%0\";
1339: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1340: return \"xorw %2,%0\";
1341: }
1342: return \"xord %2,%0\";
1343: }")
1344:
1345: (define_insn "xorhi3"
1346: [(set (match_operand:HI 0 "general_operand" "=g")
1347: (xor:HI (match_operand:HI 1 "general_operand" "%0")
1348: (match_operand:HI 2 "general_operand" "g")))]
1349: ""
1350: "*
1351: {
1352: if (GET_CODE(operands[2]) == CONST_INT &&
1353: (INTVAL(operands[2]) & 0xffffff00) == 0)
1354: return \"xorb %2,%0\";
1355: return \"xorw %2,%0\";
1356: }")
1357:
1358: (define_insn "xorqi3"
1359: [(set (match_operand:QI 0 "general_operand" "=g")
1360: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1361: (match_operand:QI 2 "general_operand" "g")))]
1362: ""
1363: "xorb %2,%0")
1364:
1365: (define_insn "negdf2"
1366: [(set (match_operand:DF 0 "general_operand" "=fm<")
1367: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1368: "TARGET_32081"
1369: "negl %1,%0")
1370:
1371: (define_insn "negsf2"
1372: [(set (match_operand:SF 0 "general_operand" "=fm<")
1373: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1374: "TARGET_32081"
1375: "negf %1,%0")
1376:
1377: (define_insn "negsi2"
1378: [(set (match_operand:SI 0 "general_operand" "=g<")
1379: (neg:SI (match_operand:SI 1 "general_operand" "rmn")))]
1380: ""
1381: "negd %1,%0")
1382:
1383: (define_insn "neghi2"
1384: [(set (match_operand:HI 0 "general_operand" "=g<")
1385: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1386: ""
1387: "negw %1,%0")
1388:
1389: (define_insn "negqi2"
1390: [(set (match_operand:QI 0 "general_operand" "=g<")
1391: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1392: ""
1393: "negb %1,%0")
1394:
1395: (define_insn "one_cmplsi2"
1396: [(set (match_operand:SI 0 "general_operand" "=g<")
1397: (not:SI (match_operand:SI 1 "general_operand" "rmn")))]
1398: ""
1399: "comd %1,%0")
1400:
1401: (define_insn "one_cmplhi2"
1402: [(set (match_operand:HI 0 "general_operand" "=g<")
1403: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1404: ""
1405: "comw %1,%0")
1406:
1407: (define_insn "one_cmplqi2"
1408: [(set (match_operand:QI 0 "general_operand" "=g<")
1409: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1410: ""
1411: "comb %1,%0")
1412:
1413: ;; arithmetic left and right shift operations
1414: ;; on the 32532 we will always use lshd for arithmetic left shifts,
1415: ;; because it is three times faster. Broken programs which
1416: ;; use negative shift counts are probably broken differently
1417: ;; than elsewhere.
1418:
1419: ;; alternative 0 never matches on the 32532
1420: (define_insn "ashlsi3"
1421: [(set (match_operand:SI 0 "general_operand" "=g,g")
1422: (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1423: (match_operand:SI 2 "general_operand" "I,rmn")))]
1424: ""
1425: "*
1426: { if (TARGET_32532)
1427: return \"lshd %2,%0\";
1428: else
1429: return output_shift_insn (operands);
1430: }")
1431:
1432: (define_insn "ashlhi3"
1433: [(set (match_operand:HI 0 "general_operand" "=g")
1434: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1435: (match_operand:SI 2 "general_operand" "rmn")))]
1436: ""
1437: "*
1438: { if (GET_CODE (operands[2]) == CONST_INT)
1439: {
1440: if (INTVAL (operands[2]) == 1)
1441: return \"addw %0,%0\";
1442: else if (INTVAL (operands[2]) == 2 && !TARGET_32532)
1443: return \"addw %0,%0\;addw %0,%0\";
1444: }
1445: if (TARGET_32532)
1446: return \"lshw %2,%0\";
1447: else
1448: return \"ashw %2,%0\";
1449: }")
1450:
1451: (define_insn "ashlqi3"
1452: [(set (match_operand:QI 0 "general_operand" "=g")
1453: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1454: (match_operand:SI 2 "general_operand" "rmn")))]
1455: ""
1456: "*
1457: { if (GET_CODE (operands[2]) == CONST_INT)
1458: {
1459: if (INTVAL (operands[2]) == 1)
1460: return \"addb %0,%0\";
1461: else if (INTVAL (operands[2]) == 2 && !TARGET_32532)
1462: return \"addb %0,%0\;addb %0,%0\";
1463: }
1464: if (TARGET_32532)
1465: return \"lshb %2,%0\";
1466: else
1467: return \"ashb %2,%0\";
1468: }")
1469:
1470: ;; Arithmetic right shift on the 32k works by negating the shift count.
1471: (define_expand "ashrsi3"
1472: [(set (match_operand:SI 0 "general_operand" "=g")
1473: (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1474: (match_operand:SI 2 "general_operand" "g")))]
1475: ""
1476: "
1477: {
1478: if (GET_CODE (operands[2]) != CONST_INT)
1479: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1480: }")
1481:
1482: (define_insn ""
1483: [(set (match_operand:SI 0 "general_operand" "=g")
1484: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1485: (match_operand:SI 2 "immediate_operand" "i")))]
1486: ""
1487: "ashd %$%n2,%0")
1488:
1489: (define_insn ""
1490: [(set (match_operand:SI 0 "general_operand" "=g")
1491: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1492: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1493: ""
1494: "ashd %2,%0")
1495:
1496: (define_expand "ashrhi3"
1497: [(set (match_operand:HI 0 "general_operand" "=g")
1498: (ashiftrt:HI (match_operand:HI 1 "general_operand" "g")
1499: (match_operand:SI 2 "general_operand" "g")))]
1500: ""
1501: "
1502: {
1503: if (GET_CODE (operands[2]) != CONST_INT)
1504: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1505: }")
1506:
1507: (define_insn ""
1508: [(set (match_operand:HI 0 "general_operand" "=g")
1509: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1510: (match_operand:SI 2 "immediate_operand" "i")))]
1511: ""
1512: "ashw %$%n2,%0")
1513:
1514: (define_insn ""
1515: [(set (match_operand:HI 0 "general_operand" "=g")
1516: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1517: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1518: ""
1519: "ashw %2,%0")
1520:
1521: (define_expand "ashrqi3"
1522: [(set (match_operand:QI 0 "general_operand" "=g")
1523: (ashiftrt:QI (match_operand:QI 1 "general_operand" "g")
1524: (match_operand:SI 2 "general_operand" "g")))]
1525: ""
1526: "
1527: {
1528: if (GET_CODE (operands[2]) != CONST_INT)
1529: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1530: }")
1531:
1532: (define_insn ""
1533: [(set (match_operand:QI 0 "general_operand" "=g")
1534: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1535: (match_operand:SI 2 "immediate_operand" "i")))]
1536: ""
1537: "ashb %$%n2,%0")
1538:
1539: (define_insn ""
1540: [(set (match_operand:QI 0 "general_operand" "=g")
1541: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1542: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1543: ""
1544: "ashb %2,%0")
1545:
1546: ;; logical shift instructions
1547:
1548: (define_insn "lshlsi3"
1549: [(set (match_operand:SI 0 "general_operand" "=g")
1550: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1551: (match_operand:SI 2 "general_operand" "rmn")))]
1552: ""
1553: "lshd %2,%0")
1554:
1555: (define_insn "lshlhi3"
1556: [(set (match_operand:HI 0 "general_operand" "=g")
1557: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1558: (match_operand:SI 2 "general_operand" "rmn")))]
1559: ""
1560: "lshw %2,%0")
1561:
1562: (define_insn "lshlqi3"
1563: [(set (match_operand:QI 0 "general_operand" "=g")
1564: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1565: (match_operand:SI 2 "general_operand" "rmn")))]
1566: ""
1567: "lshb %2,%0")
1568:
1569: ;; Logical right shift on the 32k works by negating the shift count.
1570: (define_expand "lshrsi3"
1571: [(set (match_operand:SI 0 "general_operand" "=g")
1572: (lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
1573: (match_operand:SI 2 "general_operand" "g")))]
1574: ""
1575: "
1576: {
1577: if (GET_CODE (operands[2]) != CONST_INT)
1578: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1579: }")
1580:
1581: (define_insn ""
1582: [(set (match_operand:SI 0 "general_operand" "=g")
1583: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1584: (match_operand:SI 2 "immediate_operand" "i")))]
1585: ""
1586: "lshd %$%n2,%0")
1587:
1588: (define_insn ""
1589: [(set (match_operand:SI 0 "general_operand" "=g")
1590: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1591: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1592: ""
1593: "lshd %2,%0")
1594:
1595: (define_expand "lshrhi3"
1596: [(set (match_operand:HI 0 "general_operand" "=g")
1597: (lshiftrt:HI (match_operand:HI 1 "general_operand" "g")
1598: (match_operand:SI 2 "general_operand" "g")))]
1599: ""
1600: "
1601: {
1602: if (GET_CODE (operands[2]) != CONST_INT)
1603: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1604: }")
1605:
1606: (define_insn ""
1607: [(set (match_operand:HI 0 "general_operand" "=g")
1608: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1609: (match_operand:SI 2 "immediate_operand" "i")))]
1610: ""
1611: "lshw %$%n2,%0")
1612:
1613: (define_insn ""
1614: [(set (match_operand:HI 0 "general_operand" "=g")
1615: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1616: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1617: ""
1618: "lshw %2,%0")
1619:
1620: (define_expand "lshrqi3"
1621: [(set (match_operand:QI 0 "general_operand" "=g")
1622: (lshiftrt:QI (match_operand:QI 1 "general_operand" "g")
1623: (match_operand:SI 2 "general_operand" "g")))]
1624: ""
1625: "
1626: {
1627: if (GET_CODE (operands[2]) != CONST_INT)
1628: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1629: }")
1630:
1631: (define_insn ""
1632: [(set (match_operand:QI 0 "general_operand" "=g")
1633: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1634: (match_operand:SI 2 "immediate_operand" "i")))]
1635: ""
1636: "lshb %$%n2,%0")
1637:
1638: (define_insn ""
1639: [(set (match_operand:QI 0 "general_operand" "=g")
1640: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1641: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1642: ""
1643: "lshb %2,%0")
1644:
1645: ;; Rotate instructions
1646:
1647: (define_insn "rotlsi3"
1648: [(set (match_operand:SI 0 "general_operand" "=g")
1649: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1650: (match_operand:SI 2 "general_operand" "rmn")))]
1651: ""
1652: "rotd %2,%0")
1653:
1654: (define_insn "rotlhi3"
1655: [(set (match_operand:HI 0 "general_operand" "=g")
1656: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1657: (match_operand:SI 2 "general_operand" "rmn")))]
1658: ""
1659: "rotw %2,%0")
1660:
1661: (define_insn "rotlqi3"
1662: [(set (match_operand:QI 0 "general_operand" "=g")
1663: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1664: (match_operand:SI 2 "general_operand" "rmn")))]
1665: ""
1666: "rotb %2,%0")
1667:
1668: ;; Right rotate on the 32k works by negating the shift count.
1669: (define_expand "rotrsi3"
1670: [(set (match_operand:SI 0 "general_operand" "=g")
1671: (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1672: (match_operand:SI 2 "general_operand" "g")))]
1673: ""
1674: "
1675: {
1676: if (GET_CODE (operands[2]) != CONST_INT)
1677: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1678: }")
1679:
1680: (define_insn ""
1681: [(set (match_operand:SI 0 "general_operand" "=g")
1682: (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1683: (match_operand:SI 2 "immediate_operand" "i")))]
1684: ""
1685: "rotd %$%n2,%0")
1686:
1687: (define_insn ""
1688: [(set (match_operand:SI 0 "general_operand" "=g")
1689: (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1690: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1691: ""
1692: "rotd %2,%0")
1693:
1694: (define_expand "rotrhi3"
1695: [(set (match_operand:HI 0 "general_operand" "=g")
1696: (rotatert:HI (match_operand:HI 1 "general_operand" "g")
1697: (match_operand:SI 2 "general_operand" "g")))]
1698: ""
1699: "
1700: {
1701: if (GET_CODE (operands[2]) != CONST_INT)
1702: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1703: }")
1704:
1705: (define_insn ""
1706: [(set (match_operand:HI 0 "general_operand" "=g")
1707: (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1708: (match_operand:SI 2 "immediate_operand" "i")))]
1709: ""
1710: "rotw %$%n2,%0")
1711:
1712: (define_insn ""
1713: [(set (match_operand:HI 0 "general_operand" "=g")
1714: (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1715: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1716: ""
1717: "rotw %2,%0")
1718:
1719: (define_expand "rotrqi3"
1720: [(set (match_operand:QI 0 "general_operand" "=g")
1721: (rotatert:QI (match_operand:QI 1 "general_operand" "g")
1722: (match_operand:SI 2 "general_operand" "g")))]
1723: ""
1724: "
1725: {
1726: if (GET_CODE (operands[2]) != CONST_INT)
1727: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1728: }")
1729:
1730: (define_insn ""
1731: [(set (match_operand:QI 0 "general_operand" "=g")
1732: (rotatert:QI (match_operand:QI 1 "general_operand" "0")
1733: (match_operand:SI 2 "immediate_operand" "i")))]
1734: ""
1735: "rotb %$%n2,%0")
1736:
1737: (define_insn ""
1738: [(set (match_operand:QI 0 "general_operand" "=g")
1739: (rotatert:QI (match_operand:QI 1 "general_operand" "0")
1740: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1741: ""
1742: "rotb %2,%0")
1743:
1744: ;;- load or push effective address
1745: ;; These come after the move, add, and multiply patterns
1746: ;; because we don't want pushl $1 turned into pushad 1.
1747:
1748: (define_insn ""
1749: [(set (match_operand:SI 0 "general_operand" "=g<")
1750: (match_operand:QI 1 "address_operand" "p"))]
1751: ""
1752: "*
1753: {
1754: if (REG_P (operands[0])
1755: && GET_CODE (operands[1]) == MULT
1756: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
1757: && (INTVAL (XEXP (operands[1], 1)) == 2
1758: || INTVAL (XEXP (operands[1], 1)) == 4))
1759: {
1760: rtx xoperands[3];
1761: xoperands[0] = operands[0];
1762: xoperands[1] = XEXP (operands[1], 0);
1763: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
1764: return output_shift_insn (xoperands);
1765: }
1766: return \"addr %a1,%0\";
1767: }")
1768:
1769: ;;; Index insns. These are about the same speed as multiply-add counterparts.
1770: ;;; but slower then using power-of-2 shifts if we can use them
1771: ;
1772: ;(define_insn ""
1773: ; [(set (match_operand:SI 0 "register_operand" "=r")
1774: ; (plus:SI (match_operand:SI 1 "general_operand" "rmn")
1775: ; (mult:SI (match_operand:SI 2 "register_operand" "0")
1776: ; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))]
1777: ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
1778: ; "indexd %0,%3,%1")
1779: ;
1780: ;(define_insn ""
1781: ; [(set (match_operand:SI 0 "register_operand" "=r")
1782: ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
1783: ; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1)))
1784: ; (match_operand:SI 3 "general_operand" "rmn")))]
1785: ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
1786: ; "indexd %0,%2,%3")
1787:
1788: ;; Set, Clear, and Invert bit
1789:
1790: (define_insn ""
1791: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
1792: (const_int 1)
1793: (match_operand:SI 1 "general_operand" "rmn"))
1794: (const_int 1))]
1795: ""
1796: "sbitd %1,%0")
1797:
1798: (define_insn ""
1799: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
1800: (const_int 1)
1801: (match_operand:SI 1 "general_operand" "rmn"))
1802: (const_int 0))]
1803: ""
1804: "cbitd %1,%0")
1805:
1806: (define_insn ""
1807: [(set (match_operand:SI 0 "general_operand" "+g")
1808: (xor:SI (ashift:SI (const_int 1)
1809: (match_operand:SI 1 "general_operand" "rmn"))
1810: (match_dup 0)))]
1811: ""
1812: "ibitd %1,%0")
1813:
1814: (define_insn ""
1815: [(set (match_operand:QI 0 "general_operand" "=g")
1816: (xor:QI (subreg:QI
1817: (ashift:SI (const_int 1)
1818: (match_operand:QI 1 "general_operand" "rmn")) 0)
1819: (match_dup 0)))]
1820: ""
1821: "ibitb %1,%0")
1822:
1823: ;; Recognize jbs and jbc instructions.
1824:
1825: (define_insn ""
1826: [(set (cc0)
1827: (zero_extract (match_operand:SI 0 "general_operand" "rm")
1828: (const_int 1)
1829: (match_operand:SI 1 "general_operand" "g")))]
1830: ""
1831: "*
1832: { cc_status.flags = CC_Z_IN_F;
1833: return \"tbitd %1,%0\";
1834: }")
1835:
1836: ;; extract(base, width, offset)
1837: ;; Signed bitfield extraction is not supported in hardware on the
1838: ;; NS 32032. It is therefore better to let GCC figure out a
1839: ;; good strategy for generating the proper instruction sequence
1840: ;; and represent it as rtl.
1841:
1842: ;; Optimize the case of extracting a byte or word from a register.
1843: ;; Otherwise we must load a register with the offset of the
1844: ;; chunk we want, and perform an extract insn (each of which
1845: ;; is very expensive). Since we use the stack to do our bit-twiddling
1846: ;; we cannot use it for a destination. Perhaps things are fast
1847: ;; enough on the 32532 that such hacks are not needed.
1848:
1849: (define_insn ""
1850: [(set (match_operand:SI 0 "general_operand" "=ro")
1851: (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1852: (match_operand:SI 2 "const_int_operand" "i")
1853: (match_operand:SI 3 "const_int_operand" "i")))]
1854: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1855: && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
1856: "*
1857: {
1858: output_asm_insn (\"movd %1,tos\", operands);
1859: if (INTVAL (operands[2]) == 16)
1860: {
1861: if (INTVAL (operands[3]) == 8)
1862: output_asm_insn (\"movzwd 1(sp),%0\", operands);
1863: else
1864: output_asm_insn (\"movzwd 2(sp),%0\", operands);
1865: }
1866: else
1867: {
1868: if (INTVAL (operands[3]) == 8)
1869: output_asm_insn (\"movzbd 1(sp),%0\", operands);
1870: else if (INTVAL (operands[3]) == 16)
1871: output_asm_insn (\"movzbd 2(sp),%0\", operands);
1872: else
1873: output_asm_insn (\"movzbd 3(sp),%0\", operands);
1874: }
1875: if (TARGET_32532 || TARGET_32332)
1876: return \"cmpqd %$0,tos\";
1877: else
1878: return \"adjspb %$-4\";
1879: }")
1880:
1881: (define_insn ""
1882: [(set (match_operand:SI 0 "general_operand" "=g<")
1883: (zero_extract:SI (match_operand:SI 1 "register_operand" "g")
1884: (match_operand:SI 2 "const_int_operand" "i")
1885: (match_operand:SI 3 "general_operand" "rK")))]
1886: ""
1887: "*
1888: { if (GET_CODE (operands[3]) == CONST_INT)
1889: return \"extsd %1,%0,%3,%2\";
1890: else return \"extd %3,%1,%0,%2\";
1891: }")
1892:
1893: (define_insn "extzv"
1894: [(set (match_operand:SI 0 "general_operand" "=g<")
1895: (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
1896: (match_operand:SI 2 "const_int_operand" "i")
1897: (match_operand:SI 3 "general_operand" "rK")))]
1898: ""
1899: "*
1900: { if (GET_CODE (operands[3]) == CONST_INT)
1901: return \"extsd %1,%0,%3,%2\";
1902: else return \"extd %3,%1,%0,%2\";
1903: }")
1904:
1905: (define_insn ""
1906: [(set (zero_extract:SI (match_operand:SI 0 "memory_operand" "+o")
1907: (match_operand:SI 1 "const_int_operand" "i")
1908: (match_operand:SI 2 "general_operand" "rn"))
1909: (match_operand:SI 3 "general_operand" "rm"))]
1910: ""
1911: "*
1912: { if (GET_CODE (operands[2]) == CONST_INT)
1913: {
1914: if (INTVAL (operands[2]) >= 8)
1915: {
1916: operands[0] = adj_offsettable_operand (operands[0],
1917: INTVAL (operands[2]) / 8);
1918: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
1919: }
1920: if (INTVAL (operands[1]) <= 8)
1921: return \"inssb %3,%0,%2,%1\";
1922: else if (INTVAL (operands[1]) <= 16)
1923: return \"inssw %3,%0,%2,%1\";
1924: else
1925: return \"inssd %3,%0,%2,%1\";
1926: }
1927: return \"insd %2,%3,%0,%1\";
1928: }")
1929:
1930: (define_insn ""
1931: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1932: (match_operand:SI 1 "const_int_operand" "i")
1933: (match_operand:SI 2 "general_operand" "rK"))
1934: (match_operand:SI 3 "general_operand" "rm"))]
1935: ""
1936: "*
1937: { if (GET_CODE (operands[2]) == CONST_INT)
1938: if (INTVAL (operands[1]) <= 8)
1939: return \"inssb %3,%0,%2,%1\";
1940: else if (INTVAL (operands[1]) <= 16)
1941: return \"inssw %3,%0,%2,%1\";
1942: else
1943: return \"inssd %3,%0,%2,%1\";
1944: return \"insd %2,%3,%0,%1\";
1945: }")
1946:
1947: (define_insn "insv"
1948: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
1949: (match_operand:SI 1 "const_int_operand" "i")
1950: (match_operand:SI 2 "general_operand" "rK"))
1951: (match_operand:SI 3 "general_operand" "rm"))]
1952: ""
1953: "*
1954: { if (GET_CODE (operands[2]) == CONST_INT)
1955: if (INTVAL (operands[1]) <= 8)
1956: return \"inssb %3,%0,%2,%1\";
1957: else if (INTVAL (operands[1]) <= 16)
1958: return \"inssw %3,%0,%2,%1\";
1959: else
1960: return \"inssd %3,%0,%2,%1\";
1961: return \"insd %2,%3,%0,%1\";
1962: }")
1963:
1964:
1965: (define_insn "jump"
1966: [(set (pc)
1967: (label_ref (match_operand 0 "" "")))]
1968: ""
1969: "br %l0")
1970:
1971: (define_insn "beq"
1972: [(set (pc)
1973: (if_then_else (eq (cc0)
1974: (const_int 0))
1975: (label_ref (match_operand 0 "" ""))
1976: (pc)))]
1977: ""
1978: "*
1979: { if (cc_prev_status.flags & CC_Z_IN_F)
1980: return \"bfc %l0\";
1981: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1982: return \"bfs %l0\";
1983: else return \"beq %l0\";
1984: }")
1985:
1986: (define_insn "bne"
1987: [(set (pc)
1988: (if_then_else (ne (cc0)
1989: (const_int 0))
1990: (label_ref (match_operand 0 "" ""))
1991: (pc)))]
1992: ""
1993: "*
1994: { if (cc_prev_status.flags & CC_Z_IN_F)
1995: return \"bfs %l0\";
1996: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1997: return \"bfc %l0\";
1998: else return \"bne %l0\";
1999: }")
2000:
2001: (define_insn "bgt"
2002: [(set (pc)
2003: (if_then_else (gt (cc0)
2004: (const_int 0))
2005: (label_ref (match_operand 0 "" ""))
2006: (pc)))]
2007: ""
2008: "bgt %l0")
2009:
2010: (define_insn "bgtu"
2011: [(set (pc)
2012: (if_then_else (gtu (cc0)
2013: (const_int 0))
2014: (label_ref (match_operand 0 "" ""))
2015: (pc)))]
2016: ""
2017: "bhi %l0")
2018:
2019: (define_insn "blt"
2020: [(set (pc)
2021: (if_then_else (lt (cc0)
2022: (const_int 0))
2023: (label_ref (match_operand 0 "" ""))
2024: (pc)))]
2025: ""
2026: "blt %l0")
2027:
2028: (define_insn "bltu"
2029: [(set (pc)
2030: (if_then_else (ltu (cc0)
2031: (const_int 0))
2032: (label_ref (match_operand 0 "" ""))
2033: (pc)))]
2034: ""
2035: "blo %l0")
2036:
2037: (define_insn "bge"
2038: [(set (pc)
2039: (if_then_else (ge (cc0)
2040: (const_int 0))
2041: (label_ref (match_operand 0 "" ""))
2042: (pc)))]
2043: ""
2044: "bge %l0")
2045:
2046: (define_insn "bgeu"
2047: [(set (pc)
2048: (if_then_else (geu (cc0)
2049: (const_int 0))
2050: (label_ref (match_operand 0 "" ""))
2051: (pc)))]
2052: ""
2053: "bhs %l0")
2054:
2055: (define_insn "ble"
2056: [(set (pc)
2057: (if_then_else (le (cc0)
2058: (const_int 0))
2059: (label_ref (match_operand 0 "" ""))
2060: (pc)))]
2061: ""
2062: "ble %l0")
2063:
2064: (define_insn "bleu"
2065: [(set (pc)
2066: (if_then_else (leu (cc0)
2067: (const_int 0))
2068: (label_ref (match_operand 0 "" ""))
2069: (pc)))]
2070: ""
2071: "bls %l0")
2072:
2073: (define_insn ""
2074: [(set (pc)
2075: (if_then_else (eq (cc0)
2076: (const_int 0))
2077: (pc)
2078: (label_ref (match_operand 0 "" ""))))]
2079: ""
2080: "*
2081: { if (cc_prev_status.flags & CC_Z_IN_F)
2082: return \"bfs %l0\";
2083: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2084: return \"bfc %l0\";
2085: else return \"bne %l0\";
2086: }")
2087:
2088: (define_insn ""
2089: [(set (pc)
2090: (if_then_else (ne (cc0)
2091: (const_int 0))
2092: (pc)
2093: (label_ref (match_operand 0 "" ""))))]
2094: ""
2095: "*
2096: { if (cc_prev_status.flags & CC_Z_IN_F)
2097: return \"bfc %l0\";
2098: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2099: return \"bfs %l0\";
2100: else return \"beq %l0\";
2101: }")
2102:
2103: (define_insn ""
2104: [(set (pc)
2105: (if_then_else (gt (cc0)
2106: (const_int 0))
2107: (pc)
2108: (label_ref (match_operand 0 "" ""))))]
2109: ""
2110: "ble %l0")
2111:
2112: (define_insn ""
2113: [(set (pc)
2114: (if_then_else (gtu (cc0)
2115: (const_int 0))
2116: (pc)
2117: (label_ref (match_operand 0 "" ""))))]
2118: ""
2119: "bls %l0")
2120:
2121: (define_insn ""
2122: [(set (pc)
2123: (if_then_else (lt (cc0)
2124: (const_int 0))
2125: (pc)
2126: (label_ref (match_operand 0 "" ""))))]
2127: ""
2128: "bge %l0")
2129:
2130: (define_insn ""
2131: [(set (pc)
2132: (if_then_else (ltu (cc0)
2133: (const_int 0))
2134: (pc)
2135: (label_ref (match_operand 0 "" ""))))]
2136: ""
2137: "bhs %l0")
2138:
2139: (define_insn ""
2140: [(set (pc)
2141: (if_then_else (ge (cc0)
2142: (const_int 0))
2143: (pc)
2144: (label_ref (match_operand 0 "" ""))))]
2145: ""
2146: "blt %l0")
2147:
2148: (define_insn ""
2149: [(set (pc)
2150: (if_then_else (geu (cc0)
2151: (const_int 0))
2152: (pc)
2153: (label_ref (match_operand 0 "" ""))))]
2154: ""
2155: "blo %l0")
2156:
2157: (define_insn ""
2158: [(set (pc)
2159: (if_then_else (le (cc0)
2160: (const_int 0))
2161: (pc)
2162: (label_ref (match_operand 0 "" ""))))]
2163: ""
2164: "bgt %l0")
2165:
2166: (define_insn ""
2167: [(set (pc)
2168: (if_then_else (leu (cc0)
2169: (const_int 0))
2170: (pc)
2171: (label_ref (match_operand 0 "" ""))))]
2172: ""
2173: "bhi %l0")
2174:
2175: ;; Subtract-and-jump and Add-and-jump insns.
2176: ;; These can actually be used for adding numbers in the range -8 to 7
2177:
2178: (define_insn ""
2179: [(set (pc)
2180: (if_then_else
2181: (ne (match_operand:SI 0 "general_operand" "+g")
2182: (match_operand:SI 1 "const_int_operand" "i"))
2183: (label_ref (match_operand 2 "" ""))
2184: (pc)))
2185: (set (match_dup 0)
2186: (minus:SI (match_dup 0)
2187: (match_dup 1)))]
2188: "INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2189: "acbd %$%n1,%0,%l2")
2190:
2191: (define_insn ""
2192: [(set (pc)
2193: (if_then_else
2194: (ne (match_operand:SI 0 "general_operand" "+g")
2195: (match_operand:SI 1 "const_int_operand" "i"))
2196: (label_ref (match_operand 2 "" ""))
2197: (pc)))
2198: (set (match_dup 0)
2199: (plus:SI (match_dup 0)
2200: (match_operand:SI 3 "const_int_operand" "i")))]
2201: "INTVAL (operands[1]) == - INTVAL (operands[3])
2202: && INTVAL (operands[3]) >= -8 && INTVAL (operands[3]) < 8"
2203: "acbd %3,%0,%l2")
2204:
2205: (define_insn "call"
2206: [(call (match_operand:QI 0 "memory_operand" "m")
2207: (match_operand:QI 1 "general_operand" "g"))]
2208: ""
2209: "*
2210: {
2211: #ifndef JSR_ALWAYS
2212: if (GET_CODE (operands[0]) == MEM)
2213: {
2214: rtx temp = XEXP (operands[0], 0);
2215: if (CONSTANT_ADDRESS_P (temp))
2216: {
2217: #ifdef ENCORE_ASM
2218: return \"bsr %?%0\";
2219: #else
2220: #ifdef CALL_MEMREF_IMPLICIT
2221: operands[0] = temp;
2222: return \"bsr %0\";
2223: #else
2224: #ifdef GNX_V3
2225: return \"bsr %0\";
2226: #else
2227: return \"bsr %?%a0\";
2228: #endif
2229: #endif
2230: #endif
2231: }
2232: if (GET_CODE (XEXP (operands[0], 0)) == REG)
2233: #if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT)
2234: return \"jsr %0\";
2235: #else
2236: return \"jsr %a0\";
2237: #endif
2238: }
2239: #endif /* not JSR_ALWAYS */
2240: return \"jsr %0\";
2241: }")
2242:
2243: (define_insn "call_value"
2244: [(set (match_operand 0 "" "=rf")
2245: (call (match_operand:QI 1 "memory_operand" "m")
2246: (match_operand:QI 2 "general_operand" "g")))]
2247: ""
2248: "*
2249: {
2250: #ifndef JSR_ALWAYS
2251: if (GET_CODE (operands[1]) == MEM)
2252: {
2253: rtx temp = XEXP (operands[1], 0);
2254: if (CONSTANT_ADDRESS_P (temp))
2255: {
2256: #ifdef ENCORE_ASM
2257: return \"bsr %?%1\";
2258: #else
2259: #ifdef CALL_MEMREF_IMPLICIT
2260: operands[1] = temp;
2261: return \"bsr %1\";
2262: #else
2263: #ifdef GNX_V3
2264: return \"bsr %1\";
2265: #else
2266: return \"bsr %?%a1\";
2267: #endif
2268: #endif
2269: #endif
2270: }
2271: if (GET_CODE (XEXP (operands[1], 0)) == REG)
2272: #if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT)
2273: return \"jsr %1\";
2274: #else
2275: return \"jsr %a1\";
2276: #endif
2277: }
2278: #endif /* not JSR_ALWAYS */
2279: return \"jsr %1\";
2280: }")
2281:
2282: ;; Call subroutine returning any type.
2283:
2284: (define_expand "untyped_call"
2285: [(parallel [(call (match_operand 0 "" "")
2286: (const_int 0))
2287: (match_operand 1 "" "")
2288: (match_operand 2 "" "")])]
2289: ""
2290: "
2291: {
2292: int i;
2293:
2294: emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
2295:
2296: for (i = 0; i < XVECLEN (operands[2], 0); i++)
2297: {
2298: rtx set = XVECEXP (operands[2], 0, i);
2299: emit_move_insn (SET_DEST (set), SET_SRC (set));
2300: }
2301:
2302: /* The optimizer does not know that the call sets the function value
2303: registers we stored in the result block. We avoid problems by
2304: claiming that all hard registers are used and clobbered at this
2305: point. */
2306: emit_insn (gen_blockage ());
2307:
2308: DONE;
2309: }")
2310:
2311: ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2312: ;; all of memory. This blocks insns from being moved across this point.
2313:
2314: (define_insn "blockage"
2315: [(unspec_volatile [(const_int 0)] 0)]
2316: ""
2317: "")
2318:
2319: (define_insn "return"
2320: [(return)]
2321: "0"
2322: "ret 0")
2323:
2324: (define_insn "abssf2"
2325: [(set (match_operand:SF 0 "general_operand" "=fm<")
2326: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2327: "TARGET_32081"
2328: "absf %1,%0")
2329:
2330: (define_insn "absdf2"
2331: [(set (match_operand:DF 0 "general_operand" "=fm<")
2332: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
2333: "TARGET_32081"
2334: "absl %1,%0")
2335:
2336: (define_insn "abssi2"
2337: [(set (match_operand:SI 0 "general_operand" "=g<")
2338: (abs:SI (match_operand:SI 1 "general_operand" "rmn")))]
2339: ""
2340: "absd %1,%0")
2341:
2342: (define_insn "abshi2"
2343: [(set (match_operand:HI 0 "general_operand" "=g<")
2344: (abs:HI (match_operand:HI 1 "general_operand" "g")))]
2345: ""
2346: "absw %1,%0")
2347:
2348: (define_insn "absqi2"
2349: [(set (match_operand:QI 0 "general_operand" "=g<")
2350: (abs:QI (match_operand:QI 1 "general_operand" "g")))]
2351: ""
2352: "absb %1,%0")
2353:
2354: (define_insn "nop"
2355: [(const_int 0)]
2356: ""
2357: "nop")
2358:
2359: (define_insn "indirect_jump"
2360: [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
2361: ""
2362: "jump %0")
2363:
2364: (define_insn "tablejump"
2365: [(set (pc)
2366: (plus:SI (pc) (match_operand:SI 0 "general_operand" "g")))
2367: (use (label_ref (match_operand 1 "" "")))]
2368: ""
2369: "*
2370: {
2371: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
2372: CODE_LABEL_NUMBER (operands[1]));
2373: return \"cased %0\";
2374: }")
2375:
2376: ;; Scondi instructions
2377: (define_insn "seq"
2378: [(set (match_operand:SI 0 "general_operand" "=g<")
2379: (eq:SI (cc0) (const_int 0)))]
2380: ""
2381: "*
2382: { if (cc_prev_status.flags & CC_Z_IN_F)
2383: return \"sfcd %0\";
2384: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2385: return \"sfsd %0\";
2386: else return \"seqd %0\";
2387: }")
2388:
2389: (define_insn ""
2390: [(set (match_operand:HI 0 "general_operand" "=g<")
2391: (eq:HI (cc0) (const_int 0)))]
2392: ""
2393: "*
2394: { if (cc_prev_status.flags & CC_Z_IN_F)
2395: return \"sfcw %0\";
2396: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2397: return \"sfsw %0\";
2398: else return \"seqw %0\";
2399: }")
2400:
2401: (define_insn ""
2402: [(set (match_operand:QI 0 "general_operand" "=g<")
2403: (eq:QI (cc0) (const_int 0)))]
2404: ""
2405: "*
2406: { if (cc_prev_status.flags & CC_Z_IN_F)
2407: return \"sfcb %0\";
2408: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2409: return \"sfsb %0\";
2410: else return \"seqb %0\";
2411: }")
2412:
2413: (define_insn "sne"
2414: [(set (match_operand:SI 0 "general_operand" "=g<")
2415: (ne:SI (cc0) (const_int 0)))]
2416: ""
2417: "*
2418: { if (cc_prev_status.flags & CC_Z_IN_F)
2419: return \"sfsd %0\";
2420: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2421: return \"sfcd %0\";
2422: else return \"sned %0\";
2423: }")
2424:
2425: (define_insn ""
2426: [(set (match_operand:HI 0 "general_operand" "=g<")
2427: (ne:HI (cc0) (const_int 0)))]
2428: ""
2429: "*
2430: { if (cc_prev_status.flags & CC_Z_IN_F)
2431: return \"sfsw %0\";
2432: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2433: return \"sfcw %0\";
2434: else return \"snew %0\";
2435: }")
2436:
2437: (define_insn ""
2438: [(set (match_operand:QI 0 "general_operand" "=g<")
2439: (ne:QI (cc0) (const_int 0)))]
2440: ""
2441: "*
2442: { if (cc_prev_status.flags & CC_Z_IN_F)
2443: return \"sfsb %0\";
2444: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2445: return \"sfcb %0\";
2446: else return \"sneb %0\";
2447: }")
2448:
2449: (define_insn "sgt"
2450: [(set (match_operand:SI 0 "general_operand" "=g<")
2451: (gt:SI (cc0) (const_int 0)))]
2452: ""
2453: "sgtd %0")
2454:
2455: (define_insn ""
2456: [(set (match_operand:HI 0 "general_operand" "=g<")
2457: (gt:HI (cc0) (const_int 0)))]
2458: ""
2459: "sgtw %0")
2460:
2461: (define_insn ""
2462: [(set (match_operand:QI 0 "general_operand" "=g<")
2463: (gt:QI (cc0) (const_int 0)))]
2464: ""
2465: "sgtb %0")
2466:
2467: (define_insn "sgtu"
2468: [(set (match_operand:SI 0 "general_operand" "=g<")
2469: (gtu:SI (cc0) (const_int 0)))]
2470: ""
2471: "shid %0")
2472:
2473: (define_insn ""
2474: [(set (match_operand:HI 0 "general_operand" "=g<")
2475: (gtu:HI (cc0) (const_int 0)))]
2476: ""
2477: "shiw %0")
2478:
2479: (define_insn ""
2480: [(set (match_operand:QI 0 "general_operand" "=g<")
2481: (gtu:QI (cc0) (const_int 0)))]
2482: ""
2483: "shib %0")
2484:
2485: (define_insn "slt"
2486: [(set (match_operand:SI 0 "general_operand" "=g<")
2487: (lt:SI (cc0) (const_int 0)))]
2488: ""
2489: "sltd %0")
2490:
2491: (define_insn ""
2492: [(set (match_operand:HI 0 "general_operand" "=g<")
2493: (lt:HI (cc0) (const_int 0)))]
2494: ""
2495: "sltw %0")
2496:
2497: (define_insn ""
2498: [(set (match_operand:QI 0 "general_operand" "=g<")
2499: (lt:QI (cc0) (const_int 0)))]
2500: ""
2501: "sltb %0")
2502:
2503: (define_insn "sltu"
2504: [(set (match_operand:SI 0 "general_operand" "=g<")
2505: (ltu:SI (cc0) (const_int 0)))]
2506: ""
2507: "slod %0")
2508:
2509: (define_insn ""
2510: [(set (match_operand:HI 0 "general_operand" "=g<")
2511: (ltu:HI (cc0) (const_int 0)))]
2512: ""
2513: "slow %0")
2514:
2515: (define_insn ""
2516: [(set (match_operand:QI 0 "general_operand" "=g<")
2517: (ltu:QI (cc0) (const_int 0)))]
2518: ""
2519: "slob %0")
2520:
2521: (define_insn "sge"
2522: [(set (match_operand:SI 0 "general_operand" "=g<")
2523: (ge:SI (cc0) (const_int 0)))]
2524: ""
2525: "sged %0")
2526:
2527: (define_insn ""
2528: [(set (match_operand:HI 0 "general_operand" "=g<")
2529: (ge:HI (cc0) (const_int 0)))]
2530: ""
2531: "sgew %0")
2532:
2533: (define_insn ""
2534: [(set (match_operand:QI 0 "general_operand" "=g<")
2535: (ge:QI (cc0) (const_int 0)))]
2536: ""
2537: "sgeb %0")
2538:
2539: (define_insn "sgeu"
2540: [(set (match_operand:SI 0 "general_operand" "=g<")
2541: (geu:SI (cc0) (const_int 0)))]
2542: ""
2543: "shsd %0")
2544:
2545: (define_insn ""
2546: [(set (match_operand:HI 0 "general_operand" "=g<")
2547: (geu:HI (cc0) (const_int 0)))]
2548: ""
2549: "shsw %0")
2550:
2551: (define_insn ""
2552: [(set (match_operand:QI 0 "general_operand" "=g<")
2553: (geu:QI (cc0) (const_int 0)))]
2554: ""
2555: "shsb %0")
2556:
2557: (define_insn "sle"
2558: [(set (match_operand:SI 0 "general_operand" "=g<")
2559: (le:SI (cc0) (const_int 0)))]
2560: ""
2561: "sled %0")
2562:
2563: (define_insn ""
2564: [(set (match_operand:HI 0 "general_operand" "=g<")
2565: (le:HI (cc0) (const_int 0)))]
2566: ""
2567: "slew %0")
2568:
2569: (define_insn ""
2570: [(set (match_operand:QI 0 "general_operand" "=g<")
2571: (le:QI (cc0) (const_int 0)))]
2572: ""
2573: "sleb %0")
2574:
2575: (define_insn "sleu"
2576: [(set (match_operand:SI 0 "general_operand" "=g<")
2577: (leu:SI (cc0) (const_int 0)))]
2578: ""
2579: "slsd %0")
2580:
2581: (define_insn ""
2582: [(set (match_operand:HI 0 "general_operand" "=g<")
2583: (leu:HI (cc0) (const_int 0)))]
2584: ""
2585: "slsw %0")
2586:
2587: (define_insn ""
2588: [(set (match_operand:QI 0 "general_operand" "=g<")
2589: (leu:QI (cc0) (const_int 0)))]
2590: ""
2591: "slsb %0")
2592:
2593: ;; Speed up stack adjust followed by a fullword fixedpoint push.
2594:
2595: (define_peephole
2596: [(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int 4)))
2597: (set (match_operand:SI 0 "push_operand" "=m")
2598: (match_operand:SI 1 "general_operand" "g"))]
2599: "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2600: "*
2601: {
2602: return \"movd %1,0(sp)\";
2603: }")
2604:
2605: ;; Speed up stack adjust followed by two fullword fixedpoint pushes.
2606:
2607: (define_peephole
2608: [(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int 8)))
2609: (set (match_operand:SI 0 "push_operand" "=m")
2610: (match_operand:SI 1 "general_operand" "g"))
2611: (set (match_operand:SI 2 "push_operand" "=m")
2612: (match_operand:SI 3 "general_operand" "g"))]
2613: "! reg_mentioned_p (stack_pointer_rtx, operands[1])
2614: && ! reg_mentioned_p (stack_pointer_rtx, operands[3])"
2615: "*
2616: {
2617: return \"movd %1,4(sp); movd %3,0(sp)\";
2618: }")
2619:
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.