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1.1 ! root 1: ;;- Machine description for IBM RISC System 6000 (POWER) for GNU C compiler ! 2: ;; Copyright (C) 1990, 1991, 1992, 1993 Free Software Foundation, Inc. ! 3: ;; Contributed by Richard Kenner ([email protected]) ! 4: ! 5: ;; This file is part of GNU CC. ! 6: ! 7: ;; GNU CC is free software; you can redistribute it and/or modify ! 8: ;; it under the terms of the GNU General Public License as published by ! 9: ;; the Free Software Foundation; either version 2, or (at your option) ! 10: ;; any later version. ! 11: ! 12: ;; GNU CC is distributed in the hope that it will be useful, ! 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ! 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 15: ;; GNU General Public License for more details. ! 16: ! 17: ;; You should have received a copy of the GNU General Public License ! 18: ;; along with GNU CC; see the file COPYING. If not, write to ! 19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! 20: ! 21: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ! 22: ! 23: ;; Define an insn type attribute. This is used in function unit delay ! 24: ;; computations. ! 25: (define_attr "type" "integer,load,fpload,imul,idiv,branch,compare,delayed_compare,fpcompare,mtlr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt" ! 26: (const_string "integer")) ! 27: ! 28: ;; Length (in bytes). ! 29: (define_attr "length" "" ! 30: (if_then_else (eq_attr "type" "branch") ! 31: (if_then_else (and (ge (minus (pc) (match_dup 0)) ! 32: (const_int -32768)) ! 33: (lt (minus (pc) (match_dup 0)) ! 34: (const_int 32767))) ! 35: (const_int 8) ! 36: (const_int 12)) ! 37: (const_int 4))) ! 38: ! 39: ;; Processor type -- this attribute must exactly match the processor_type ! 40: ;; enumeration in rs6000.h. ! 41: ! 42: (define_attr "cpu" "rios1,rios2,ppc601,ppc603,ppc604,ppc620" ! 43: (const (symbol_ref "rs6000_cpu_attr"))) ! 44: ! 45: ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY ! 46: ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) ! 47: ! 48: (define_function_unit "lsu" 1 0 ! 49: (and (eq_attr "type" "load") ! 50: (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620")) ! 51: 2 0) ! 52: ! 53: (define_function_unit "lsu" 1 0 ! 54: (and (eq_attr "type" "fpload") ! 55: (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620")) ! 56: 2 0) ! 57: ! 58: (define_function_unit "iu" 1 0 ! 59: (and (eq_attr "type" "load") ! 60: (eq_attr "cpu" "rios1,ppc601")) ! 61: 2 0) ! 62: ! 63: (define_function_unit "iu" 1 0 ! 64: (and (eq_attr "type" "fpload") ! 65: (eq_attr "cpu" "rios1,ppc601")) ! 66: 3 0) ! 67: ! 68: (define_function_unit "iu" 1 0 ! 69: (and (eq_attr "type" "imul") ! 70: (eq_attr "cpu" "rios1")) ! 71: 3 0) ! 72: ! 73: (define_function_unit "iu" 1 0 ! 74: (and (eq_attr "type" "imul") ! 75: (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620")) ! 76: 5 0) ! 77: ! 78: (define_function_unit "iu" 1 0 ! 79: (and (eq_attr "type" "idiv") ! 80: (eq_attr "cpu" "rios1")) ! 81: 19 0) ! 82: ! 83: (define_function_unit "iu" 1 0 ! 84: (and (eq_attr "type" "idiv") ! 85: (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620")) ! 86: 36 0) ! 87: ! 88: (define_function_unit "bpu" 1 0 ! 89: (eq_attr "type" "compare") ! 90: 4 0) ! 91: ! 92: (define_function_unit "bpu" 1 0 ! 93: (eq_attr "type" "delayed_compare") ! 94: 5 0) ! 95: ! 96: (define_function_unit "bpu" 1 0 ! 97: (and (eq_attr "type" "fpcompare") ! 98: (eq_attr "cpu" "rios1,rios2")) ! 99: 8 0) ! 100: ! 101: (define_function_unit "bpu" 1 0 ! 102: (and (eq_attr "type" "fpcompare") ! 103: (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620")) ! 104: 4 0) ! 105: ! 106: (define_function_unit "bpu" 1 0 ! 107: (and (eq_attr "type" "mtlr") ! 108: (eq_attr "cpu" "rios1,rios2")) ! 109: 5 0) ! 110: ! 111: (define_function_unit "bpu" 1 0 ! 112: (and (eq_attr "type" "mtlr") ! 113: (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620")) ! 114: 4 0) ! 115: ! 116: (define_function_unit "fpu" 1 0 ! 117: (and (eq_attr "type" "fp") ! 118: (eq_attr "cpu" "rios1")) ! 119: 2 0) ! 120: ! 121: (define_function_unit "fpu" 1 0 ! 122: (and (eq_attr "type" "fp") ! 123: (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620")) ! 124: 4 0) ! 125: ! 126: (define_function_unit "fpu" 1 0 ! 127: (and (eq_attr "type" "dmul") ! 128: (eq_attr "cpu" "rios1")) ! 129: 2 0) ! 130: ! 131: (define_function_unit "fpu" 1 0 ! 132: (and (eq_attr "type" "dmul") ! 133: (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620")) ! 134: 5 0) ! 135: ! 136: (define_function_unit "fpu" 1 0 ! 137: (and (eq_attr "type" "sdiv") ! 138: (eq_attr "cpu" "rios1")) ! 139: 19 0) ! 140: ! 141: (define_function_unit "fpu" 1 0 ! 142: (and (eq_attr "type" "sdiv") ! 143: (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620")) ! 144: 17 0) ! 145: ! 146: (define_function_unit "fpu" 1 0 ! 147: (and (eq_attr "type" "ddiv") ! 148: (eq_attr "cpu" "rios1")) ! 149: 19 0) ! 150: ! 151: (define_function_unit "fpu" 1 0 ! 152: (and (eq_attr "type" "ddiv") ! 153: (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620")) ! 154: 31 0) ! 155: ! 156: (define_function_unit "fpu" 1 0 ! 157: (and (eq_attr "type" "ssqrt") ! 158: (eq_attr "cpu" "ppc603,ppc604,ppc620")) ! 159: 31 0) ! 160: ! 161: (define_function_unit "fpu" 1 0 ! 162: (and (eq_attr "type" "dsqrt") ! 163: (eq_attr "cpu" "ppc603,ppc604,ppc620")) ! 164: 31 0) ! 165: ! 166: (define_function_unit "iu2" 2 0 ! 167: (and (eq_attr "type" "integer") ! 168: (eq_attr "cpu" "rios2")) ! 169: 1 0 ! 170: [(eq_attr "type" "imul,idiv")]) ! 171: ! 172: (define_function_unit "imuldiv" 1 0 ! 173: (and (eq_attr "type" "imul") ! 174: (eq_attr "cpu" "rios2")) ! 175: 2 0 ! 176: [(eq_attr "type" "integer")]) ! 177: ! 178: (define_function_unit "imuldiv" 1 0 ! 179: (and (eq_attr "type" "idiv") ! 180: (eq_attr "cpu" "rios2")) ! 181: 13 0 ! 182: [(eq_attr "type" "integer")]) ! 183: ! 184: (define_function_unit "fpu2" 2 0 ! 185: (and (eq_attr "type" "fp") ! 186: (eq_attr "cpu" "rios2")) ! 187: 2 0) ! 188: ! 189: (define_function_unit "fpu2" 2 0 ! 190: (and (eq_attr "type" "dmul") ! 191: (eq_attr "cpu" "rios2")) ! 192: 2 0) ! 193: ! 194: (define_function_unit "fpu2" 2 0 ! 195: (and (eq_attr "type" "sdiv") ! 196: (eq_attr "cpu" "rios2")) ! 197: 17 0) ! 198: ! 199: (define_function_unit "fpu2" 2 0 ! 200: (and (eq_attr "type" "ddiv") ! 201: (eq_attr "cpu" "rios2")) ! 202: 17 0) ! 203: ! 204: (define_function_unit "fpu2" 2 0 ! 205: (and (eq_attr "type" "ssqrt") ! 206: (eq_attr "cpu" "rios2")) ! 207: 26 0) ! 208: ! 209: (define_function_unit "fpu2" 2 0 ! 210: (and (eq_attr "type" "dsqrt") ! 211: (eq_attr "cpu" "rios2")) ! 212: 26 0) ! 213: ! 214: ;; Start with fixed-point load and store insns. Here we put only the more ! 215: ;; complex forms. Basic data transfer is done later. ! 216: ! 217: (define_expand "zero_extendqisi2" ! 218: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 219: (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] ! 220: "" ! 221: "") ! 222: ! 223: (define_insn "" ! 224: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 225: (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] ! 226: "" ! 227: "@ ! 228: lbz%U1%X1 %0,%1 ! 229: {rlinm|rlwinm} %0,%1,0,0xff" ! 230: [(set_attr "type" "load,*")]) ! 231: ! 232: (define_insn "" ! 233: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 234: (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) ! 235: (const_int 0))) ! 236: (clobber (match_scratch:SI 2 "=r"))] ! 237: "" ! 238: "{andil.|andi.} %2,%1,0xff" ! 239: [(set_attr "type" "compare")]) ! 240: ! 241: (define_insn "" ! 242: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 243: (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) ! 244: (const_int 0))) ! 245: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 246: (zero_extend:SI (match_dup 1)))] ! 247: "" ! 248: "{andil.|andi.} %0,%1,0xff" ! 249: [(set_attr "type" "compare")]) ! 250: ! 251: (define_expand "zero_extendqihi2" ! 252: [(set (match_operand:HI 0 "gpc_reg_operand" "") ! 253: (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] ! 254: "" ! 255: "") ! 256: ! 257: (define_insn "" ! 258: [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") ! 259: (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] ! 260: "" ! 261: "@ ! 262: lbz%U1%X1 %0,%1 ! 263: {rlinm|rlwinm} %0,%1,0,0xff" ! 264: [(set_attr "type" "load,*")]) ! 265: ! 266: (define_expand "zero_extendhisi2" ! 267: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 268: (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] ! 269: "" ! 270: "") ! 271: ! 272: (define_insn "" ! 273: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 274: (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] ! 275: "" ! 276: "@ ! 277: lhz%U1%X1 %0,%1 ! 278: {rlinm|rlwinm} %0,%1,0,0xffff" ! 279: [(set_attr "type" "load,*")]) ! 280: ! 281: (define_insn "" ! 282: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 283: (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) ! 284: (const_int 0))) ! 285: (clobber (match_scratch:SI 2 "=r"))] ! 286: "" ! 287: "{andil.|andi.} %2,%1,0xffff" ! 288: [(set_attr "type" "compare")]) ! 289: ! 290: (define_insn "" ! 291: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 292: (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) ! 293: (const_int 0))) ! 294: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 295: (zero_extend:SI (match_dup 1)))] ! 296: "" ! 297: "{andil.|andi.} %0,%1,0xffff" ! 298: [(set_attr "type" "compare")]) ! 299: ! 300: (define_expand "extendhisi2" ! 301: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 302: (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] ! 303: "" ! 304: "") ! 305: ! 306: (define_insn "" ! 307: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 308: (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] ! 309: "" ! 310: "@ ! 311: lha%U1%X1 %0,%1 ! 312: {exts|extsh} %0,%1" ! 313: [(set_attr "type" "load,*")]) ! 314: ! 315: (define_insn "" ! 316: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 317: (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) ! 318: (const_int 0))) ! 319: (clobber (match_scratch:SI 2 "=r"))] ! 320: "" ! 321: "{exts.|extsh.} %2,%1" ! 322: [(set_attr "type" "compare")]) ! 323: ! 324: (define_insn "" ! 325: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 326: (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) ! 327: (const_int 0))) ! 328: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 329: (sign_extend:SI (match_dup 1)))] ! 330: "" ! 331: "{exts.|extsh.} %0,%1" ! 332: [(set_attr "type" "compare")]) ! 333: ! 334: ;; Fixed-point arithmetic insns. ! 335: (define_insn "addsi3" ! 336: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 337: (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b") ! 338: (match_operand:SI 2 "add_operand" "rI,J")))] ! 339: "" ! 340: "@ ! 341: {a%I2|add%I2c} %0,%1,%2 ! 342: {cau|addis} %0,%1,%u2") ! 343: ! 344: (define_insn "" ! 345: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 346: (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 347: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 348: (const_int 0))) ! 349: (clobber (match_scratch:SI 3 "=r"))] ! 350: "" ! 351: "{a%I2.|add%I2c.} %3,%1,%2" ! 352: [(set_attr "type" "compare")]) ! 353: ! 354: (define_insn "" ! 355: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 356: (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 357: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 358: (const_int 0))) ! 359: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 360: (plus:SI (match_dup 1) (match_dup 2)))] ! 361: "" ! 362: "{a%I2.|add%I2c.} %0,%1,%2" ! 363: [(set_attr "type" "compare")]) ! 364: ! 365: ;; Split an add that we can't do in one insn into two insns, each of which ! 366: ;; does one 16-bit part. This is used by combine. Note that the low-order ! 367: ;; add should be last in case the result gets used in an address. ! 368: ! 369: (define_split ! 370: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 371: (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 372: (match_operand:SI 2 "non_add_cint_operand" "")))] ! 373: "" ! 374: [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) ! 375: (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] ! 376: " ! 377: { ! 378: int low = INTVAL (operands[2]) & 0xffff; ! 379: int high = (unsigned) INTVAL (operands[2]) >> 16; ! 380: ! 381: if (low & 0x8000) ! 382: high++, low |= 0xffff0000; ! 383: ! 384: operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16); ! 385: operands[4] = gen_rtx (CONST_INT, VOIDmode, low); ! 386: }") ! 387: ! 388: (define_expand "one_cmplsi2" ! 389: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 390: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] ! 391: "" ! 392: "") ! 393: ! 394: (define_insn "" ! 395: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 396: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] ! 397: "TARGET_POWER" ! 398: "{sfi|subfic} %0,%1,-1") ! 399: ! 400: (define_insn "" ! 401: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 402: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] ! 403: "! TARGET_POWER" ! 404: "nor %0,%1,%1") ! 405: ! 406: (define_insn "" ! 407: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 408: (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 409: (const_int 0))) ! 410: (clobber (match_scratch:SI 2 "=r"))] ! 411: "" ! 412: "nor. %2,%1,%1" ! 413: [(set_attr "type" "compare")]) ! 414: ! 415: (define_insn "" ! 416: [(set (match_operand:CC 2 "cc_reg_operand" "=-x") ! 417: (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 418: (const_int 0))) ! 419: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 420: (not:SI (match_dup 1)))] ! 421: "" ! 422: "nor. %0,%2,%1" ! 423: [(set_attr "type" "compare")]) ! 424: ! 425: (define_insn "" ! 426: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 427: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") ! 428: (match_operand:SI 2 "gpc_reg_operand" "r")))] ! 429: "" ! 430: "{sf%I1|subf%I1c} %0,%2,%1") ! 431: ! 432: (define_insn "" ! 433: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 434: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 435: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 436: (const_int 0))) ! 437: (clobber (match_scratch:SI 3 "=r"))] ! 438: "" ! 439: "{sf.|subfc.} %3,%2,%1" ! 440: [(set_attr "type" "compare")]) ! 441: ! 442: (define_insn "" ! 443: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 444: (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 445: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 446: (const_int 0))) ! 447: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 448: (minus:SI (match_dup 1) (match_dup 2)))] ! 449: "" ! 450: "{sf.|subfc.} %0,%2,%1" ! 451: [(set_attr "type" "compare")]) ! 452: ! 453: (define_expand "subsi3" ! 454: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 455: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") ! 456: (match_operand:SI 2 "reg_or_cint_operand" "")))] ! 457: "" ! 458: " ! 459: { ! 460: if (GET_CODE (operands[2]) == CONST_INT) ! 461: { ! 462: emit_insn (gen_addsi3 (operands[0], operands[1], ! 463: negate_rtx (SImode, operands[2]))); ! 464: DONE; ! 465: } ! 466: }") ! 467: ! 468: ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] ! 469: ;; instruction and some auxiliary computations. Then we just have a single ! 470: ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by ! 471: ;; combine. ! 472: ! 473: (define_expand "sminsi3" ! 474: [(set (match_dup 3) ! 475: (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 476: (match_operand:SI 2 "reg_or_short_operand" "")) ! 477: (const_int 0) ! 478: (minus:SI (match_dup 2) (match_dup 1)))) ! 479: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 480: (minus:SI (match_dup 2) (match_dup 3)))] ! 481: "TARGET_POWER" ! 482: " ! 483: { operands[3] = gen_reg_rtx (SImode); }") ! 484: ! 485: (define_split ! 486: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 487: (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 488: (match_operand:SI 2 "reg_or_short_operand" ""))) ! 489: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] ! 490: "TARGET_POWER" ! 491: [(set (match_dup 3) ! 492: (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) ! 493: (const_int 0) ! 494: (minus:SI (match_dup 2) (match_dup 1)))) ! 495: (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] ! 496: "") ! 497: ! 498: (define_expand "smaxsi3" ! 499: [(set (match_dup 3) ! 500: (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 501: (match_operand:SI 2 "reg_or_short_operand" "")) ! 502: (const_int 0) ! 503: (minus:SI (match_dup 2) (match_dup 1)))) ! 504: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 505: (plus:SI (match_dup 3) (match_dup 1)))] ! 506: "TARGET_POWER" ! 507: " ! 508: { operands[3] = gen_reg_rtx (SImode); }") ! 509: ! 510: (define_split ! 511: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 512: (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 513: (match_operand:SI 2 "reg_or_short_operand" ""))) ! 514: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] ! 515: "TARGET_POWER" ! 516: [(set (match_dup 3) ! 517: (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) ! 518: (const_int 0) ! 519: (minus:SI (match_dup 2) (match_dup 1)))) ! 520: (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] ! 521: "") ! 522: ! 523: (define_expand "uminsi3" ! 524: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 525: (const_int -2147483648))) ! 526: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") ! 527: (const_int -2147483648))) ! 528: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) ! 529: (const_int 0) ! 530: (minus:SI (match_dup 4) (match_dup 3)))) ! 531: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 532: (minus:SI (match_dup 2) (match_dup 3)))] ! 533: "TARGET_POWER" ! 534: " ! 535: { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") ! 536: ! 537: (define_expand "umaxsi3" ! 538: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 539: (const_int -2147483648))) ! 540: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") ! 541: (const_int -2147483648))) ! 542: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) ! 543: (const_int 0) ! 544: (minus:SI (match_dup 4) (match_dup 3)))) ! 545: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 546: (plus:SI (match_dup 3) (match_dup 1)))] ! 547: "TARGET_POWER" ! 548: " ! 549: { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") ! 550: ! 551: (define_insn "" ! 552: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 553: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") ! 554: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 555: (const_int 0) ! 556: (minus:SI (match_dup 2) (match_dup 1))))] ! 557: "TARGET_POWER" ! 558: "doz%I2 %0,%1,%2") ! 559: ! 560: (define_insn "" ! 561: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 562: (compare:CC ! 563: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") ! 564: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 565: (const_int 0) ! 566: (minus:SI (match_dup 2) (match_dup 1))) ! 567: (const_int 0))) ! 568: (clobber (match_scratch:SI 3 "=r"))] ! 569: "TARGET_POWER" ! 570: "doz%I2. %3,%1,%2" ! 571: [(set_attr "type" "delayed_compare")]) ! 572: ! 573: (define_insn "" ! 574: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 575: (compare:CC ! 576: (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") ! 577: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 578: (const_int 0) ! 579: (minus:SI (match_dup 2) (match_dup 1))) ! 580: (const_int 0))) ! 581: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 582: (if_then_else:SI (gt (match_dup 1) (match_dup 2)) ! 583: (const_int 0) ! 584: (minus:SI (match_dup 2) (match_dup 1))))] ! 585: "TARGET_POWER" ! 586: "doz%I2. %0,%1,%2" ! 587: [(set_attr "type" "delayed_compare")]) ! 588: ! 589: ;; We don't need abs with condition code because such comparisons should ! 590: ;; never be done. ! 591: (define_insn "abssi2" ! 592: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 593: (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] ! 594: "TARGET_POWER" ! 595: "abs %0,%1") ! 596: ! 597: (define_insn "" ! 598: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 599: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] ! 600: "TARGET_POWER" ! 601: "nabs %0,%1") ! 602: ! 603: (define_insn "negsi2" ! 604: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 605: (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] ! 606: "" ! 607: "neg %0,%1") ! 608: ! 609: (define_insn "" ! 610: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 611: (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 612: (const_int 0))) ! 613: (clobber (match_scratch:SI 2 "=r"))] ! 614: "" ! 615: "neg. %2,%1" ! 616: [(set_attr "type" "compare")]) ! 617: ! 618: (define_insn "" ! 619: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 620: (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 621: (const_int 0))) ! 622: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 623: (neg:SI (match_dup 1)))] ! 624: "" ! 625: "neg. %0,%1" ! 626: [(set_attr "type" "compare")]) ! 627: ! 628: (define_insn "ffssi2" ! 629: [(set (match_operand:SI 0 "register_operand" "=&r") ! 630: (ffs:SI (match_operand:SI 1 "register_operand" "r")))] ! 631: "" ! 632: "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32" ! 633: [(set_attr "length" "16")]) ! 634: ! 635: (define_expand "mulsi3" ! 636: [(use (match_operand:SI 0 "gpc_reg_operand" "")) ! 637: (use (match_operand:SI 1 "gpc_reg_operand" "")) ! 638: (use (match_operand:SI 2 "reg_or_short_operand" ""))] ! 639: "" ! 640: " ! 641: { ! 642: if (TARGET_POWER) ! 643: emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); ! 644: else ! 645: emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); ! 646: DONE; ! 647: }") ! 648: ! 649: (define_insn "mulsi3_mq" ! 650: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 651: (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") ! 652: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) ! 653: (clobber (match_scratch:SI 3 "=q,q"))] ! 654: "TARGET_POWER" ! 655: "@ ! 656: {muls|mullw} %0,%1,%2 ! 657: {muli|mulli} %0,%1,%2" ! 658: [(set_attr "type" "imul")]) ! 659: ! 660: (define_insn "mulsi3_no_mq" ! 661: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 662: (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") ! 663: (match_operand:SI 2 "reg_or_short_operand" "r,I")))] ! 664: "! TARGET_POWER" ! 665: "@ ! 666: mullw %0,%1,%2 ! 667: mulli %0,%1,%2" ! 668: [(set_attr "type" "imul")]) ! 669: ! 670: (define_insn "" ! 671: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 672: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 673: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 674: (const_int 0))) ! 675: (clobber (match_scratch:SI 3 "=r")) ! 676: (clobber (match_scratch:SI 4 "=q"))] ! 677: "TARGET_POWER" ! 678: "{muls.|mullw.} %3,%1,%2" ! 679: [(set_attr "type" "delayed_compare")]) ! 680: ! 681: (define_insn "" ! 682: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 683: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 684: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 685: (const_int 0))) ! 686: (clobber (match_scratch:SI 3 "=r"))] ! 687: "! TARGET_POWER" ! 688: "mullw. %3,%1,%2" ! 689: [(set_attr "type" "delayed_compare")]) ! 690: ! 691: (define_insn "" ! 692: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 693: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 694: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 695: (const_int 0))) ! 696: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 697: (mult:SI (match_dup 1) (match_dup 2))) ! 698: (clobber (match_scratch:SI 4 "=q"))] ! 699: "TARGET_POWER" ! 700: "{muls.|mullw.} %0,%1,%2" ! 701: [(set_attr "type" "delayed_compare")]) ! 702: ! 703: (define_insn "" ! 704: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 705: (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 706: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 707: (const_int 0))) ! 708: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 709: (mult:SI (match_dup 1) (match_dup 2)))] ! 710: "! TARGET_POWER" ! 711: "mullw. %0,%1,%2" ! 712: [(set_attr "type" "delayed_compare")]) ! 713: ! 714: ;; Operand 1 is divided by operand 2; quotient goes to operand ! 715: ;; 0 and remainder to operand 3. ! 716: ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). ! 717: ! 718: (define_insn "divmodsi4" ! 719: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 720: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 721: (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 722: (set (match_operand:SI 3 "gpc_reg_operand" "=q") ! 723: (mod:SI (match_dup 1) (match_dup 2)))] ! 724: "TARGET_POWER" ! 725: "divs %0,%1,%2" ! 726: [(set_attr "type" "idiv")]) ! 727: ! 728: (define_insn "" ! 729: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 730: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 731: (match_operand:SI 2 "gpc_reg_operand" "r")))] ! 732: "TARGET_POWERPC" ! 733: "divw %0, %1, %2" ! 734: [(set_attr "type" "idiv")]) ! 735: ! 736: (define_insn "udivsi3" ! 737: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 738: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 739: (match_operand:SI 2 "gpc_reg_operand" "r")))] ! 740: "TARGET_POWERPC" ! 741: "divwu %0, %1, %2" ! 742: [(set_attr "type" "idiv")]) ! 743: ! 744: ;; For powers of two we can do srai/aze for divide and then adjust for ! 745: ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be ! 746: ;; used; for PowerPC, force operands into register and do a normal divide. ! 747: (define_expand "divsi3" ! 748: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 749: (div:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 750: (match_operand:SI 2 "reg_or_cint_operand" "")))] ! 751: "" ! 752: " ! 753: { ! 754: if (GET_CODE (operands[2]) == CONST_INT ! 755: && exact_log2 (INTVAL (operands[2])) >= 0) ! 756: ; ! 757: else if (! TARGET_POWERPC) ! 758: FAIL; ! 759: else ! 760: operands[2] = force_reg (SImode, operands[2]); ! 761: }") ! 762: ! 763: (define_expand "modsi3" ! 764: [(use (match_operand:SI 0 "gpc_reg_operand" "")) ! 765: (use (match_operand:SI 1 "gpc_reg_operand" "")) ! 766: (use (match_operand:SI 2 "reg_or_cint_operand" ""))] ! 767: "" ! 768: " ! 769: { ! 770: int i = exact_log2 (INTVAL (operands[2])); ! 771: rtx temp1; ! 772: rtx temp2; ! 773: ! 774: if (GET_CODE (operands[2]) != CONST_INT || i < 0) ! 775: FAIL; ! 776: ! 777: temp1 = gen_reg_rtx (SImode); ! 778: temp2 = gen_reg_rtx (SImode); ! 779: ! 780: emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); ! 781: emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); ! 782: emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); ! 783: DONE; ! 784: ! 785: }") ! 786: ! 787: (define_insn "" ! 788: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 789: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 790: (match_operand:SI 2 "const_int_operand" "N")))] ! 791: "exact_log2 (INTVAL (operands[2])) >= 0" ! 792: "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" ! 793: [(set_attr "length" "8")]) ! 794: ! 795: (define_insn "" ! 796: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 797: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 798: (match_operand:SI 2 "const_int_operand" "N"))) ! 799: (clobber (match_scratch:SI 3 "=r"))] ! 800: "exact_log2 (INTVAL (operands[2])) >= 0" ! 801: "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3" ! 802: [(set_attr "type" "compare") ! 803: (set_attr "length" "8")]) ! 804: ! 805: (define_insn "" ! 806: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 807: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 808: (match_operand:SI 2 "const_int_operand" "N"))) ! 809: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 810: (div:SI (match_dup 1) (match_dup 2)))] ! 811: "exact_log2 (INTVAL (operands[2])) >= 0" ! 812: "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0" ! 813: [(set_attr "type" "compare") ! 814: (set_attr "length" "8")]) ! 815: ! 816: (define_insn "" ! 817: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 818: (udiv:SI ! 819: (plus:DI (lshift:DI ! 820: (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 821: (const_int 32)) ! 822: (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) ! 823: (match_operand:SI 3 "gpc_reg_operand" "r"))) ! 824: (set (match_operand:SI 2 "register_operand" "=*q") ! 825: (umod:SI ! 826: (plus:DI (lshift:DI ! 827: (zero_extend:DI (match_dup 1)) (const_int 32)) ! 828: (zero_extend:DI (match_dup 4))) ! 829: (match_dup 3)))] ! 830: ! 831: "TARGET_POWER" ! 832: "div %0,%1,%3" ! 833: [(set_attr "type" "idiv")]) ! 834: ! 835: ;; To do unsigned divide we handle the cases of the divisor looking like a ! 836: ;; negative number. If it is a constant that is less than 2**31, we don't ! 837: ;; have to worry about the branches. So make a few subroutines here. ! 838: ;; ! 839: ;; First comes the normal case. ! 840: (define_expand "udivmodsi4_normal" ! 841: [(set (match_dup 4) (const_int 0)) ! 842: (parallel [(set (match_operand:SI 0 "" "") ! 843: (udiv:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4)) ! 844: (const_int 32)) ! 845: (zero_extend:DI (match_operand:SI 1 "" ""))) ! 846: (match_operand:SI 2 "" ""))) ! 847: (set (match_operand:SI 3 "" "") ! 848: (umod:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4)) ! 849: (const_int 32)) ! 850: (zero_extend:DI (match_dup 1))) ! 851: (match_dup 2)))])] ! 852: "TARGET_POWER" ! 853: " ! 854: { operands[4] = gen_reg_rtx (SImode); }") ! 855: ! 856: ;; This handles the branches. ! 857: (define_expand "udivmodsi4_tests" ! 858: [(set (match_operand:SI 0 "" "") (const_int 0)) ! 859: (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) ! 860: (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) ! 861: (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) ! 862: (label_ref (match_operand:SI 4 "" "")) (pc))) ! 863: (set (match_dup 0) (const_int 1)) ! 864: (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) ! 865: (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) ! 866: (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) ! 867: (label_ref (match_dup 4)) (pc)))] ! 868: "TARGET_POWER" ! 869: " ! 870: { operands[5] = gen_reg_rtx (CCUNSmode); ! 871: operands[6] = gen_reg_rtx (CCmode); ! 872: }") ! 873: ! 874: (define_expand "udivmodsi4" ! 875: [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 876: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 877: (match_operand:SI 2 "reg_or_cint_operand" ""))) ! 878: (set (match_operand:SI 3 "gpc_reg_operand" "") ! 879: (umod:SI (match_dup 1) (match_dup 2)))])] ! 880: "TARGET_POWER" ! 881: " ! 882: { ! 883: rtx label = 0; ! 884: ! 885: if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) ! 886: { ! 887: operands[2] = force_reg (SImode, operands[2]); ! 888: label = gen_label_rtx (); ! 889: emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], ! 890: operands[3], label)); ! 891: } ! 892: else ! 893: operands[2] = force_reg (SImode, operands[2]); ! 894: ! 895: emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], ! 896: operands[3])); ! 897: if (label) ! 898: emit_label (label); ! 899: ! 900: DONE; ! 901: }") ! 902: ! 903: (define_insn "andsi3" ! 904: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") ! 905: (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") ! 906: (match_operand:SI 2 "and_operand" "?r,L,K,J"))) ! 907: (clobber (match_scratch:CC 3 "=X,X,x,x"))] ! 908: "" ! 909: "@ ! 910: and %0,%1,%2 ! 911: {rlinm|rlwinm} %0,%1,0,%m2,%M2 ! 912: {andil.|andi.} %0,%1,%b2 ! 913: {andiu.|andis.} %0,%1,%u2") ! 914: ! 915: (define_insn "" ! 916: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") ! 917: (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") ! 918: (match_operand:SI 2 "and_operand" "r,K,J,L")) ! 919: (const_int 0))) ! 920: (clobber (match_scratch:SI 3 "=r,r,r,r"))] ! 921: "" ! 922: "@ ! 923: and. %3,%1,%2 ! 924: {andil.|andi.} %3,%1,%b2 ! 925: {andiu.|andis.} %3,%1,%u2 ! 926: {rlinm.|rlwinm.} %3,%1,0,%m2,%M2" ! 927: [(set_attr "type" "compare,compare,compare,delayed_compare")]) ! 928: ! 929: (define_insn "" ! 930: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") ! 931: (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") ! 932: (match_operand:SI 2 "and_operand" "r,K,J,L")) ! 933: (const_int 0))) ! 934: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") ! 935: (and:SI (match_dup 1) (match_dup 2)))] ! 936: "" ! 937: "@ ! 938: and. %0,%1,%2 ! 939: {andil.|andi.} %0,%1,%b2 ! 940: {andiu.|andis.} %0,%1,%u2 ! 941: {rlinm.|rlwinm.} %0,%1,0,%m2,%M2" ! 942: [(set_attr "type" "compare,compare,compare,delayed_compare")]) ! 943: ! 944: ;; Take a AND with a constant that cannot be done in a single insn and try to ! 945: ;; split it into two insns. This does not verify that the insns are valid ! 946: ;; since this need not be done as combine will do it. ! 947: ! 948: (define_split ! 949: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 950: (and:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 951: (match_operand:SI 2 "non_and_cint_operand" "")))] ! 952: "" ! 953: [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3))) ! 954: (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))] ! 955: " ! 956: { ! 957: int maskval = INTVAL (operands[2]); ! 958: int i, transitions, last_bit_value; ! 959: int orig = maskval, first_c = maskval, second_c; ! 960: ! 961: /* We know that MASKVAL must have more than 2 bit-transitions. Start at ! 962: the low-order bit and count for the third transition. When we get there, ! 963: make a first mask that has everything to the left of that position ! 964: a one. Then make the second mask to turn off whatever else is needed. */ ! 965: ! 966: for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++) ! 967: { ! 968: if (((maskval >>= 1) & 1) != last_bit_value) ! 969: last_bit_value ^= 1, transitions++; ! 970: ! 971: if (transitions > 2) ! 972: { ! 973: first_c |= (~0) << i; ! 974: break; ! 975: } ! 976: } ! 977: ! 978: second_c = orig | ~ first_c; ! 979: ! 980: operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c); ! 981: operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c); ! 982: }") ! 983: ! 984: (define_insn "iorsi3" ! 985: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") ! 986: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") ! 987: (match_operand:SI 2 "logical_operand" "r,K,J")))] ! 988: "" ! 989: "@ ! 990: or %0,%1,%2 ! 991: {oril|ori} %0,%1,%b2 ! 992: {oriu|oris} %0,%1,%u2") ! 993: ! 994: (define_insn "" ! 995: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 996: (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 997: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 998: (const_int 0))) ! 999: (clobber (match_scratch:SI 3 "=r"))] ! 1000: "" ! 1001: "or. %3,%1,%2" ! 1002: [(set_attr "type" "compare")]) ! 1003: ! 1004: (define_insn "" ! 1005: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1006: (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1007: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 1008: (const_int 0))) ! 1009: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1010: (ior:SI (match_dup 1) (match_dup 2)))] ! 1011: "" ! 1012: "or. %0,%1,%2" ! 1013: [(set_attr "type" "compare")]) ! 1014: ! 1015: ;; Split an IOR that we can't do in one insn into two insns, each of which ! 1016: ;; does one 16-bit part. This is used by combine. ! 1017: ! 1018: (define_split ! 1019: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 1020: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 1021: (match_operand:SI 2 "non_logical_cint_operand" "")))] ! 1022: "" ! 1023: [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3))) ! 1024: (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))] ! 1025: " ! 1026: { ! 1027: operands[3] = gen_rtx (CONST_INT, VOIDmode, ! 1028: INTVAL (operands[2]) & 0xffff0000); ! 1029: operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); ! 1030: }") ! 1031: ! 1032: (define_insn "xorsi3" ! 1033: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") ! 1034: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") ! 1035: (match_operand:SI 2 "logical_operand" "r,K,J")))] ! 1036: "" ! 1037: "@ ! 1038: xor %0,%1,%2 ! 1039: {xoril|xori} %0,%1,%b2 ! 1040: {xoriu|xoris} %0,%1,%u2") ! 1041: ! 1042: (define_insn "" ! 1043: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1044: (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1045: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 1046: (const_int 0))) ! 1047: (clobber (match_scratch:SI 3 "=r"))] ! 1048: "" ! 1049: "xor. %3,%1,%2" ! 1050: [(set_attr "type" "compare")]) ! 1051: ! 1052: (define_insn "" ! 1053: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1054: (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1055: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 1056: (const_int 0))) ! 1057: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1058: (xor:SI (match_dup 1) (match_dup 2)))] ! 1059: "" ! 1060: "xor. %0,%1,%2" ! 1061: [(set_attr "type" "compare")]) ! 1062: ! 1063: ;; Split an XOR that we can't do in one insn into two insns, each of which ! 1064: ;; does one 16-bit part. This is used by combine. ! 1065: ! 1066: (define_split ! 1067: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 1068: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 1069: (match_operand:SI 2 "non_logical_cint_operand" "")))] ! 1070: "" ! 1071: [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3))) ! 1072: (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))] ! 1073: " ! 1074: { ! 1075: operands[3] = gen_rtx (CONST_INT, VOIDmode, ! 1076: INTVAL (operands[2]) & 0xffff0000); ! 1077: operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); ! 1078: }") ! 1079: ! 1080: (define_insn "" ! 1081: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1082: (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") ! 1083: (match_operand:SI 2 "gpc_reg_operand" "r"))))] ! 1084: "" ! 1085: "eqv %0,%1,%2") ! 1086: ! 1087: (define_insn "" ! 1088: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1089: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") ! 1090: (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 1091: (const_int 0))) ! 1092: (clobber (match_scratch:SI 3 "=r"))] ! 1093: "" ! 1094: "eqv. %3,%1,%2" ! 1095: [(set_attr "type" "compare")]) ! 1096: ! 1097: (define_insn "" ! 1098: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1099: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") ! 1100: (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 1101: (const_int 0))) ! 1102: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1103: (not:SI (xor:SI (match_dup 1) (match_dup 2))))] ! 1104: "" ! 1105: "eqv. %0,%1,%2" ! 1106: [(set_attr "type" "compare")]) ! 1107: ! 1108: (define_insn "" ! 1109: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1110: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1111: (match_operand:SI 2 "gpc_reg_operand" "r")))] ! 1112: "" ! 1113: "andc %0,%2,%1") ! 1114: ! 1115: (define_insn "" ! 1116: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1117: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1118: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 1119: (const_int 0))) ! 1120: (clobber (match_scratch:SI 3 "=r"))] ! 1121: "" ! 1122: "andc. %3,%2,%1" ! 1123: [(set_attr "type" "compare")]) ! 1124: ! 1125: (define_insn "" ! 1126: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1127: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1128: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 1129: (const_int 0))) ! 1130: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1131: (and:SI (not:SI (match_dup 1)) (match_dup 2)))] ! 1132: "" ! 1133: "andc. %0,%2,%1" ! 1134: [(set_attr "type" "compare")]) ! 1135: ! 1136: (define_insn "" ! 1137: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1138: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1139: (match_operand:SI 2 "gpc_reg_operand" "r")))] ! 1140: "" ! 1141: "orc %0,%2,%1") ! 1142: ! 1143: (define_insn "" ! 1144: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1145: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1146: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 1147: (const_int 0))) ! 1148: (clobber (match_scratch:SI 3 "=r"))] ! 1149: "" ! 1150: "orc. %3,%2,%1" ! 1151: [(set_attr "type" "compare")]) ! 1152: ! 1153: (define_insn "" ! 1154: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1155: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1156: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 1157: (const_int 0))) ! 1158: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1159: (ior:SI (not:SI (match_dup 1)) (match_dup 2)))] ! 1160: "" ! 1161: "orc. %0,%2,%1" ! 1162: [(set_attr "type" "compare")]) ! 1163: ! 1164: (define_insn "" ! 1165: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1166: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1167: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] ! 1168: "" ! 1169: "nand %0,%1,%2") ! 1170: ! 1171: (define_insn "" ! 1172: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1173: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1174: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 1175: (const_int 0))) ! 1176: (clobber (match_scratch:SI 3 "=r"))] ! 1177: "" ! 1178: "nand. %3,%1,%2" ! 1179: [(set_attr "type" "compare")]) ! 1180: ! 1181: (define_insn "" ! 1182: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1183: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1184: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 1185: (const_int 0))) ! 1186: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1187: (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] ! 1188: "" ! 1189: "nand. %0,%1,%2" ! 1190: [(set_attr "type" "compare")]) ! 1191: ! 1192: (define_insn "" ! 1193: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1194: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1195: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] ! 1196: "" ! 1197: "nor %0,%1,%2") ! 1198: ! 1199: (define_insn "" ! 1200: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1201: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1202: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 1203: (const_int 0))) ! 1204: (clobber (match_scratch:SI 3 "=r"))] ! 1205: "" ! 1206: "nor. %3,%1,%2" ! 1207: [(set_attr "type" "compare")]) ! 1208: ! 1209: (define_insn "" ! 1210: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1211: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1212: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 1213: (const_int 0))) ! 1214: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1215: (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] ! 1216: "" ! 1217: "nor. %0,%1,%2" ! 1218: [(set_attr "type" "compare")]) ! 1219: ! 1220: ;; maskir insn. We need four forms because things might be in arbitrary ! 1221: ;; orders. Don't define forms that only set CR fields because these ! 1222: ;; would modify an input register. ! 1223: ! 1224: (define_insn "" ! 1225: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1226: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) ! 1227: (match_operand:SI 1 "gpc_reg_operand" "0")) ! 1228: (and:SI (match_dup 2) ! 1229: (match_operand:SI 3 "gpc_reg_operand" "r"))))] ! 1230: "TARGET_POWER" ! 1231: "maskir %0,%3,%2") ! 1232: ! 1233: (define_insn "" ! 1234: [(set (match_operand:SI 0 "register_operand" "=r") ! 1235: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) ! 1236: (match_operand:SI 1 "gpc_reg_operand" "0")) ! 1237: (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") ! 1238: (match_dup 2))))] ! 1239: "TARGET_POWER" ! 1240: "maskir %0,%3,%2") ! 1241: ! 1242: (define_insn "" ! 1243: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1244: (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") ! 1245: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 1246: (and:SI (not:SI (match_dup 2)) ! 1247: (match_operand:SI 1 "gpc_reg_operand" "0"))))] ! 1248: "TARGET_POWER" ! 1249: "maskir %0,%3,%2") ! 1250: ! 1251: (define_insn "" ! 1252: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1253: (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") ! 1254: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 1255: (and:SI (not:SI (match_dup 2)) ! 1256: (match_operand:SI 1 "gpc_reg_operand" "0"))))] ! 1257: "TARGET_POWER" ! 1258: "maskir %0,%3,%2") ! 1259: ! 1260: (define_insn "" ! 1261: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 1262: (compare:CC ! 1263: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) ! 1264: (match_operand:SI 1 "gpc_reg_operand" "0")) ! 1265: (and:SI (match_dup 2) ! 1266: (match_operand:SI 3 "gpc_reg_operand" "r"))) ! 1267: (const_int 0))) ! 1268: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1269: (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) ! 1270: (and:SI (match_dup 2) (match_dup 3))))] ! 1271: "TARGET_POWER" ! 1272: "maskir. %0,%3,%2" ! 1273: [(set_attr "type" "compare")]) ! 1274: ! 1275: (define_insn "" ! 1276: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 1277: (compare:CC ! 1278: (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) ! 1279: (match_operand:SI 1 "gpc_reg_operand" "0")) ! 1280: (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") ! 1281: (match_dup 2))) ! 1282: (const_int 0))) ! 1283: (set (match_operand:SI 0 "register_operand" "=r") ! 1284: (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) ! 1285: (and:SI (match_dup 3) (match_dup 2))))] ! 1286: "TARGET_POWER" ! 1287: "maskir. %0,%3,%2" ! 1288: [(set_attr "type" "compare")]) ! 1289: ! 1290: (define_insn "" ! 1291: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 1292: (compare:CC ! 1293: (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") ! 1294: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 1295: (and:SI (not:SI (match_dup 2)) ! 1296: (match_operand:SI 1 "gpc_reg_operand" "0"))) ! 1297: (const_int 0))) ! 1298: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1299: (ior:SI (and:SI (match_dup 2) (match_dup 3)) ! 1300: (and:SI (not:SI (match_dup 2)) (match_dup 1))))] ! 1301: "TARGET_POWER" ! 1302: "maskir. %0,%3,%2" ! 1303: [(set_attr "type" "compare")]) ! 1304: ! 1305: (define_insn "" ! 1306: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 1307: (compare:CC ! 1308: (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") ! 1309: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 1310: (and:SI (not:SI (match_dup 2)) ! 1311: (match_operand:SI 1 "gpc_reg_operand" "0"))) ! 1312: (const_int 0))) ! 1313: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1314: (ior:SI (and:SI (match_dup 3) (match_dup 2)) ! 1315: (and:SI (not:SI (match_dup 2)) (match_dup 1))))] ! 1316: "TARGET_POWER" ! 1317: "maskir. %0,%3,%2" ! 1318: [(set_attr "type" "compare")]) ! 1319: ! 1320: ;; Rotate and shift insns, in all their variants. These support shifts, ! 1321: ;; field inserts and extracts, and various combinations thereof. ! 1322: (define_insn "insv" ! 1323: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") ! 1324: (match_operand:SI 1 "const_int_operand" "i") ! 1325: (match_operand:SI 2 "const_int_operand" "i")) ! 1326: (match_operand:SI 3 "gpc_reg_operand" "r"))] ! 1327: "" ! 1328: "* ! 1329: { ! 1330: int start = INTVAL (operands[2]) & 31; ! 1331: int size = INTVAL (operands[1]) & 31; ! 1332: ! 1333: operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size); ! 1334: operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1); ! 1335: return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\"; ! 1336: }") ! 1337: ! 1338: (define_insn "extzv" ! 1339: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1340: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1341: (match_operand:SI 2 "const_int_operand" "i") ! 1342: (match_operand:SI 3 "const_int_operand" "i")))] ! 1343: "" ! 1344: "* ! 1345: { ! 1346: int start = INTVAL (operands[3]) & 31; ! 1347: int size = INTVAL (operands[2]) & 31; ! 1348: ! 1349: if (start + size >= 32) ! 1350: operands[3] = const0_rtx; ! 1351: else ! 1352: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); ! 1353: return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; ! 1354: }") ! 1355: ! 1356: (define_insn "" ! 1357: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1358: (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1359: (match_operand:SI 2 "const_int_operand" "i") ! 1360: (match_operand:SI 3 "const_int_operand" "i")) ! 1361: (const_int 0))) ! 1362: (clobber (match_scratch:SI 4 "=r"))] ! 1363: "" ! 1364: "* ! 1365: { ! 1366: int start = INTVAL (operands[3]) & 31; ! 1367: int size = INTVAL (operands[2]) & 31; ! 1368: ! 1369: /* If the bitfield being tested fits in the upper or lower half of a ! 1370: word, it is possible to use andiu. or andil. to test it. This is ! 1371: useful because the condition register set-use delay is smaller for ! 1372: andi[ul]. than for rlinm. This doesn't work when the starting bit ! 1373: position is 0 because the LT and GT bits may be set wrong. */ ! 1374: ! 1375: if ((start > 0 && start + size <= 16) || start >= 16) ! 1376: { ! 1377: operands[3] = gen_rtx (CONST_INT, VOIDmode, ! 1378: ((1 << (16 - (start & 15))) ! 1379: - (1 << (16 - (start & 15) - size)))); ! 1380: if (start < 16) ! 1381: return \"{andiu.|andis.} %4,%1,%3\"; ! 1382: else ! 1383: return \"{andil.|andi.} %4,%1,%3\"; ! 1384: } ! 1385: ! 1386: if (start + size >= 32) ! 1387: operands[3] = const0_rtx; ! 1388: else ! 1389: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); ! 1390: return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; ! 1391: }" ! 1392: [(set_attr "type" "compare")]) ! 1393: ! 1394: (define_insn "" ! 1395: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 1396: (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1397: (match_operand:SI 2 "const_int_operand" "i") ! 1398: (match_operand:SI 3 "const_int_operand" "i")) ! 1399: (const_int 0))) ! 1400: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1401: (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] ! 1402: "" ! 1403: "* ! 1404: { ! 1405: int start = INTVAL (operands[3]) & 31; ! 1406: int size = INTVAL (operands[2]) & 31; ! 1407: ! 1408: if (start >= 16 && start + size == 32) ! 1409: { ! 1410: operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1); ! 1411: return \"{andil.|andi.} %0,%1,%3\"; ! 1412: } ! 1413: ! 1414: if (start + size >= 32) ! 1415: operands[3] = const0_rtx; ! 1416: else ! 1417: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); ! 1418: return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; ! 1419: }" ! 1420: [(set_attr "type" "delayed_compare")]) ! 1421: ! 1422: (define_insn "rotlsi3" ! 1423: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1424: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1425: (match_operand:SI 2 "reg_or_cint_operand" "ri")))] ! 1426: "" ! 1427: "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") ! 1428: ! 1429: (define_insn "" ! 1430: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1431: (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1432: (match_operand:SI 2 "reg_or_cint_operand" "ri")) ! 1433: (const_int 0))) ! 1434: (clobber (match_scratch:SI 3 "=r"))] ! 1435: "" ! 1436: "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff" ! 1437: [(set_attr "type" "delayed_compare")]) ! 1438: ! 1439: (define_insn "" ! 1440: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1441: (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1442: (match_operand:SI 2 "reg_or_cint_operand" "ri")) ! 1443: (const_int 0))) ! 1444: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1445: (rotate:SI (match_dup 1) (match_dup 2)))] ! 1446: "" ! 1447: "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff" ! 1448: [(set_attr "type" "delayed_compare")]) ! 1449: ! 1450: (define_insn "" ! 1451: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1452: (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1453: (match_operand:SI 2 "reg_or_cint_operand" "ri")) ! 1454: (match_operand:SI 3 "mask_operand" "L")))] ! 1455: "" ! 1456: "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") ! 1457: ! 1458: (define_insn "" ! 1459: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1460: (compare:CC (and:SI ! 1461: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1462: (match_operand:SI 2 "reg_or_cint_operand" "ri")) ! 1463: (match_operand:SI 3 "mask_operand" "L")) ! 1464: (const_int 0))) ! 1465: (clobber (match_scratch:SI 4 "=r"))] ! 1466: "" ! 1467: "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3" ! 1468: [(set_attr "type" "delayed_compare")]) ! 1469: ! 1470: (define_insn "" ! 1471: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 1472: (compare:CC (and:SI ! 1473: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1474: (match_operand:SI 2 "reg_or_cint_operand" "ri")) ! 1475: (match_operand:SI 3 "mask_operand" "L")) ! 1476: (const_int 0))) ! 1477: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1478: (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] ! 1479: "" ! 1480: "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3" ! 1481: [(set_attr "type" "delayed_compare")]) ! 1482: ! 1483: (define_insn "" ! 1484: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1485: (zero_extend:SI ! 1486: (subreg:QI ! 1487: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1488: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] ! 1489: "" ! 1490: "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") ! 1491: ! 1492: (define_insn "" ! 1493: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1494: (compare:CC (zero_extend:SI ! 1495: (subreg:QI ! 1496: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1497: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) ! 1498: (const_int 0))) ! 1499: (clobber (match_scratch:SI 3 "=r"))] ! 1500: "" ! 1501: "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff" ! 1502: [(set_attr "type" "delayed_compare")]) ! 1503: ! 1504: (define_insn "" ! 1505: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1506: (compare:CC (zero_extend:SI ! 1507: (subreg:QI ! 1508: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1509: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) ! 1510: (const_int 0))) ! 1511: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1512: (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] ! 1513: "" ! 1514: "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff" ! 1515: [(set_attr "type" "delayed_compare")]) ! 1516: ! 1517: (define_insn "" ! 1518: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1519: (zero_extend:SI ! 1520: (subreg:HI ! 1521: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1522: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] ! 1523: "" ! 1524: "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") ! 1525: ! 1526: (define_insn "" ! 1527: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1528: (compare:CC (zero_extend:SI ! 1529: (subreg:HI ! 1530: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1531: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) ! 1532: (const_int 0))) ! 1533: (clobber (match_scratch:SI 3 "=r"))] ! 1534: "" ! 1535: "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff" ! 1536: [(set_attr "type" "delayed_compare")]) ! 1537: ! 1538: (define_insn "" ! 1539: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1540: (compare:CC (zero_extend:SI ! 1541: (subreg:HI ! 1542: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1543: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) ! 1544: (const_int 0))) ! 1545: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1546: (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] ! 1547: "" ! 1548: "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff" ! 1549: [(set_attr "type" "delayed_compare")]) ! 1550: ! 1551: ;; Note that we use "sle." instead of "sl." so that we can set ! 1552: ;; SHIFT_COUNT_TRUNCATED. ! 1553: ! 1554: (define_expand "ashlsi3" ! 1555: [(use (match_operand:SI 0 "gpc_reg_operand" "")) ! 1556: (use (match_operand:SI 1 "gpc_reg_operand" "")) ! 1557: (use (match_operand:SI 2 "reg_or_cint_operand" ""))] ! 1558: "" ! 1559: " ! 1560: { ! 1561: if (TARGET_POWER) ! 1562: emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); ! 1563: else ! 1564: emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); ! 1565: DONE; ! 1566: }") ! 1567: ! 1568: (define_insn "ashlsi3_power" ! 1569: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 1570: (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1571: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) ! 1572: (clobber (match_scratch:SI 3 "=q,X"))] ! 1573: "TARGET_POWER" ! 1574: "@ ! 1575: sle %0,%1,%2 ! 1576: {sli|slwi} %0,%1,%h2" ! 1577: [(set_attr "length" "8")]) ! 1578: ! 1579: (define_insn "ashlsi3_no_power" ! 1580: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1581: (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1582: (match_operand:SI 2 "reg_or_cint_operand" "ri")))] ! 1583: "! TARGET_POWER" ! 1584: "slw%I2 %0,%1,%2" ! 1585: [(set_attr "length" "8")]) ! 1586: ! 1587: (define_insn "" ! 1588: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") ! 1589: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1590: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) ! 1591: (const_int 0))) ! 1592: (clobber (match_scratch:SI 3 "=r,r")) ! 1593: (clobber (match_scratch:SI 4 "=q,X"))] ! 1594: "TARGET_POWER" ! 1595: "@ ! 1596: sle. %3,%1,%2 ! 1597: {sli.|slwi.} %3,%1,%h2" ! 1598: [(set_attr "type" "delayed_compare")]) ! 1599: ! 1600: (define_insn "" ! 1601: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1602: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1603: (match_operand:SI 2 "reg_or_cint_operand" "ri")) ! 1604: (const_int 0))) ! 1605: (clobber (match_scratch:SI 3 "=r"))] ! 1606: "TARGET_POWERPC" ! 1607: "slw%I2. %3,%1,%2" ! 1608: [(set_attr "type" "delayed_compare")]) ! 1609: ! 1610: (define_insn "" ! 1611: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") ! 1612: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1613: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) ! 1614: (const_int 0))) ! 1615: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 1616: (ashift:SI (match_dup 1) (match_dup 2))) ! 1617: (clobber (match_scratch:SI 4 "=q,X"))] ! 1618: "TARGET_POWER" ! 1619: "@ ! 1620: sle. %0,%1,%2 ! 1621: {sli.|slwi.} %0,%1,%h2" ! 1622: [(set_attr "type" "delayed_compare")]) ! 1623: ! 1624: (define_insn "" ! 1625: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1626: (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1627: (match_operand:SI 2 "reg_or_cint_operand" "ri")) ! 1628: (const_int 0))) ! 1629: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1630: (ashift:SI (match_dup 1) (match_dup 2)))] ! 1631: "TARGET_POWERPC" ! 1632: "slw%I2. %0,%1,%2" ! 1633: [(set_attr "type" "delayed_compare")]) ! 1634: ! 1635: (define_insn "" ! 1636: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1637: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1638: (match_operand:SI 2 "const_int_operand" "i")) ! 1639: (match_operand:SI 3 "mask_operand" "L")))] ! 1640: "includes_lshift_p (operands[2], operands[3])" ! 1641: "{rlinm|rlwinm} %0,%h1,%h2,%m3,%M3") ! 1642: ! 1643: (define_insn "" ! 1644: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1645: (compare:CC ! 1646: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1647: (match_operand:SI 2 "const_int_operand" "i")) ! 1648: (match_operand:SI 3 "mask_operand" "L")) ! 1649: (const_int 0))) ! 1650: (clobber (match_scratch:SI 4 "=r"))] ! 1651: "includes_lshift_p (operands[2], operands[3])" ! 1652: "{rlinm.|rlwinm.} %4,%h1,%h2,%m3,%M3" ! 1653: [(set_attr "type" "delayed_compare")]) ! 1654: ! 1655: (define_insn "" ! 1656: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 1657: (compare:CC ! 1658: (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1659: (match_operand:SI 2 "const_int_operand" "i")) ! 1660: (match_operand:SI 3 "mask_operand" "L")) ! 1661: (const_int 0))) ! 1662: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1663: (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] ! 1664: "includes_lshift_p (operands[2], operands[3])" ! 1665: "{rlinm.|rlwinm.} %0,%h1,%h2,%m3,%M3" ! 1666: [(set_attr "type" "delayed_compare")]) ! 1667: ! 1668: ;; The AIX assembler mis-handles "sri x,x,0", so write that case as ! 1669: ;; "sli x,x,0". ! 1670: (define_expand "lshrsi3" ! 1671: [(use (match_operand:SI 0 "gpc_reg_operand" "")) ! 1672: (use (match_operand:SI 1 "gpc_reg_operand" "")) ! 1673: (use (match_operand:SI 2 "reg_or_cint_operand" ""))] ! 1674: "" ! 1675: " ! 1676: { ! 1677: if (TARGET_POWER) ! 1678: emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); ! 1679: else ! 1680: emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); ! 1681: DONE; ! 1682: }") ! 1683: ! 1684: (define_insn "lshrsi3_power" ! 1685: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 1686: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1687: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) ! 1688: (clobber (match_scratch:SI 3 "=q,X"))] ! 1689: "TARGET_POWER" ! 1690: "@ ! 1691: sre %0,%1,%2 ! 1692: {s%A2i|s%A2wi} %0,%1,%h2") ! 1693: ! 1694: (define_insn "lshrsi3_no_power" ! 1695: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1696: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1697: (match_operand:SI 2 "reg_or_cint_operand" "ri")))] ! 1698: "! TARGET_POWER" ! 1699: "srw%I2 %0,%1,%2") ! 1700: ! 1701: (define_insn "" ! 1702: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") ! 1703: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1704: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) ! 1705: (const_int 0))) ! 1706: (clobber (match_scratch:SI 3 "=r,r")) ! 1707: (clobber (match_scratch:SI 4 "=q,X"))] ! 1708: "TARGET_POWER" ! 1709: "@ ! 1710: sre. %3,%1,%2 ! 1711: {s%A2i.|s%A2wi.} %3,%1,%h2" ! 1712: [(set_attr "type" "delayed_compare")]) ! 1713: ! 1714: (define_insn "" ! 1715: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1716: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1717: (match_operand:SI 2 "reg_or_cint_operand" "ri")) ! 1718: (const_int 0))) ! 1719: (clobber (match_scratch:SI 3 "=r"))] ! 1720: "! TARGET_POWER" ! 1721: "srw%I2. %3,%1,%2" ! 1722: [(set_attr "type" "delayed_compare")]) ! 1723: ! 1724: (define_insn "" ! 1725: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") ! 1726: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1727: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) ! 1728: (const_int 0))) ! 1729: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 1730: (lshiftrt:SI (match_dup 1) (match_dup 2))) ! 1731: (clobber (match_scratch:SI 4 "=q,X"))] ! 1732: "TARGET_POWER" ! 1733: "@ ! 1734: sre. %0,%1,%2 ! 1735: {s%A2i.|s%A2wi.} %0,%1,%h2" ! 1736: [(set_attr "type" "delayed_compare")]) ! 1737: ! 1738: (define_insn "" ! 1739: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1740: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1741: (match_operand:SI 2 "reg_or_cint_operand" "ri")) ! 1742: (const_int 0))) ! 1743: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1744: (lshiftrt:SI (match_dup 1) (match_dup 2)))] ! 1745: "! TARGET_POWER" ! 1746: "srw%I2. %0,%1,%2" ! 1747: [(set_attr "type" "delayed_compare")]) ! 1748: ! 1749: (define_insn "" ! 1750: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1751: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1752: (match_operand:SI 2 "const_int_operand" "i")) ! 1753: (match_operand:SI 3 "mask_operand" "L")))] ! 1754: "includes_rshift_p (operands[2], operands[3])" ! 1755: "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") ! 1756: ! 1757: (define_insn "" ! 1758: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1759: (compare:CC ! 1760: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1761: (match_operand:SI 2 "const_int_operand" "i")) ! 1762: (match_operand:SI 3 "mask_operand" "L")) ! 1763: (const_int 0))) ! 1764: (clobber (match_scratch:SI 4 "=r"))] ! 1765: "includes_rshift_p (operands[2], operands[3])" ! 1766: "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3" ! 1767: [(set_attr "type" "delayed_compare")]) ! 1768: ! 1769: (define_insn "" ! 1770: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 1771: (compare:CC ! 1772: (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1773: (match_operand:SI 2 "const_int_operand" "i")) ! 1774: (match_operand:SI 3 "mask_operand" "L")) ! 1775: (const_int 0))) ! 1776: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1777: (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] ! 1778: "includes_rshift_p (operands[2], operands[3])" ! 1779: "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3" ! 1780: [(set_attr "type" "delayed_compare")]) ! 1781: ! 1782: (define_insn "" ! 1783: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1784: (zero_extend:SI ! 1785: (subreg:QI ! 1786: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1787: (match_operand:SI 2 "const_int_operand" "i")) 0)))] ! 1788: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" ! 1789: "{rlinm|rlwinm} %0,%1,%s2,0xff") ! 1790: ! 1791: (define_insn "" ! 1792: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1793: (compare:CC ! 1794: (zero_extend:SI ! 1795: (subreg:QI ! 1796: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1797: (match_operand:SI 2 "const_int_operand" "i")) 0)) ! 1798: (const_int 0))) ! 1799: (clobber (match_scratch:SI 3 "=r"))] ! 1800: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" ! 1801: "{rlinm.|rlwinm.} %3,%1,%s2,0xff" ! 1802: [(set_attr "type" "delayed_compare")]) ! 1803: ! 1804: (define_insn "" ! 1805: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1806: (compare:CC ! 1807: (zero_extend:SI ! 1808: (subreg:QI ! 1809: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1810: (match_operand:SI 2 "const_int_operand" "i")) 0)) ! 1811: (const_int 0))) ! 1812: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1813: (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] ! 1814: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" ! 1815: "{rlinm.|rlwinm.} %0,%1,%s2,0xff" ! 1816: [(set_attr "type" "delayed_compare")]) ! 1817: ! 1818: (define_insn "" ! 1819: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1820: (zero_extend:SI ! 1821: (subreg:HI ! 1822: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1823: (match_operand:SI 2 "const_int_operand" "i")) 0)))] ! 1824: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" ! 1825: "{rlinm|rlwinm} %0,%1,%s2,0xffff") ! 1826: ! 1827: (define_insn "" ! 1828: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1829: (compare:CC ! 1830: (zero_extend:SI ! 1831: (subreg:HI ! 1832: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1833: (match_operand:SI 2 "const_int_operand" "i")) 0)) ! 1834: (const_int 0))) ! 1835: (clobber (match_scratch:SI 3 "=r"))] ! 1836: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" ! 1837: "{rlinm.|rlwinm.} %3,%1,%s2,0xffff" ! 1838: [(set_attr "type" "delayed_compare")]) ! 1839: ! 1840: (define_insn "" ! 1841: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1842: (compare:CC ! 1843: (zero_extend:SI ! 1844: (subreg:HI ! 1845: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1846: (match_operand:SI 2 "const_int_operand" "i")) 0)) ! 1847: (const_int 0))) ! 1848: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1849: (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] ! 1850: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" ! 1851: "{rlinm.|rlwinm.} %0,%1,%s2,0xffff" ! 1852: [(set_attr "type" "delayed_compare")]) ! 1853: ! 1854: (define_insn "" ! 1855: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") ! 1856: (const_int 1) ! 1857: (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1858: (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") ! 1859: (const_int 31)))] ! 1860: "TARGET_POWER" ! 1861: "rrib %0,%1,%2") ! 1862: ! 1863: (define_insn "" ! 1864: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") ! 1865: (const_int 1) ! 1866: (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1867: (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") ! 1868: (const_int 31)))] ! 1869: "TARGET_POWER" ! 1870: "rrib %0,%1,%2") ! 1871: ! 1872: (define_insn "" ! 1873: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") ! 1874: (const_int 1) ! 1875: (match_operand:SI 1 "gpc_reg_operand" "r")) ! 1876: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") ! 1877: (const_int 1) ! 1878: (const_int 0)))] ! 1879: "TARGET_POWER" ! 1880: "rrib %0,%1,%2") ! 1881: ! 1882: (define_expand "ashrsi3" ! 1883: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 1884: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 1885: (match_operand:SI 2 "reg_or_cint_operand" "")))] ! 1886: "" ! 1887: " ! 1888: { ! 1889: if (TARGET_POWER) ! 1890: emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); ! 1891: else ! 1892: emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); ! 1893: DONE; ! 1894: }") ! 1895: ! 1896: (define_insn "ashrsi3_power" ! 1897: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 1898: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1899: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) ! 1900: (clobber (match_scratch:SI 3 "=q,X"))] ! 1901: "TARGET_POWER" ! 1902: "@ ! 1903: srea %0,%1,%2 ! 1904: {srai|srawi} %0,%1,%h2") ! 1905: ! 1906: (define_insn "ashrsi3_no_power" ! 1907: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1908: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1909: (match_operand:SI 2 "reg_or_cint_operand" "ri")))] ! 1910: "! TARGET_POWER" ! 1911: "sraw%I2 %0,%1,%2") ! 1912: ! 1913: (define_insn "" ! 1914: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") ! 1915: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1916: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) ! 1917: (const_int 0))) ! 1918: (clobber (match_scratch:SI 3 "=r,r")) ! 1919: (clobber (match_scratch:SI 4 "=q,X"))] ! 1920: "TARGET_POWER" ! 1921: "@ ! 1922: srea. %3,%1,%2 ! 1923: {srai.|srawi.} %3,%1,%h2" ! 1924: [(set_attr "type" "delayed_compare")]) ! 1925: ! 1926: (define_insn "" ! 1927: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 1928: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1929: (match_operand:SI 2 "reg_or_cint_operand" "ri")) ! 1930: (const_int 0))) ! 1931: (clobber (match_scratch:SI 3 "=r"))] ! 1932: "! TARGET_POWER" ! 1933: "sraw%I2. %3,%1,%2" ! 1934: [(set_attr "type" "delayed_compare")]) ! 1935: ! 1936: (define_insn "" ! 1937: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") ! 1938: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 1939: (match_operand:SI 2 "reg_or_cint_operand" "r,i")) ! 1940: (const_int 0))) ! 1941: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 1942: (ashiftrt:SI (match_dup 1) (match_dup 2))) ! 1943: (clobber (match_scratch:SI 4 "=q,X"))] ! 1944: "TARGET_POWER" ! 1945: "@ ! 1946: srea. %0,%1,%2 ! 1947: {srai.|srawi.} %0,%1,%h2" ! 1948: [(set_attr "type" "delayed_compare")]) ! 1949: ! 1950: (define_insn "" ! 1951: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 1952: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 1953: (match_operand:SI 2 "reg_or_cint_operand" "ri")) ! 1954: (const_int 0))) ! 1955: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1956: (ashiftrt:SI (match_dup 1) (match_dup 2)))] ! 1957: "! TARGET_POWER" ! 1958: "sraw%I2. %0,%1,%2" ! 1959: [(set_attr "type" "delayed_compare")]) ! 1960: ! 1961: (define_expand "extendqisi2" ! 1962: [(use (match_operand:SI 0 "gpc_reg_operand" "")) ! 1963: (use (match_operand:QI 1 "gpc_reg_operand" ""))] ! 1964: "" ! 1965: " ! 1966: { ! 1967: if (TARGET_POWER) ! 1968: emit_insn (gen_extendqisi2_power (operands[0], operands[1])); ! 1969: else ! 1970: emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); ! 1971: DONE; ! 1972: }") ! 1973: ! 1974: (define_expand "extendqisi2_power" ! 1975: [(parallel [(set (match_dup 2) ! 1976: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") ! 1977: (const_int 24))) ! 1978: (clobber (scratch:SI))]) ! 1979: (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 1980: (ashiftrt:SI (match_dup 2) ! 1981: (const_int 24))) ! 1982: (clobber (scratch:SI))])] ! 1983: "TARGET_POWER" ! 1984: " ! 1985: { operands[1] = gen_lowpart (SImode, operands[1]); ! 1986: operands[2] = gen_reg_rtx (SImode); }") ! 1987: ! 1988: (define_expand "extendqisi2_no_power" ! 1989: [(set (match_dup 2) ! 1990: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") ! 1991: (const_int 24))) ! 1992: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 1993: (ashiftrt:SI (match_dup 2) ! 1994: (const_int 24)))] ! 1995: "! TARGET_POWER" ! 1996: " ! 1997: { operands[1] = gen_lowpart (SImode, operands[1]); ! 1998: operands[2] = gen_reg_rtx (SImode); }") ! 1999: ! 2000: (define_expand "extendqihi2" ! 2001: [(use (match_operand:HI 0 "gpc_reg_operand" "")) ! 2002: (use (match_operand:QI 1 "gpc_reg_operand" ""))] ! 2003: "" ! 2004: " ! 2005: { ! 2006: if (TARGET_POWER) ! 2007: emit_insn (gen_extendqihi2_power (operands[0], operands[1])); ! 2008: else ! 2009: emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); ! 2010: DONE; ! 2011: }") ! 2012: ! 2013: (define_expand "extendqihi2_power" ! 2014: [(parallel [(set (match_dup 2) ! 2015: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") ! 2016: (const_int 24))) ! 2017: (clobber (scratch:SI))]) ! 2018: (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") ! 2019: (ashiftrt:SI (match_dup 2) ! 2020: (const_int 24))) ! 2021: (clobber (scratch:SI))])] ! 2022: "TARGET_POWER" ! 2023: " ! 2024: { operands[0] = gen_lowpart (SImode, operands[0]); ! 2025: operands[1] = gen_lowpart (SImode, operands[1]); ! 2026: operands[2] = gen_reg_rtx (SImode); }") ! 2027: ! 2028: (define_expand "extendqihi2_no_power" ! 2029: [(set (match_dup 2) ! 2030: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") ! 2031: (const_int 24))) ! 2032: (set (match_operand:HI 0 "gpc_reg_operand" "") ! 2033: (ashiftrt:SI (match_dup 2) ! 2034: (const_int 24)))] ! 2035: "! TARGET_POWER" ! 2036: " ! 2037: { operands[0] = gen_lowpart (SImode, operands[0]); ! 2038: operands[1] = gen_lowpart (SImode, operands[1]); ! 2039: operands[2] = gen_reg_rtx (SImode); }") ! 2040: ! 2041: ;; Floating-point insns, excluding normal data motion. ! 2042: ;; ! 2043: ;; PowerPC has a full set of single-precision floating point instructions. ! 2044: ;; ! 2045: ;; For the POWER architecture, we pretend that we have both SFmode and ! 2046: ;; DFmode insns, while, in fact, all fp insns are actually done in double. ! 2047: ;; The only conversions we will do will be when storing to memory. In that ! 2048: ;; case, we will use the "frsp" instruction before storing. ! 2049: ;; ! 2050: ;; Note that when we store into a single-precision memory location, we need to ! 2051: ;; use the frsp insn first. If the register being stored isn't dead, we ! 2052: ;; need a scratch register for the frsp. But this is difficult when the store ! 2053: ;; is done by reload. It is not incorrect to do the frsp on the register in ! 2054: ;; this case, we just lose precision that we would have otherwise gotten but ! 2055: ;; is not guaranteed. Perhaps this should be tightened up at some point. ! 2056: ! 2057: (define_insn "extendsfdf2" ! 2058: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 2059: (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] ! 2060: "" ! 2061: "* ! 2062: { ! 2063: if (REGNO (operands[0]) == REGNO (operands[1])) ! 2064: return \"\"; ! 2065: else ! 2066: return \"fmr %0,%1\"; ! 2067: }" ! 2068: [(set_attr "type" "fp")]) ! 2069: ! 2070: (define_insn "truncdfsf2" ! 2071: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2072: (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] ! 2073: "" ! 2074: "frsp %0,%1" ! 2075: [(set_attr "type" "fp")]) ! 2076: ! 2077: (define_insn "negsf2" ! 2078: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2079: (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] ! 2080: "" ! 2081: "fneg %0,%1" ! 2082: [(set_attr "type" "fp")]) ! 2083: ! 2084: (define_insn "abssf2" ! 2085: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2086: (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] ! 2087: "" ! 2088: "fabs %0,%1" ! 2089: [(set_attr "type" "fp")]) ! 2090: ! 2091: (define_insn "" ! 2092: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2093: (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] ! 2094: "" ! 2095: "fnabs %0,%1" ! 2096: [(set_attr "type" "fp")]) ! 2097: ! 2098: (define_expand "addsf3" ! 2099: [(set (match_operand:SF 0 "gpc_reg_operand" "") ! 2100: (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") ! 2101: (match_operand:SF 2 "gpc_reg_operand" "")))] ! 2102: "" ! 2103: "") ! 2104: ! 2105: (define_insn "" ! 2106: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2107: (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 2108: (match_operand:SF 2 "gpc_reg_operand" "f")))] ! 2109: "TARGET_POWERPC" ! 2110: "fadds %0,%1,%2" ! 2111: [(set_attr "type" "fp")]) ! 2112: ! 2113: (define_insn "" ! 2114: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2115: (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 2116: (match_operand:SF 2 "gpc_reg_operand" "f")))] ! 2117: "TARGET_POWER" ! 2118: "{fa|fadd} %0,%1,%2" ! 2119: [(set_attr "type" "fp")]) ! 2120: ! 2121: (define_expand "subsf3" ! 2122: [(set (match_operand:SF 0 "gpc_reg_operand" "") ! 2123: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") ! 2124: (match_operand:SF 2 "gpc_reg_operand" "")))] ! 2125: "" ! 2126: "") ! 2127: ! 2128: (define_insn "" ! 2129: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2130: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") ! 2131: (match_operand:SF 2 "gpc_reg_operand" "f")))] ! 2132: "TARGET_POWERPC" ! 2133: "fsubs %0,%1,%2" ! 2134: [(set_attr "type" "fp")]) ! 2135: ! 2136: (define_insn "" ! 2137: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2138: (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") ! 2139: (match_operand:SF 2 "gpc_reg_operand" "f")))] ! 2140: "TARGET_POWER" ! 2141: "{fs|fsub} %0,%1,%2" ! 2142: [(set_attr "type" "fp")]) ! 2143: ! 2144: (define_expand "mulsf3" ! 2145: [(set (match_operand:SF 0 "gpc_reg_operand" "") ! 2146: (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") ! 2147: (match_operand:SF 2 "gpc_reg_operand" "")))] ! 2148: "" ! 2149: "") ! 2150: ! 2151: (define_insn "" ! 2152: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2153: (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 2154: (match_operand:SF 2 "gpc_reg_operand" "f")))] ! 2155: "TARGET_POWERPC" ! 2156: "fmuls %0,%1,%2" ! 2157: [(set_attr "type" "fp")]) ! 2158: ! 2159: (define_insn "" ! 2160: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2161: (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 2162: (match_operand:SF 2 "gpc_reg_operand" "f")))] ! 2163: "TARGET_POWER" ! 2164: "{fm|fmul} %0,%1,%2" ! 2165: [(set_attr "type" "fp")]) ! 2166: ! 2167: (define_expand "divsf3" ! 2168: [(set (match_operand:SF 0 "gpc_reg_operand" "") ! 2169: (div:SF (match_operand:SF 1 "gpc_reg_operand" "") ! 2170: (match_operand:SF 2 "gpc_reg_operand" "")))] ! 2171: "" ! 2172: "") ! 2173: ! 2174: (define_insn "" ! 2175: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2176: (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") ! 2177: (match_operand:SF 2 "gpc_reg_operand" "f")))] ! 2178: "TARGET_POWERPC" ! 2179: "fdivs %0,%1,%2" ! 2180: [(set_attr "type" "sdiv")]) ! 2181: ! 2182: (define_insn "" ! 2183: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2184: (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") ! 2185: (match_operand:SF 2 "gpc_reg_operand" "f")))] ! 2186: "TARGET_POWER" ! 2187: "{fd|fdiv} %0,%1,%2" ! 2188: [(set_attr "type" "sdiv")]) ! 2189: ! 2190: (define_insn "" ! 2191: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2192: (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 2193: (match_operand:SF 2 "gpc_reg_operand" "f")) ! 2194: (match_operand:SF 3 "gpc_reg_operand" "f")))] ! 2195: "TARGET_POWERPC" ! 2196: "fmadds %0,%1,%2,%3" ! 2197: [(set_attr "type" "fp")]) ! 2198: ! 2199: (define_insn "" ! 2200: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2201: (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 2202: (match_operand:SF 2 "gpc_reg_operand" "f")) ! 2203: (match_operand:SF 3 "gpc_reg_operand" "f")))] ! 2204: "TARGET_POWER" ! 2205: "{fma|fmadd} %0,%1,%2,%3" ! 2206: [(set_attr "type" "fp")]) ! 2207: ! 2208: (define_insn "" ! 2209: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2210: (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 2211: (match_operand:SF 2 "gpc_reg_operand" "f")) ! 2212: (match_operand:SF 3 "gpc_reg_operand" "f")))] ! 2213: "TARGET_POWERPC" ! 2214: "fmsubs %0,%1,%2,%3" ! 2215: [(set_attr "type" "fp")]) ! 2216: ! 2217: (define_insn "" ! 2218: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2219: (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 2220: (match_operand:SF 2 "gpc_reg_operand" "f")) ! 2221: (match_operand:SF 3 "gpc_reg_operand" "f")))] ! 2222: "TARGET_POWER" ! 2223: "{fms|fmsub} %0,%1,%2,%3" ! 2224: [(set_attr "type" "fp")]) ! 2225: ! 2226: (define_insn "" ! 2227: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2228: (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 2229: (match_operand:SF 2 "gpc_reg_operand" "f")) ! 2230: (match_operand:SF 3 "gpc_reg_operand" "f"))))] ! 2231: "TARGET_POWERPC" ! 2232: "fnmadds %0,%1,%2,%3" ! 2233: [(set_attr "type" "fp")]) ! 2234: ! 2235: (define_insn "" ! 2236: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2237: (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 2238: (match_operand:SF 2 "gpc_reg_operand" "f")) ! 2239: (match_operand:SF 3 "gpc_reg_operand" "f"))))] ! 2240: "TARGET_POWER" ! 2241: "{fnma|fnmadd} %0,%1,%2,%3" ! 2242: [(set_attr "type" "fp")]) ! 2243: ! 2244: (define_insn "" ! 2245: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2246: (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 2247: (match_operand:SF 2 "gpc_reg_operand" "f")) ! 2248: (match_operand:SF 3 "gpc_reg_operand" "f"))))] ! 2249: "TARGET_POWERPC" ! 2250: "fnmsubs %0,%1,%2,%3" ! 2251: [(set_attr "type" "fp")]) ! 2252: ! 2253: (define_insn "" ! 2254: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2255: (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") ! 2256: (match_operand:SF 2 "gpc_reg_operand" "f")) ! 2257: (match_operand:SF 3 "gpc_reg_operand" "f"))))] ! 2258: "TARGET_POWER" ! 2259: "{fnms|fnmsub} %0,%1,%2,%3" ! 2260: [(set_attr "type" "fp")]) ! 2261: ! 2262: (define_expand "sqrtsf2" ! 2263: [(set (match_operand:SF 0 "gpc_reg_operand" "") ! 2264: (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] ! 2265: "TARGET_POWERPCSQR || TARGET_POWER2" ! 2266: "") ! 2267: ! 2268: (define_insn "" ! 2269: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2270: (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] ! 2271: "TARGET_POWERPCSQR" ! 2272: "fsqrts %0,%1" ! 2273: [(set_attr "type" "ssqrt")]) ! 2274: ! 2275: (define_insn "" ! 2276: [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ! 2277: (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] ! 2278: "TARGET_POWER2" ! 2279: "fsqrt %0,%1" ! 2280: [(set_attr "type" "dsqrt")]) ! 2281: ! 2282: (define_insn "negdf2" ! 2283: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 2284: (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] ! 2285: "" ! 2286: "fneg %0,%1" ! 2287: [(set_attr "type" "fp")]) ! 2288: ! 2289: (define_insn "absdf2" ! 2290: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 2291: (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] ! 2292: "" ! 2293: "fabs %0,%1" ! 2294: [(set_attr "type" "fp")]) ! 2295: ! 2296: (define_insn "" ! 2297: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 2298: (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] ! 2299: "" ! 2300: "fnabs %0,%1" ! 2301: [(set_attr "type" "fp")]) ! 2302: ! 2303: (define_insn "adddf3" ! 2304: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 2305: (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") ! 2306: (match_operand:DF 2 "gpc_reg_operand" "f")))] ! 2307: "" ! 2308: "{fa|fadd} %0,%1,%2" ! 2309: [(set_attr "type" "fp")]) ! 2310: ! 2311: (define_insn "subdf3" ! 2312: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 2313: (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") ! 2314: (match_operand:DF 2 "gpc_reg_operand" "f")))] ! 2315: "" ! 2316: "{fs|fsub} %0,%1,%2" ! 2317: [(set_attr "type" "fp")]) ! 2318: ! 2319: (define_insn "muldf3" ! 2320: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 2321: (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") ! 2322: (match_operand:DF 2 "gpc_reg_operand" "f")))] ! 2323: "" ! 2324: "{fm|fmul} %0,%1,%2" ! 2325: [(set_attr "type" "dmul")]) ! 2326: ! 2327: (define_insn "divdf3" ! 2328: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 2329: (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") ! 2330: (match_operand:DF 2 "gpc_reg_operand" "f")))] ! 2331: "" ! 2332: "{fd|fdiv} %0,%1,%2" ! 2333: [(set_attr "type" "ddiv")]) ! 2334: ! 2335: (define_insn "" ! 2336: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 2337: (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") ! 2338: (match_operand:DF 2 "gpc_reg_operand" "f")) ! 2339: (match_operand:DF 3 "gpc_reg_operand" "f")))] ! 2340: "" ! 2341: "{fma|fmadd} %0,%1,%2,%3" ! 2342: [(set_attr "type" "dmul")]) ! 2343: ! 2344: (define_insn "" ! 2345: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 2346: (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") ! 2347: (match_operand:DF 2 "gpc_reg_operand" "f")) ! 2348: (match_operand:DF 3 "gpc_reg_operand" "f")))] ! 2349: "" ! 2350: "{fms|fmsub} %0,%1,%2,%3" ! 2351: [(set_attr "type" "dmul")]) ! 2352: ! 2353: (define_insn "" ! 2354: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 2355: (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") ! 2356: (match_operand:DF 2 "gpc_reg_operand" "f")) ! 2357: (match_operand:DF 3 "gpc_reg_operand" "f"))))] ! 2358: "" ! 2359: "{fnma|fnmadd} %0,%1,%2,%3" ! 2360: [(set_attr "type" "dmul")]) ! 2361: ! 2362: (define_insn "" ! 2363: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 2364: (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") ! 2365: (match_operand:DF 2 "gpc_reg_operand" "f")) ! 2366: (match_operand:DF 3 "gpc_reg_operand" "f"))))] ! 2367: "" ! 2368: "{fnms|fnmsub} %0,%1,%2,%3" ! 2369: [(set_attr "type" "dmul")]) ! 2370: ! 2371: (define_insn "sqrtdf2" ! 2372: [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ! 2373: (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] ! 2374: "TARGET_POWERPCSQR || TARGET_POWER2" ! 2375: "fsqrt %0,%1" ! 2376: [(set_attr "type" "dsqrt")]) ! 2377: ! 2378: ;; Conversions to and from floating-point. ! 2379: (define_expand "floatsidf2" ! 2380: [(set (match_dup 2) ! 2381: (plus:DI (zero_extend:DI ! 2382: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 2383: (match_dup 3))) ! 2384: (match_dup 4))) ! 2385: (set (match_operand:DF 0 "gpc_reg_operand" "") ! 2386: (minus:DF (subreg:DF (match_dup 2) 0) ! 2387: (match_dup 5)))] ! 2388: "" ! 2389: " ! 2390: { ! 2391: #if HOST_BITS_PER_INT != BITS_PER_WORD ! 2392: /* Maybe someone can figure out how to do this in that case. I don't ! 2393: want to right now. */ ! 2394: abort (); ! 2395: #endif ! 2396: ! 2397: operands[2] = gen_reg_rtx (DImode); ! 2398: operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000); ! 2399: operands[4] = immed_double_const (0, 0x43300000, DImode); ! 2400: operands[5] = force_reg (DFmode, immed_double_const (0x43300000, ! 2401: 0x80000000, DFmode)); ! 2402: }") ! 2403: ! 2404: (define_expand "floatunssidf2" ! 2405: [(set (match_dup 2) ! 2406: (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) ! 2407: (match_dup 3))) ! 2408: (set (match_operand:DF 0 "gpc_reg_operand" "") ! 2409: (minus:DF (subreg:DF (match_dup 2) 0) ! 2410: (match_dup 4)))] ! 2411: "" ! 2412: " ! 2413: { ! 2414: #if HOST_BITS_PER_INT != BITS_PER_WORD ! 2415: /* Maybe someone can figure out how to do this in that case. I don't ! 2416: want to right now. */ ! 2417: abort (); ! 2418: #endif ! 2419: ! 2420: operands[2] = gen_reg_rtx (DImode); ! 2421: operands[3] = immed_double_const (0, 0x43300000, DImode); ! 2422: operands[4] = force_reg (DFmode, immed_double_const (0x43300000, 0, DFmode)); ! 2423: }") ! 2424: ! 2425: ;; For the above two cases, we always split. ! 2426: (define_split ! 2427: [(set (match_operand:DI 0 "gpc_reg_operand" "") ! 2428: (plus:DI (zero_extend:DI ! 2429: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") ! 2430: (match_operand:SI 2 "logical_operand" ""))) ! 2431: (match_operand:DI 3 "immediate_operand" "")))] ! 2432: "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD ! 2433: && GET_CODE (operands[3]) == CONST_DOUBLE ! 2434: && CONST_DOUBLE_LOW (operands[3]) == 0" ! 2435: [(set (match_dup 6) (xor:SI (match_dup 1) (match_dup 2))) ! 2436: (set (match_dup 4) (match_dup 5))] ! 2437: " ! 2438: { operands[4] = operand_subword (operands[0], 0, 0, DImode); ! 2439: operands[5] = operand_subword (operands[3], 0, 0, DImode); ! 2440: operands[6] = operand_subword (operands[0], 1, 0, DImode); ! 2441: }") ! 2442: ! 2443: (define_insn "" ! 2444: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 2445: (plus:DI (zero_extend:DI ! 2446: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") ! 2447: (match_operand:SI 2 "logical_operand" "rKJ"))) ! 2448: (match_operand:DI 3 "immediate_operand" "n")))] ! 2449: "HOST_BITS_PER_INT == BITS_PER_WORD ! 2450: && GET_CODE (operands[3]) == CONST_DOUBLE ! 2451: && CONST_DOUBLE_LOW (operands[3]) == 0" ! 2452: "#" ! 2453: [(set_attr "length" "8")]) ! 2454: ! 2455: (define_split ! 2456: [(set (match_operand:DI 0 "gpc_reg_operand" "=") ! 2457: (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) ! 2458: (match_operand:DI 2 "immediate_operand" "")))] ! 2459: "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD ! 2460: && GET_CODE (operands[2]) == CONST_DOUBLE ! 2461: && CONST_DOUBLE_LOW (operands[2]) == 0" ! 2462: [(set (match_dup 3) (match_dup 4)) ! 2463: (set (match_dup 5) (match_dup 1))] ! 2464: " ! 2465: { operands[3] = operand_subword (operands[0], 0, 0, DImode); ! 2466: operands[4] = operand_subword (operands[2], 0, 0, DImode); ! 2467: operands[5] = operand_subword (operands[0], 1, 0, DImode); ! 2468: ! 2469: if (rtx_equal_p (operands[1], operands[5])) ! 2470: { ! 2471: emit_move_insn (operands[3], operands[4]); ! 2472: DONE; ! 2473: } ! 2474: ! 2475: if (rtx_equal_p (operands[1], operands[3])) ! 2476: { ! 2477: rtx temp; ! 2478: ! 2479: temp = operands[3]; operands[3] = operands[5]; operands[5] = temp; ! 2480: temp = operands[4]; operands[4] = operands[1]; operands[1] = temp; ! 2481: } ! 2482: }") ! 2483: ! 2484: (define_insn "" ! 2485: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 2486: (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 2487: (match_operand:DI 2 "immediate_operand" "n")))] ! 2488: "HOST_BITS_PER_INT == BITS_PER_WORD ! 2489: && GET_CODE (operands[2]) == CONST_DOUBLE ! 2490: && CONST_DOUBLE_LOW (operands[2]) == 0" ! 2491: "#" ! 2492: [(set_attr "length" "8")]) ! 2493: ! 2494: (define_expand "fix_truncdfsi2" ! 2495: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 2496: (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))] ! 2497: "" ! 2498: " ! 2499: { ! 2500: emit_insn (gen_trunc_call (operands[0], operands[1], ! 2501: gen_rtx (SYMBOL_REF, Pmode, \"itrunc\"))); ! 2502: DONE; ! 2503: }") ! 2504: ! 2505: (define_expand "fixuns_truncdfsi2" ! 2506: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 2507: (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))] ! 2508: "" ! 2509: " ! 2510: { ! 2511: emit_insn (gen_trunc_call (operands[0], operands[1], ! 2512: gen_rtx (SYMBOL_REF, Pmode, \"uitrunc\"))); ! 2513: DONE; ! 2514: }") ! 2515: ! 2516: ! 2517: (define_expand "trunc_call" ! 2518: [(parallel [(set (match_operand:SI 0 "" "") ! 2519: (fix:SI (match_operand:DF 1 "" ""))) ! 2520: (use (match_operand:SI 2 "" ""))])] ! 2521: "" ! 2522: " ! 2523: { ! 2524: rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]); ! 2525: rtx first = XVECEXP (insns, 0, 0); ! 2526: rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1); ! 2527: ! 2528: REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last, ! 2529: REG_NOTES (first)); ! 2530: REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last)); ! 2531: ! 2532: emit_insn (insns); ! 2533: DONE; ! 2534: }") ! 2535: ! 2536: (define_expand "trunc_call_rtl" ! 2537: [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" "")) ! 2538: (use (reg:DF 33)) ! 2539: (parallel [(set (reg:SI 3) ! 2540: (call (mem:SI (match_operand 2 "" "")) (const_int 0))) ! 2541: (clobber (scratch:SI))]) ! 2542: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 2543: (reg:SI 3))] ! 2544: "" ! 2545: " ! 2546: { ! 2547: rs6000_trunc_used = 1; ! 2548: }") ! 2549: ! 2550: ;; Define the DImode operations that can be done in a small number ! 2551: ;; of instructions. ! 2552: (define_expand "adddi3" ! 2553: [(set (match_operand:DI 0 "gpc_reg_operand" "") ! 2554: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") ! 2555: (match_operand:DI 2 "reg_or_short_operand" "")))] ! 2556: "" ! 2557: " ! 2558: { ! 2559: if (! TARGET_POWER ! 2560: && short_cint_operand (operands[2], DImode)) ! 2561: FAIL; ! 2562: }") ! 2563: ! 2564: (define_insn "" ! 2565: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") ! 2566: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") ! 2567: (match_operand:DI 2 "reg_or_short_operand" "r,I")))] ! 2568: "TARGET_POWER" ! 2569: "@ ! 2570: {a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2 ! 2571: {ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1" ! 2572: [(set_attr "length" "8")]) ! 2573: ! 2574: (define_insn "" ! 2575: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 2576: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r") ! 2577: (match_operand:DI 2 "gpc_reg_operand" "r")))] ! 2578: "! TARGET_POWER" ! 2579: "addc %L0,%L1,%L2\;adde %0,%1,%2" ! 2580: [(set_attr "length" "8")]) ! 2581: ! 2582: (define_expand "subdi3" ! 2583: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") ! 2584: (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") ! 2585: (match_operand:DI 2 "gpc_reg_operand" "r,r")))] ! 2586: "" ! 2587: " ! 2588: { ! 2589: if (! TARGET_POWER ! 2590: && short_cint_operand (operands[1], DImode)) ! 2591: FAIL; ! 2592: }") ! 2593: ! 2594: (define_insn "" ! 2595: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") ! 2596: (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") ! 2597: (match_operand:DI 2 "gpc_reg_operand" "r,r")))] ! 2598: "TARGET_POWER" ! 2599: "@ ! 2600: {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1 ! 2601: {sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2" ! 2602: [(set_attr "length" "8")]) ! 2603: ! 2604: (define_insn "" ! 2605: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 2606: (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") ! 2607: (match_operand:DI 2 "gpc_reg_operand" "r")))] ! 2608: "! TARGET_POWER" ! 2609: "subfc %L0,%L2,%L1\;subfe %0,%2,%1" ! 2610: [(set_attr "length" "8")]) ! 2611: ! 2612: (define_expand "negdi2" ! 2613: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 2614: (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] ! 2615: "" ! 2616: "") ! 2617: ! 2618: (define_insn "" ! 2619: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 2620: (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] ! 2621: "" ! 2622: "{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1" ! 2623: [(set_attr "length" "8")]) ! 2624: ! 2625: (define_insn "mulsidi3" ! 2626: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") ! 2627: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 2628: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) ! 2629: (clobber (match_scratch:SI 3 "=q"))] ! 2630: "TARGET_POWER" ! 2631: "mul %0,%1,%2\;mfmq %L0" ! 2632: [(set_attr "length" "8")]) ! 2633: ! 2634: ;; If operands 0 and 2 are in the same register, we have a problem. But ! 2635: ;; operands 0 and 1 (the usual case) can be in the same register. That's ! 2636: ;; why we have the strange constraints below. ! 2637: (define_insn "ashldi3" ! 2638: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") ! 2639: (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") ! 2640: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) ! 2641: (clobber (match_scratch:SI 3 "=X,q,q,q"))] ! 2642: "TARGET_POWER" ! 2643: "@ ! 2644: {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} ! 2645: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 ! 2646: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 ! 2647: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" ! 2648: [(set_attr "length" "8")]) ! 2649: ! 2650: (define_insn "lshrdi3" ! 2651: [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r") ! 2652: (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") ! 2653: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) ! 2654: (clobber (match_scratch:SI 3 "=X,q,q,q"))] ! 2655: "TARGET_POWER" ! 2656: "@ ! 2657: {cal %0,0(0)|li %0,0}\;{s%A2i|s%A2wi} %L0,%1,%h2 ! 2658: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 ! 2659: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 ! 2660: sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" ! 2661: [(set_attr "length" "8")]) ! 2662: ! 2663: ;; Shift by a variable amount is too complex to be worth open-coding. We ! 2664: ;; just handle shifts by constants. ! 2665: ! 2666: (define_expand "ashrdi3" ! 2667: [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=") ! 2668: (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") ! 2669: (match_operand:SI 2 "general_operand" ""))) ! 2670: (clobber (match_scratch:SI 3 ""))])] ! 2671: "TARGET_POWER" ! 2672: " ! 2673: { if (GET_CODE (operands[2]) != CONST_INT) ! 2674: FAIL; ! 2675: }") ! 2676: ! 2677: (define_insn "" ! 2678: [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") ! 2679: (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") ! 2680: (match_operand:SI 2 "const_int_operand" "M,i"))) ! 2681: (clobber (match_scratch:SI 3 "=X,q"))] ! 2682: "TARGET_POWER" ! 2683: "@ ! 2684: {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 ! 2685: sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" ! 2686: [(set_attr "length" "8")]) ! 2687: ! 2688: ;; Now define ways of moving data around. ! 2689: ;; ! 2690: ;; For SI, we special-case integers that can't be loaded in one insn. We ! 2691: ;; do the load 16-bits at a time. We could do this by loading from memory, ! 2692: ;; and this is even supposed to be faster, but it is simpler not to get ! 2693: ;; integers in the TOC. ! 2694: (define_expand "movsi" ! 2695: [(set (match_operand:SI 0 "general_operand" "") ! 2696: (match_operand:SI 1 "any_operand" ""))] ! 2697: "" ! 2698: " ! 2699: { ! 2700: if (GET_CODE (operands[0]) != REG) ! 2701: operands[1] = force_reg (SImode, operands[1]); ! 2702: ! 2703: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT ! 2704: && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])) ! 2705: { ! 2706: operands[1] = force_const_mem (SImode, operands[1]); ! 2707: if (! memory_address_p (SImode, XEXP (operands[1], 0)) ! 2708: && ! reload_in_progress) ! 2709: operands[1] = change_address (operands[1], SImode, ! 2710: XEXP (operands[1], 0)); ! 2711: } ! 2712: ! 2713: if (GET_CODE (operands[1]) == CONST_INT ! 2714: && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000 ! 2715: && (INTVAL (operands[1]) & 0xffff) != 0) ! 2716: { ! 2717: emit_move_insn (operands[0], ! 2718: gen_rtx (CONST_INT, VOIDmode, ! 2719: INTVAL (operands[1]) & 0xffff0000)); ! 2720: emit_insn (gen_iorsi3 (operands[0], operands[0], ! 2721: gen_rtx (CONST_INT, VOIDmode, ! 2722: INTVAL (operands[1]) & 0xffff))); ! 2723: DONE; ! 2724: } ! 2725: }") ! 2726: ! 2727: (define_insn "" ! 2728: [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*c*q,*l,*h") ! 2729: (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r,0"))] ! 2730: "TARGET_POWER && (gpc_reg_operand (operands[0], SImode) ! 2731: || gpc_reg_operand (operands[1], SImode))" ! 2732: "@ ! 2733: {ai|addic} %0,%1,0 ! 2734: {l%U1%X1|lwz%U1%X1} %0,%1 ! 2735: {st%U0%X0|stw%U0%X0} %1,%0 ! 2736: {cal %0,%1(0)|li %0,%1} ! 2737: {cau %0,0,%u1|lis %0,%u1} ! 2738: mf%1 %0 ! 2739: mt%0 %1 ! 2740: mt%0 %1 ! 2741: cror 0,0,0" ! 2742: [(set_attr "type" "*,load,*,*,*,*,*,mtlr,*")]) ! 2743: ! 2744: (define_insn "" ! 2745: [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*h") ! 2746: (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r"))] ! 2747: "! TARGET_POWER && (gpc_reg_operand (operands[0], SImode) ! 2748: || gpc_reg_operand (operands[1], SImode))" ! 2749: "@ ! 2750: mr %0,%1 ! 2751: lwz%U1%X1 %0,%1 ! 2752: stw%U0%X0 %1,%0 ! 2753: li %0,%1 ! 2754: lis %0,%u1 ! 2755: mf%1 %0 ! 2756: mt%0 %1" ! 2757: [(set_attr "type" "*,load,*,*,*,*,*")]) ! 2758: ! 2759: ;; Split a load of a large constant into the appropriate two-insn ! 2760: ;; sequence. ! 2761: ! 2762: (define_split ! 2763: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 2764: (match_operand:SI 1 "const_int_operand" ""))] ! 2765: "(unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000 ! 2766: && (INTVAL (operands[1]) & 0xffff) != 0" ! 2767: [(set (match_dup 0) ! 2768: (match_dup 2)) ! 2769: (set (match_dup 0) ! 2770: (ior:SI (match_dup 0) ! 2771: (match_dup 3)))] ! 2772: " ! 2773: { ! 2774: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 2775: INTVAL (operands[1]) & 0xffff0000); ! 2776: operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff); ! 2777: }") ! 2778: ! 2779: (define_insn "" ! 2780: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 2781: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") ! 2782: (const_int 0))) ! 2783: (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] ! 2784: "" ! 2785: "{ai.|addic.} %0,%1,0" ! 2786: [(set_attr "type" "compare")]) ! 2787: ! 2788: (define_expand "movhi" ! 2789: [(set (match_operand:HI 0 "general_operand" "") ! 2790: (match_operand:HI 1 "any_operand" ""))] ! 2791: "" ! 2792: " ! 2793: { ! 2794: if (GET_CODE (operands[0]) != REG) ! 2795: operands[1] = force_reg (HImode, operands[1]); ! 2796: ! 2797: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT) ! 2798: { ! 2799: operands[1] = force_const_mem (HImode, operands[1]); ! 2800: if (! memory_address_p (HImode, XEXP (operands[1], 0)) ! 2801: && ! reload_in_progress) ! 2802: operands[1] = change_address (operands[1], HImode, ! 2803: XEXP (operands[1], 0)); ! 2804: } ! 2805: }") ! 2806: ! 2807: (define_insn "" ! 2808: [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h") ! 2809: (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))] ! 2810: "TARGET_POWER && (gpc_reg_operand (operands[0], HImode) ! 2811: || gpc_reg_operand (operands[1], HImode))" ! 2812: "@ ! 2813: {oril|ori} %0,%1,0 ! 2814: lhz%U1%X1 %0,%1 ! 2815: sth%U0%X0 %1,%0 ! 2816: {cal %0,%w1(0)|li %0,%w1} ! 2817: mf%1 %0 ! 2818: mt%0 %1 ! 2819: cror 0,0,0" ! 2820: [(set_attr "type" "*,load,*,*,*,*,*")]) ! 2821: ! 2822: (define_insn "" ! 2823: [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h") ! 2824: (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))] ! 2825: "! TARGET_POWER && (gpc_reg_operand (operands[0], HImode) ! 2826: || gpc_reg_operand (operands[1], HImode))" ! 2827: "@ ! 2828: ori %0,%1,0 ! 2829: lhz%U1%X1 %0,%1 ! 2830: sth%U0%X0 %1,%0 ! 2831: li %0,%w1 ! 2832: mf%1 %0 ! 2833: mt%0 %1" ! 2834: [(set_attr "type" "*,load,*,*,*,*")]) ! 2835: ! 2836: (define_expand "movqi" ! 2837: [(set (match_operand:QI 0 "general_operand" "") ! 2838: (match_operand:QI 1 "any_operand" ""))] ! 2839: "" ! 2840: " ! 2841: { ! 2842: if (GET_CODE (operands[0]) != REG) ! 2843: operands[1] = force_reg (QImode, operands[1]); ! 2844: ! 2845: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT) ! 2846: { ! 2847: operands[1] = force_const_mem (QImode, operands[1]); ! 2848: if (! memory_address_p (QImode, XEXP (operands[1], 0)) ! 2849: && ! reload_in_progress) ! 2850: operands[1] = change_address (operands[1], QImode, ! 2851: XEXP (operands[1], 0)); ! 2852: } ! 2853: }") ! 2854: ! 2855: (define_insn "" ! 2856: [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h") ! 2857: (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))] ! 2858: "TARGET_POWER && (gpc_reg_operand (operands[0], QImode) ! 2859: || gpc_reg_operand (operands[1], QImode))" ! 2860: "@ ! 2861: {oril|ori} %0,%1,0 ! 2862: lbz%U1%X1 %0,%1 ! 2863: stb%U0%X0 %1,%0 ! 2864: {cal %0,%1(0)|li %0,%1} ! 2865: mf%1 %0 ! 2866: mt%0 %1 ! 2867: cror 0,0,0" ! 2868: [(set_attr "type" "*,load,*,*,*,*,*")]) ! 2869: ! 2870: (define_insn "" ! 2871: [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h") ! 2872: (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))] ! 2873: "! TARGET_POWER && (gpc_reg_operand (operands[0], QImode) ! 2874: || gpc_reg_operand (operands[1], QImode))" ! 2875: "@ ! 2876: mr %0,%1 ! 2877: lbz%U1%X1 %0,%1 ! 2878: stb%U0%X0 %1,%0 ! 2879: li %0,%1 ! 2880: mf%1 %0 ! 2881: mt%0 %1" ! 2882: [(set_attr "type" "*,load,*,*,*,*")]) ! 2883: ! 2884: ;; Here is how to move condition codes around. When we store CC data in ! 2885: ;; an integer register or memory, we store just the high-order 4 bits. ! 2886: ;; This lets us not shift in the most common case of CR0. ! 2887: (define_expand "movcc" ! 2888: [(set (match_operand:CC 0 "nonimmediate_operand" "") ! 2889: (match_operand:CC 1 "nonimmediate_operand" ""))] ! 2890: "" ! 2891: "") ! 2892: ! 2893: (define_insn "" ! 2894: [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") ! 2895: (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] ! 2896: "register_operand (operands[0], CCmode) ! 2897: || register_operand (operands[1], CCmode)" ! 2898: "@ ! 2899: mcrf %0,%1 ! 2900: mtcrf 128,%1 ! 2901: {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff ! 2902: mfcr %0 ! 2903: mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 ! 2904: {ai %0,%1,0|mr %0,%1} ! 2905: {l%U1%X1|lwz%U1%X1} %0,%1 ! 2906: {st%U0%U1|stw%U0%U1} %1,%0" ! 2907: [(set_attr "type" "*,*,*,compare,*,*,load,*") ! 2908: (set_attr "length" "*,*,12,*,8,*,*,*")]) ! 2909: ! 2910: ;; For floating-point, we normally deal with the floating-point registers. ! 2911: ;; The sole exception is that parameter passing can produce floating-point ! 2912: ;; values in fixed-point registers. Unless the value is a simple constant ! 2913: ;; or already in memory, we deal with this by allocating memory and copying ! 2914: ;; the value explicitly via that memory location. ! 2915: (define_expand "movsf" ! 2916: [(set (match_operand:SF 0 "nonimmediate_operand" "") ! 2917: (match_operand:SF 1 "any_operand" ""))] ! 2918: "" ! 2919: " ! 2920: { ! 2921: /* If we are called from reload, we might be getting a SUBREG of a hard ! 2922: reg. So expand it. */ ! 2923: if (GET_CODE (operands[0]) == SUBREG ! 2924: && GET_CODE (SUBREG_REG (operands[0])) == REG ! 2925: && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER) ! 2926: operands[0] = alter_subreg (operands[0]); ! 2927: if (GET_CODE (operands[1]) == SUBREG ! 2928: && GET_CODE (SUBREG_REG (operands[1])) == REG ! 2929: && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER) ! 2930: operands[1] = alter_subreg (operands[1]); ! 2931: ! 2932: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32) ! 2933: { ! 2934: rtx stack_slot; ! 2935: ! 2936: /* If this is a store to memory or another integer register do the ! 2937: move directly. Otherwise store to a temporary stack slot and ! 2938: load from there into a floating point register. */ ! 2939: ! 2940: if (GET_CODE (operands[0]) == MEM ! 2941: || (GET_CODE (operands[0]) == REG ! 2942: && (REGNO (operands[0]) < 32 ! 2943: || (reload_in_progress ! 2944: && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)))) ! 2945: { ! 2946: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode), ! 2947: operand_subword (operands[1], 0, 0, SFmode)); ! 2948: DONE; ! 2949: } ! 2950: ! 2951: stack_slot = gen_rtx (MEM, SFmode, plus_constant (stack_pointer_rtx, 4)); ! 2952: emit_move_insn (stack_slot, operands[1]); ! 2953: emit_move_insn (operands[0], stack_slot); ! 2954: DONE; ! 2955: } ! 2956: ! 2957: if (GET_CODE (operands[0]) == MEM) ! 2958: operands[1] = force_reg (SFmode, operands[1]); ! 2959: ! 2960: if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) ! 2961: { ! 2962: rtx stack_slot; ! 2963: ! 2964: if (GET_CODE (operands[1]) == MEM ! 2965: #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE) ! 2966: || GET_CODE (operands[1]) == CONST_DOUBLE ! 2967: #endif ! 2968: || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32) ! 2969: || (reload_in_progress && GET_CODE (operands[1]) == REG ! 2970: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)) ! 2971: { ! 2972: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode), ! 2973: operand_subword (operands[1], 0, 0, SFmode)); ! 2974: DONE; ! 2975: } ! 2976: ! 2977: if (reload_in_progress) ! 2978: stack_slot = gen_rtx (MEM, SFmode, ! 2979: plus_constant (stack_pointer_rtx, 4)); ! 2980: else ! 2981: stack_slot = assign_stack_temp (SFmode, 4, 0); ! 2982: emit_move_insn (stack_slot, operands[1]); ! 2983: emit_move_insn (operands[0], stack_slot); ! 2984: DONE; ! 2985: } ! 2986: ! 2987: if (CONSTANT_P (operands[1])) ! 2988: { ! 2989: operands[1] = force_const_mem (SFmode, operands[1]); ! 2990: if (! memory_address_p (SFmode, XEXP (operands[1], 0)) ! 2991: && ! reload_in_progress) ! 2992: operands[1] = change_address (operands[1], SFmode, ! 2993: XEXP (operands[1], 0)); ! 2994: } ! 2995: }") ! 2996: ! 2997: (define_split ! 2998: [(set (match_operand:SF 0 "gpc_reg_operand" "") ! 2999: (match_operand:SF 1 "easy_fp_constant" ""))] ! 3000: "reload_completed && REGNO (operands[0]) <= 31" ! 3001: [(set (match_dup 2) (match_dup 3))] ! 3002: " ! 3003: { operands[2] = operand_subword (operands[0], 0, 0, SFmode); ! 3004: operands[3] = operand_subword (operands[1], 0, 0, SFmode); }") ! 3005: ! 3006: (define_insn "" ! 3007: [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m") ! 3008: (match_operand:SF 1 "input_operand" "f,m,f"))] ! 3009: "gpc_reg_operand (operands[0], SFmode) ! 3010: || gpc_reg_operand (operands[1], SFmode)" ! 3011: "@ ! 3012: fmr %0,%1 ! 3013: lfs%U1%X1 %0,%1 ! 3014: frsp %1,%1\;stfs%U0%X0 %1,%0" ! 3015: [(set_attr "type" "fp,fpload,*") ! 3016: (set_attr "length" "*,*,8")]) ! 3017: ! 3018: (define_expand "movdf" ! 3019: [(set (match_operand:DF 0 "nonimmediate_operand" "") ! 3020: (match_operand:DF 1 "any_operand" ""))] ! 3021: "" ! 3022: " ! 3023: { ! 3024: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) ! 3025: { ! 3026: emit_move_insn (operand_subword (operands[0], 1, 1, DFmode), ! 3027: operand_subword_force (operands[1], 1, DFmode)); ! 3028: emit_move_insn (operand_subword (operands[0], 0, 1, DFmode), ! 3029: operand_subword_force (operands[1], 0, DFmode)); ! 3030: DONE; ! 3031: } ! 3032: ! 3033: if (GET_CODE (operands[0]) != REG) ! 3034: operands[1] = force_reg (DFmode, operands[1]); ! 3035: ! 3036: if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode)) ! 3037: { ! 3038: operands[1] = force_const_mem (DFmode, operands[1]); ! 3039: if (! memory_address_p (DFmode, XEXP (operands[1], 0)) ! 3040: && ! reload_in_progress) ! 3041: operands[1] = change_address (operands[1], DFmode, ! 3042: XEXP (operands[1], 0)); ! 3043: } ! 3044: }") ! 3045: ! 3046: (define_split ! 3047: [(set (match_operand:DF 0 "gpc_reg_operand" "") ! 3048: (match_operand:DF 1 "easy_fp_constant" ""))] ! 3049: "reload_completed && REGNO (operands[0]) <= 31" ! 3050: [(set (match_dup 2) (match_dup 3)) ! 3051: (set (match_dup 4) (match_dup 5))] ! 3052: " ! 3053: { operands[2] = operand_subword (operands[0], 0, 0, DFmode); ! 3054: operands[3] = operand_subword (operands[1], 0, 0, DFmode); ! 3055: operands[4] = operand_subword (operands[0], 1, 0, DFmode); ! 3056: operands[5] = operand_subword (operands[1], 1, 0, DFmode); }") ! 3057: ! 3058: ;; Don't have reload use general registers to load a constant. First, ! 3059: ;; it might not work if the output operand has is the equivalent of ! 3060: ;; a non-offsettable memref, but also it is less efficient than loading ! 3061: ;; the constant into an FP register, since it will probably be used there. ! 3062: ;; The "??" is a kludge until we can figure out a more reasonable way ! 3063: ;; of handling these non-offsettable values. ! 3064: (define_insn "" ! 3065: [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m") ! 3066: (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))] ! 3067: "register_operand (operands[0], DFmode) ! 3068: || register_operand (operands[1], DFmode)" ! 3069: "* ! 3070: { ! 3071: switch (which_alternative) ! 3072: { ! 3073: case 0: ! 3074: /* We normally copy the low-numbered register first. However, if ! 3075: the first register operand 0 is the same as the second register of ! 3076: operand 1, we must copy in the opposite order. */ ! 3077: if (REGNO (operands[0]) == REGNO (operands[1]) + 1) ! 3078: return \"{oril %L0,%L1,0|mr %L0,%L1}\;{oril %0,%1,0|mr %0,%1}\"; ! 3079: else ! 3080: return \"{oril %0,%1,0|mr %0,%1}\;{oril %L0,%L1,0|mr %L0,%L1}\"; ! 3081: case 1: ! 3082: /* If the low-address word is used in the address, we must load it ! 3083: last. Otherwise, load it first. Note that we cannot have ! 3084: auto-increment in that case since the address register is known to be ! 3085: dead. */ ! 3086: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, ! 3087: operands [1], 0)) ! 3088: return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; ! 3089: else ! 3090: return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; ! 3091: case 2: ! 3092: return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; ! 3093: case 3: ! 3094: return \"#\"; ! 3095: case 4: ! 3096: return \"fmr %0,%1\"; ! 3097: case 5: ! 3098: return \"lfd%U1%X1 %0,%1\"; ! 3099: case 6: ! 3100: return \"stfd%U0%X0 %1,%0\"; ! 3101: } ! 3102: }" ! 3103: [(set_attr "type" "*,load,*,*,fp,fpload,*") ! 3104: (set_attr "length" "8,8,8,8,*,*,*")]) ! 3105: ! 3106: ;; Next come the multi-word integer load and store and the load and store ! 3107: ;; multiple insns. ! 3108: (define_expand "movdi" ! 3109: [(set (match_operand:DI 0 "general_operand" "") ! 3110: (match_operand:DI 1 "general_operand" ""))] ! 3111: "" ! 3112: " ! 3113: { ! 3114: if (GET_CODE (operands[1]) == CONST_DOUBLE ! 3115: || GET_CODE (operands[1]) == CONST_INT) ! 3116: { ! 3117: emit_move_insn (operand_subword (operands[0], 0, 0, DImode), ! 3118: operand_subword (operands[1], 0, 0, DImode)); ! 3119: emit_move_insn (operand_subword (operands[0], 1, 0, DImode), ! 3120: operand_subword (operands[1], 1, 0, DImode)); ! 3121: DONE; ! 3122: } ! 3123: ! 3124: if (GET_CODE (operands[0]) == MEM) ! 3125: operands[1] = force_reg (DImode, operands[1]); ! 3126: }") ! 3127: ! 3128: (define_insn "" ! 3129: [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m") ! 3130: (match_operand:DI 1 "input_operand" "r,m,r"))] ! 3131: "gpc_reg_operand (operands[0], DImode) ! 3132: || gpc_reg_operand (operands[1], DImode)" ! 3133: "* ! 3134: { ! 3135: switch (which_alternative) ! 3136: { ! 3137: case 0: ! 3138: /* We normally copy the low-numbered register first. However, if ! 3139: the first register operand 0 is the same as the second register of ! 3140: operand 1, we must copy in the opposite order. */ ! 3141: if (REGNO (operands[0]) == REGNO (operands[1]) + 1) ! 3142: return \"{oril %L0,%L1,0|mr %L0,%L1}\;{oril %0,%1,0|mr %0,%1}\"; ! 3143: else ! 3144: return \"{oril %0,%1,0|mr %0,%1}\;{oril %L0,%L1,0|mr %L0,%L1}\"; ! 3145: case 1: ! 3146: /* If the low-address word is used in the address, we must load it ! 3147: last. Otherwise, load it first. Note that we cannot have ! 3148: auto-increment in that case since the address register is known to be ! 3149: dead. */ ! 3150: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, ! 3151: operands [1], 0)) ! 3152: return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; ! 3153: else ! 3154: return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; ! 3155: case 2: ! 3156: return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; ! 3157: } ! 3158: }" ! 3159: [(set_attr "type" "*,load,*") ! 3160: (set_attr "length" "8")]) ! 3161: ! 3162: ;; TImode is similar, except that we usually want to compute the address into ! 3163: ;; a register and use lsi/stsi (the exception is during reload). MQ is also ! 3164: ;; clobbered in stsi for POWER, so we need a SCRATCH for it. ! 3165: (define_expand "movti" ! 3166: [(parallel [(set (match_operand:TI 0 "general_operand" "") ! 3167: (match_operand:TI 1 "general_operand" "")) ! 3168: (clobber (scratch:SI))])] ! 3169: "TARGET_POWER" ! 3170: " ! 3171: { ! 3172: if (GET_CODE (operands[0]) == MEM) ! 3173: operands[1] = force_reg (TImode, operands[1]); ! 3174: ! 3175: if (GET_CODE (operands[0]) == MEM ! 3176: && GET_CODE (XEXP (operands[0], 0)) != REG ! 3177: && ! reload_in_progress) ! 3178: operands[0] = change_address (operands[0], TImode, ! 3179: copy_addr_to_reg (XEXP (operands[0], 0))); ! 3180: ! 3181: if (GET_CODE (operands[1]) == MEM ! 3182: && GET_CODE (XEXP (operands[1], 0)) != REG ! 3183: && ! reload_in_progress) ! 3184: operands[1] = change_address (operands[1], TImode, ! 3185: copy_addr_to_reg (XEXP (operands[1], 0))); ! 3186: }") ! 3187: ! 3188: ;; We say that MQ is clobbered in the last alternative because the first ! 3189: ;; alternative would never get used otherwise since it would need a reload ! 3190: ;; while the 2nd alternative would not. We put memory cases first so they ! 3191: ;; are preferred. Otherwise, we'd try to reload the output instead of ! 3192: ;; giving the SCRATCH mq. ! 3193: (define_insn "" ! 3194: [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r") ! 3195: (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) ! 3196: (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] ! 3197: "TARGET_POWER && (gpc_reg_operand (operands[0], TImode) ! 3198: || gpc_reg_operand (operands[1], TImode))" ! 3199: "* ! 3200: { ! 3201: switch (which_alternative) ! 3202: { ! 3203: case 0: ! 3204: return \"{stsi|stswi} %1,%P0,16\"; ! 3205: ! 3206: case 1: ! 3207: return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; ! 3208: ! 3209: case 2: ! 3210: /* Normally copy registers with lowest numbered register copied first. ! 3211: But copy in the other order if the first register of the output ! 3212: is the second, third, or fourth register in the input. */ ! 3213: if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 ! 3214: && REGNO (operands[0]) <= REGNO (operands[1]) + 3) ! 3215: return \"{oril %Z0,%Z1,0|mr %Z0,%Z1}\;{oril %Y0,%Y1,0|mr %Y0,%Y1}\;{oril %L0,%L1,0|mr %L0,%L1}\;{oril %0,%1,0|mr %0,%1}\"; ! 3216: else ! 3217: return \"{oril %0,%1,0|mr %0,%1}\;{oril %L0,%L1,0|mr %L0,%L1}\;{oril %Y0,%Y1,0|mr %Y0,%Y1}\;{oril %Z0,%Z1,0|mr %Z0,%Z1}\"; ! 3218: case 3: ! 3219: /* If the address is not used in the output, we can use lsi. Otherwise, ! 3220: fall through to generating four loads. */ ! 3221: if (! reg_overlap_mentioned_p (operands[0], operands[1])) ! 3222: return \"{lsi|lswi} %0,%P1,16\"; ! 3223: /* ... fall through ... */ ! 3224: case 4: ! 3225: /* If the address register is the same as the register for the lowest- ! 3226: addressed word, load it last. Similarly for the next two words. ! 3227: Otherwise load lowest address to highest. */ ! 3228: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, ! 3229: operands[1], 0)) ! 3230: return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; ! 3231: else if (refers_to_regno_p (REGNO (operands[0]) + 1, ! 3232: REGNO (operands[0]) + 2, operands[1], 0)) ! 3233: return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; ! 3234: else if (refers_to_regno_p (REGNO (operands[0]) + 2, ! 3235: REGNO (operands[0]) + 3, operands[1], 0)) ! 3236: return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; ! 3237: else ! 3238: return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; ! 3239: } ! 3240: }" ! 3241: [(set_attr "type" "*,load,load,*,*") ! 3242: (set_attr "length" "*,16,16,*,16")]) ! 3243: ! 3244: (define_expand "load_multiple" ! 3245: [(match_par_dup 3 [(set (match_operand:SI 0 "" "") ! 3246: (match_operand:SI 1 "" "")) ! 3247: (use (match_operand:SI 2 "" ""))])] ! 3248: "TARGET_POWER" ! 3249: " ! 3250: { ! 3251: int regno; ! 3252: int count; ! 3253: rtx from; ! 3254: int i; ! 3255: ! 3256: /* Support only loading a constant number of fixed-point registers from ! 3257: memory and only bother with this if more than two; the machine ! 3258: doesn't support more than eight. */ ! 3259: if (GET_CODE (operands[2]) != CONST_INT ! 3260: || INTVAL (operands[2]) <= 2 ! 3261: || INTVAL (operands[2]) > 8 ! 3262: || GET_CODE (operands[1]) != MEM ! 3263: || GET_CODE (operands[0]) != REG ! 3264: || REGNO (operands[0]) >= 32) ! 3265: FAIL; ! 3266: ! 3267: count = INTVAL (operands[2]); ! 3268: regno = REGNO (operands[0]); ! 3269: ! 3270: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count)); ! 3271: from = force_reg (SImode, XEXP (operands[1], 0)); ! 3272: ! 3273: for (i = 0; i < count; i++) ! 3274: XVECEXP (operands[3], 0, i) ! 3275: = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i), ! 3276: gen_rtx (MEM, SImode, plus_constant (from, i * 4))); ! 3277: }") ! 3278: ! 3279: (define_insn "" ! 3280: [(match_parallel 0 "load_multiple_operation" ! 3281: [(set (match_operand:SI 1 "gpc_reg_operand" "=r") ! 3282: (match_operand:SI 2 "indirect_operand" "Q"))])] ! 3283: "TARGET_POWER" ! 3284: "* ! 3285: { ! 3286: /* We have to handle the case where the pseudo used to contain the address ! 3287: is assigned to one of the output registers. In that case, do the ! 3288: lsi, but then load the correct value. This is a bit of a mess, but is ! 3289: the best we can do. ! 3290: We set the length attribute to the maximum possible size (8 bytes). */ ! 3291: static char result[100]; ! 3292: char newload[40]; ! 3293: int i; ! 3294: ! 3295: strcpy (result, \"{lsi|lswi} %1,%P2,%N0\"); ! 3296: for (i = 0; i < XVECLEN (operands[0], 0); i++) ! 3297: if (refers_to_regno_p (REGNO (operands[1]) + i, ! 3298: REGNO (operands[1]) + i + 1, operands[2], 0)) ! 3299: { ! 3300: sprintf (newload, \"\;{l|lwz} %d,%d(%d)\", ! 3301: REGNO (operands[1]) + i, ! 3302: i * 4, REGNO (XEXP (operands[2], 0))); ! 3303: strcat (result, newload); ! 3304: } ! 3305: ! 3306: return result; ! 3307: }" ! 3308: [(set_attr "type" "load") ! 3309: (set_attr "length" "8")]) ! 3310: ! 3311: ! 3312: (define_expand "store_multiple" ! 3313: [(match_par_dup 3 [(set (match_operand:SI 0 "" "") ! 3314: (match_operand:SI 1 "" "")) ! 3315: (clobber (scratch:SI)) ! 3316: (use (match_operand:SI 2 "" ""))])] ! 3317: "TARGET_POWER" ! 3318: " ! 3319: { ! 3320: int regno; ! 3321: int count; ! 3322: rtx to; ! 3323: int i; ! 3324: ! 3325: /* Support only storing a constant number of fixed-point registers to ! 3326: memory and only bother with this if more than two; the machine ! 3327: doesn't support more than eight. */ ! 3328: if (GET_CODE (operands[2]) != CONST_INT ! 3329: || INTVAL (operands[2]) <= 2 ! 3330: || INTVAL (operands[2]) > 8 ! 3331: || GET_CODE (operands[0]) != MEM ! 3332: || GET_CODE (operands[1]) != REG ! 3333: || REGNO (operands[1]) >= 32) ! 3334: FAIL; ! 3335: ! 3336: count = INTVAL (operands[2]); ! 3337: regno = REGNO (operands[1]); ! 3338: ! 3339: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1)); ! 3340: to = force_reg (SImode, XEXP (operands[0], 0)); ! 3341: ! 3342: XVECEXP (operands[3], 0, 0) ! 3343: = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]); ! 3344: XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode, ! 3345: gen_rtx (SCRATCH, SImode)); ! 3346: ! 3347: for (i = 1; i < count; i++) ! 3348: XVECEXP (operands[3], 0, i + 1) ! 3349: = gen_rtx (SET, VOIDmode, ! 3350: gen_rtx (MEM, SImode, plus_constant (to, i * 4)), ! 3351: gen_rtx (REG, SImode, regno + i)); ! 3352: }") ! 3353: ! 3354: (define_insn "" ! 3355: [(match_parallel 0 "store_multiple_operation" ! 3356: [(set (match_operand:SI 1 "indirect_operand" "=Q") ! 3357: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 3358: (clobber (match_scratch:SI 3 "=q"))])] ! 3359: "TARGET_POWER" ! 3360: "{stsi|stswi} %2,%P1,%O0") ! 3361: ! 3362: ;; Define insns that do load or store with update. Some of these we can ! 3363: ;; get by using pre-decrement or pre-increment, but the hardware can also ! 3364: ;; do cases where the increment is not the size of the object. ! 3365: ;; ! 3366: ;; In all these cases, we use operands 0 and 1 for the register being ! 3367: ;; incremented because those are the operands that local-alloc will ! 3368: ;; tie and these are the pair most likely to be tieable (and the ones ! 3369: ;; that will benefit the most). ! 3370: ! 3371: (define_insn "" ! 3372: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") ! 3373: (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 3374: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) ! 3375: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 3376: (plus:SI (match_dup 1) (match_dup 2)))] ! 3377: "" ! 3378: "@ ! 3379: {lux|lwzux} %3,%0,%2 ! 3380: {lu|lwzu} %3,%2(%0)" ! 3381: [(set_attr "type" "load")]) ! 3382: ! 3383: (define_insn "" ! 3384: [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 3385: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) ! 3386: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 3387: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 3388: (plus:SI (match_dup 1) (match_dup 2)))] ! 3389: "" ! 3390: "@ ! 3391: {stux|stwux} %3,%0,%2 ! 3392: {stu|stwu} %3,%2(%0)") ! 3393: ! 3394: (define_insn "" ! 3395: [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") ! 3396: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 3397: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) ! 3398: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 3399: (plus:SI (match_dup 1) (match_dup 2)))] ! 3400: "" ! 3401: "@ ! 3402: lhzux %3,%0,%2 ! 3403: lhzu %3,%2(%0)" ! 3404: [(set_attr "type" "load")]) ! 3405: ! 3406: (define_insn "" ! 3407: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") ! 3408: (zero_extend:SI ! 3409: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 3410: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) ! 3411: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 3412: (plus:SI (match_dup 1) (match_dup 2)))] ! 3413: "" ! 3414: "@ ! 3415: lhzux %3,%0,%2 ! 3416: lhzu %3,%2(%0)" ! 3417: [(set_attr "type" "load")]) ! 3418: ! 3419: (define_insn "" ! 3420: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") ! 3421: (sign_extend:SI ! 3422: (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 3423: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) ! 3424: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 3425: (plus:SI (match_dup 1) (match_dup 2)))] ! 3426: "" ! 3427: "@ ! 3428: lhaux %3,%0,%2 ! 3429: lhau %3,%2(%0)" ! 3430: [(set_attr "type" "load")]) ! 3431: ! 3432: (define_insn "" ! 3433: [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 3434: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) ! 3435: (match_operand:HI 3 "gpc_reg_operand" "r,r")) ! 3436: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 3437: (plus:SI (match_dup 1) (match_dup 2)))] ! 3438: "" ! 3439: "@ ! 3440: sthux %3,%0,%2 ! 3441: sthu %3,%2(%0)") ! 3442: ! 3443: (define_insn "" ! 3444: [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") ! 3445: (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 3446: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) ! 3447: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 3448: (plus:SI (match_dup 1) (match_dup 2)))] ! 3449: "" ! 3450: "@ ! 3451: lbzux %3,%0,%2 ! 3452: lbzu %3,%2(%0)" ! 3453: [(set_attr "type" "load")]) ! 3454: ! 3455: (define_insn "" ! 3456: [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") ! 3457: (zero_extend:SI ! 3458: (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 3459: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) ! 3460: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 3461: (plus:SI (match_dup 1) (match_dup 2)))] ! 3462: "" ! 3463: "@ ! 3464: lbzux %3,%0,%2 ! 3465: lbzu %3,%2(%0)" ! 3466: [(set_attr "type" "load")]) ! 3467: ! 3468: (define_insn "" ! 3469: [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 3470: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) ! 3471: (match_operand:QI 3 "gpc_reg_operand" "r,r")) ! 3472: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 3473: (plus:SI (match_dup 1) (match_dup 2)))] ! 3474: "" ! 3475: "@ ! 3476: stbux %3,%0,%2 ! 3477: stbu %3,%2(%0)") ! 3478: ! 3479: (define_insn "" ! 3480: [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") ! 3481: (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 3482: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) ! 3483: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 3484: (plus:SI (match_dup 1) (match_dup 2)))] ! 3485: "" ! 3486: "@ ! 3487: lfsux %3,%0,%2 ! 3488: lfsu %3,%2(%0)" ! 3489: [(set_attr "type" "fpload")]) ! 3490: ! 3491: (define_insn "" ! 3492: [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 3493: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) ! 3494: (match_operand:SF 3 "gpc_reg_operand" "f,f")) ! 3495: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 3496: (plus:SI (match_dup 1) (match_dup 2)))] ! 3497: "" ! 3498: "@ ! 3499: frsp %3,%3\;stfsux %3,%0,%2 ! 3500: frsp %3,%3\;stfsu %3,%2(%0)") ! 3501: ! 3502: (define_insn "" ! 3503: [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") ! 3504: (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 3505: (match_operand:SI 2 "reg_or_short_operand" "r,I")))) ! 3506: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 3507: (plus:SI (match_dup 1) (match_dup 2)))] ! 3508: "" ! 3509: "@ ! 3510: lfdux %3,%0,%2 ! 3511: lfdu %3,%2(%0)" ! 3512: [(set_attr "type" "fpload")]) ! 3513: ! 3514: (define_insn "" ! 3515: [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") ! 3516: (match_operand:SI 2 "reg_or_short_operand" "r,I"))) ! 3517: (match_operand:DF 3 "gpc_reg_operand" "f,f")) ! 3518: (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") ! 3519: (plus:SI (match_dup 1) (match_dup 2)))] ! 3520: "" ! 3521: "@ ! 3522: stfdux %3,%0,%2 ! 3523: stfdu %3,%2(%0)") ! 3524: ! 3525: ;; Next come insns related to the calling sequence. ! 3526: ;; ! 3527: ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). ! 3528: ;; We move the back-chain and decrement the stack pointer. ! 3529: ! 3530: (define_expand "allocate_stack" ! 3531: [(set (reg:SI 1) ! 3532: (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_short_operand" "")))] ! 3533: "" ! 3534: " ! 3535: { rtx chain = gen_reg_rtx (SImode); ! 3536: rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx); ! 3537: ! 3538: emit_move_insn (chain, stack_bot); ! 3539: emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[0])); ! 3540: emit_move_insn (stack_bot, chain); ! 3541: DONE; ! 3542: }") ! 3543: ! 3544: ;; These patterns say how to save and restore the stack pointer. We need not ! 3545: ;; save the stack pointer at function level since we are careful to ! 3546: ;; preserve the backchain. At block level, we have to restore the backchain ! 3547: ;; when we restore the stack pointer. ! 3548: ;; ! 3549: ;; For nonlocal gotos, we must save both the stack pointer and its ! 3550: ;; backchain and restore both. Note that in the nonlocal case, the ! 3551: ;; save area is a memory location. ! 3552: ! 3553: (define_expand "save_stack_function" ! 3554: [(use (const_int 0))] ! 3555: "" ! 3556: "") ! 3557: ! 3558: (define_expand "restore_stack_function" ! 3559: [(use (const_int 0))] ! 3560: "" ! 3561: "") ! 3562: ! 3563: (define_expand "restore_stack_block" ! 3564: [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" ""))) ! 3565: (set (match_dup 0) (match_operand:SI 1 "register_operand" "")) ! 3566: (set (mem:SI (match_dup 0)) (match_dup 2))] ! 3567: "" ! 3568: " ! 3569: { operands[2] = gen_reg_rtx (SImode); }") ! 3570: ! 3571: (define_expand "save_stack_nonlocal" ! 3572: [(match_operand:DI 0 "memory_operand" "") ! 3573: (match_operand:SI 1 "register_operand" "")] ! 3574: "" ! 3575: " ! 3576: { ! 3577: rtx temp = gen_reg_rtx (SImode); ! 3578: ! 3579: /* Copy the backchain to the first word, sp to the second. */ ! 3580: emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1])); ! 3581: emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp); ! 3582: emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]); ! 3583: DONE; ! 3584: }") ! 3585: ! 3586: (define_expand "restore_stack_nonlocal" ! 3587: [(match_operand:SI 0 "register_operand" "") ! 3588: (match_operand:DI 1 "memory_operand" "")] ! 3589: "" ! 3590: " ! 3591: { ! 3592: rtx temp = gen_reg_rtx (SImode); ! 3593: ! 3594: /* Restore the backchain from the first word, sp from the second. */ ! 3595: emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode)); ! 3596: emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode)); ! 3597: emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp); ! 3598: DONE; ! 3599: }") ! 3600: ! 3601: ;; A function pointer is a pointer to a data area whose first word contains ! 3602: ;; the actual address of the function, whose second word contains a pointer ! 3603: ;; to its TOC, and whose third word contains a value to place in the static ! 3604: ;; chain register (r11). Note that if we load the static chain, our ! 3605: ;; "trampoline" need not have any executable code. ! 3606: ;; ! 3607: ;; operands[0] is an SImode pseudo in which we place the address of the ! 3608: ;; function. ! 3609: ;; operands[1] is the address of data area of the function to call ! 3610: ! 3611: (define_expand "call_via_ptr" ! 3612: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 3613: (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) ! 3614: (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) ! 3615: (reg:SI 2)) ! 3616: (set (reg:SI 2) ! 3617: (mem:SI (plus:SI (match_dup 1) ! 3618: (const_int 4)))) ! 3619: (set (reg:SI 11) ! 3620: (mem:SI (plus:SI (match_dup 1) ! 3621: (const_int 8)))) ! 3622: (use (reg:SI 2)) ! 3623: (use (reg:SI 11))] ! 3624: "" ! 3625: "") ! 3626: ! 3627: (define_expand "call" ! 3628: [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" "")) ! 3629: (match_operand 1 "" "")) ! 3630: (clobber (scratch:SI))])] ! 3631: "" ! 3632: " ! 3633: { ! 3634: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) ! 3635: abort (); ! 3636: ! 3637: operands[0] = XEXP (operands[0], 0); ! 3638: if (GET_CODE (operands[0]) != SYMBOL_REF) ! 3639: { ! 3640: rtx temp = gen_reg_rtx (SImode); ! 3641: ! 3642: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0]))); ! 3643: operands[0] = temp; ! 3644: } ! 3645: }") ! 3646: ! 3647: (define_expand "call_value" ! 3648: [(parallel [(set (match_operand 0 "" "") ! 3649: (call (mem:SI (match_operand:SI 1 "address_operand" "")) ! 3650: (match_operand 2 "" ""))) ! 3651: (clobber (scratch:SI))])] ! 3652: "" ! 3653: " ! 3654: { ! 3655: if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) ! 3656: abort (); ! 3657: ! 3658: operands[1] = XEXP (operands[1], 0); ! 3659: if (GET_CODE (operands[1]) != SYMBOL_REF) ! 3660: { ! 3661: rtx temp = gen_reg_rtx (SImode); ! 3662: ! 3663: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1]))); ! 3664: operands[1] = temp; ! 3665: } ! 3666: }") ! 3667: ! 3668: ;; Call to function in current module. No TOC pointer reload needed. ! 3669: ! 3670: (define_insn "" ! 3671: [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s")) ! 3672: (match_operand 1 "" "g")) ! 3673: (clobber (match_scratch:SI 2 "=l"))] ! 3674: "" ! 3675: "bl %z0") ! 3676: ! 3677: ;; Call to function which may be in another module. Restore the TOC ! 3678: ;; pointer (r2) after the call. ! 3679: ! 3680: (define_insn "" ! 3681: [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s")) ! 3682: (match_operand 1 "" "fg,fg")) ! 3683: (clobber (match_scratch:SI 2 "=l,l"))] ! 3684: "" ! 3685: "@ ! 3686: {brl|blrl}\;{l|lwz} 2,20(1) ! 3687: bl %z0\;%." ! 3688: [(set_attr "length" "8")]) ! 3689: ! 3690: (define_insn "" ! 3691: [(set (match_operand 0 "" "=fg") ! 3692: (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s")) ! 3693: (match_operand 2 "" "g"))) ! 3694: (clobber (match_scratch:SI 3 "=l"))] ! 3695: "" ! 3696: "bl %z1") ! 3697: ! 3698: (define_insn "" ! 3699: [(set (match_operand 0 "" "=fg,fg") ! 3700: (call (mem:SI (match_operand:SI 1 "call_operand" "l,s")) ! 3701: (match_operand 2 "" "fg,fg"))) ! 3702: (clobber (match_scratch:SI 3 "=l,l"))] ! 3703: "" ! 3704: "@ ! 3705: {brl|blrl}\;{l|lwz} 2,20(1) ! 3706: bl %z1\;%." ! 3707: [(set_attr "length" "8")]) ! 3708: ! 3709: ;; Call subroutine returning any type. ! 3710: ! 3711: (define_expand "untyped_call" ! 3712: [(parallel [(call (match_operand 0 "" "") ! 3713: (const_int 0)) ! 3714: (match_operand 1 "" "") ! 3715: (match_operand 2 "" "")])] ! 3716: "" ! 3717: " ! 3718: { ! 3719: int i; ! 3720: ! 3721: emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); ! 3722: ! 3723: for (i = 0; i < XVECLEN (operands[2], 0); i++) ! 3724: { ! 3725: rtx set = XVECEXP (operands[2], 0, i); ! 3726: emit_move_insn (SET_DEST (set), SET_SRC (set)); ! 3727: } ! 3728: ! 3729: /* The optimizer does not know that the call sets the function value ! 3730: registers we stored in the result block. We avoid problems by ! 3731: claiming that all hard registers are used and clobbered at this ! 3732: point. */ ! 3733: emit_insn (gen_blockage ()); ! 3734: ! 3735: DONE; ! 3736: }") ! 3737: ! 3738: ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and ! 3739: ;; all of memory. This blocks insns from being moved across this point. ! 3740: ! 3741: (define_insn "blockage" ! 3742: [(unspec_volatile [(const_int 0)] 0)] ! 3743: "" ! 3744: "") ! 3745: ! 3746: ;; Compare insns are next. Note that the RS/6000 has two types of compares, ! 3747: ;; signed & unsigned, and one type of branch. ! 3748: ;; ! 3749: ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc ! 3750: ;; insns, and branches. We store the operands of compares until we see ! 3751: ;; how it is used. ! 3752: (define_expand "cmpsi" ! 3753: [(set (cc0) ! 3754: (compare (match_operand:SI 0 "gpc_reg_operand" "") ! 3755: (match_operand:SI 1 "reg_or_short_operand" "")))] ! 3756: "" ! 3757: " ! 3758: { ! 3759: /* Take care of the possibility that operands[1] might be negative but ! 3760: this might be a logical operation. That insn doesn't exist. */ ! 3761: if (GET_CODE (operands[1]) == CONST_INT ! 3762: && INTVAL (operands[1]) < 0) ! 3763: operands[1] = force_reg (SImode, operands[1]); ! 3764: ! 3765: rs6000_compare_op0 = operands[0]; ! 3766: rs6000_compare_op1 = operands[1]; ! 3767: rs6000_compare_fp_p = 0; ! 3768: DONE; ! 3769: }") ! 3770: ! 3771: (define_expand "cmpsf" ! 3772: [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") ! 3773: (match_operand:SF 1 "gpc_reg_operand" "")))] ! 3774: "" ! 3775: " ! 3776: { ! 3777: rs6000_compare_op0 = operands[0]; ! 3778: rs6000_compare_op1 = operands[1]; ! 3779: rs6000_compare_fp_p = 1; ! 3780: DONE; ! 3781: }") ! 3782: ! 3783: (define_expand "cmpdf" ! 3784: [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") ! 3785: (match_operand:DF 1 "gpc_reg_operand" "")))] ! 3786: "" ! 3787: " ! 3788: { ! 3789: rs6000_compare_op0 = operands[0]; ! 3790: rs6000_compare_op1 = operands[1]; ! 3791: rs6000_compare_fp_p = 1; ! 3792: DONE; ! 3793: }") ! 3794: ! 3795: (define_expand "beq" ! 3796: [(set (match_dup 2) (match_dup 1)) ! 3797: (set (pc) ! 3798: (if_then_else (eq (match_dup 2) ! 3799: (const_int 0)) ! 3800: (label_ref (match_operand 0 "" "")) ! 3801: (pc)))] ! 3802: "" ! 3803: " ! 3804: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3805: operands[1] = gen_rtx (COMPARE, mode, ! 3806: rs6000_compare_op0, rs6000_compare_op1); ! 3807: operands[2] = gen_reg_rtx (mode); ! 3808: }") ! 3809: ! 3810: (define_expand "bne" ! 3811: [(set (match_dup 2) (match_dup 1)) ! 3812: (set (pc) ! 3813: (if_then_else (ne (match_dup 2) ! 3814: (const_int 0)) ! 3815: (label_ref (match_operand 0 "" "")) ! 3816: (pc)))] ! 3817: "" ! 3818: " ! 3819: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3820: operands[1] = gen_rtx (COMPARE, mode, ! 3821: rs6000_compare_op0, rs6000_compare_op1); ! 3822: operands[2] = gen_reg_rtx (mode); ! 3823: }") ! 3824: ! 3825: (define_expand "blt" ! 3826: [(set (match_dup 2) (match_dup 1)) ! 3827: (set (pc) ! 3828: (if_then_else (lt (match_dup 2) ! 3829: (const_int 0)) ! 3830: (label_ref (match_operand 0 "" "")) ! 3831: (pc)))] ! 3832: "" ! 3833: " ! 3834: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3835: operands[1] = gen_rtx (COMPARE, mode, ! 3836: rs6000_compare_op0, rs6000_compare_op1); ! 3837: operands[2] = gen_reg_rtx (mode); ! 3838: }") ! 3839: ! 3840: (define_expand "bgt" ! 3841: [(set (match_dup 2) (match_dup 1)) ! 3842: (set (pc) ! 3843: (if_then_else (gt (match_dup 2) ! 3844: (const_int 0)) ! 3845: (label_ref (match_operand 0 "" "")) ! 3846: (pc)))] ! 3847: "" ! 3848: " ! 3849: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3850: operands[1] = gen_rtx (COMPARE, mode, ! 3851: rs6000_compare_op0, rs6000_compare_op1); ! 3852: operands[2] = gen_reg_rtx (mode); ! 3853: }") ! 3854: ! 3855: (define_expand "ble" ! 3856: [(set (match_dup 2) (match_dup 1)) ! 3857: (set (pc) ! 3858: (if_then_else (le (match_dup 2) ! 3859: (const_int 0)) ! 3860: (label_ref (match_operand 0 "" "")) ! 3861: (pc)))] ! 3862: "" ! 3863: " ! 3864: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3865: operands[1] = gen_rtx (COMPARE, mode, ! 3866: rs6000_compare_op0, rs6000_compare_op1); ! 3867: operands[2] = gen_reg_rtx (mode); ! 3868: }") ! 3869: ! 3870: (define_expand "bge" ! 3871: [(set (match_dup 2) (match_dup 1)) ! 3872: (set (pc) ! 3873: (if_then_else (ge (match_dup 2) ! 3874: (const_int 0)) ! 3875: (label_ref (match_operand 0 "" "")) ! 3876: (pc)))] ! 3877: "" ! 3878: " ! 3879: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3880: operands[1] = gen_rtx (COMPARE, mode, ! 3881: rs6000_compare_op0, rs6000_compare_op1); ! 3882: operands[2] = gen_reg_rtx (mode); ! 3883: }") ! 3884: ! 3885: (define_expand "bgtu" ! 3886: [(set (match_dup 2) (match_dup 1)) ! 3887: (set (pc) ! 3888: (if_then_else (gtu (match_dup 2) ! 3889: (const_int 0)) ! 3890: (label_ref (match_operand 0 "" "")) ! 3891: (pc)))] ! 3892: "" ! 3893: " ! 3894: { operands[1] = gen_rtx (COMPARE, CCUNSmode, ! 3895: rs6000_compare_op0, rs6000_compare_op1); ! 3896: operands[2] = gen_reg_rtx (CCUNSmode); ! 3897: }") ! 3898: ! 3899: (define_expand "bltu" ! 3900: [(set (match_dup 2) (match_dup 1)) ! 3901: (set (pc) ! 3902: (if_then_else (ltu (match_dup 2) ! 3903: (const_int 0)) ! 3904: (label_ref (match_operand 0 "" "")) ! 3905: (pc)))] ! 3906: "" ! 3907: " ! 3908: { operands[1] = gen_rtx (COMPARE, CCUNSmode, ! 3909: rs6000_compare_op0, rs6000_compare_op1); ! 3910: operands[2] = gen_reg_rtx (CCUNSmode); ! 3911: }") ! 3912: ! 3913: (define_expand "bgeu" ! 3914: [(set (match_dup 2) (match_dup 1)) ! 3915: (set (pc) ! 3916: (if_then_else (geu (match_dup 2) ! 3917: (const_int 0)) ! 3918: (label_ref (match_operand 0 "" "")) ! 3919: (pc)))] ! 3920: "" ! 3921: " ! 3922: { operands[1] = gen_rtx (COMPARE, CCUNSmode, ! 3923: rs6000_compare_op0, rs6000_compare_op1); ! 3924: operands[2] = gen_reg_rtx (CCUNSmode); ! 3925: }") ! 3926: ! 3927: (define_expand "bleu" ! 3928: [(set (match_dup 2) (match_dup 1)) ! 3929: (set (pc) ! 3930: (if_then_else (leu (match_dup 2) ! 3931: (const_int 0)) ! 3932: (label_ref (match_operand 0 "" "")) ! 3933: (pc)))] ! 3934: "" ! 3935: " ! 3936: { operands[1] = gen_rtx (COMPARE, CCUNSmode, ! 3937: rs6000_compare_op0, rs6000_compare_op1); ! 3938: operands[2] = gen_reg_rtx (CCUNSmode); ! 3939: }") ! 3940: ! 3941: ;; For SNE, we would prefer that the xor/abs sequence be used for integers. ! 3942: ;; For SEQ, likewise, except that comparisons with zero should be done ! 3943: ;; with an scc insns. However, due to the order that combine see the ! 3944: ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in ! 3945: ;; the cases we don't want to handle. ! 3946: (define_expand "seq" ! 3947: [(set (match_dup 2) (match_dup 1)) ! 3948: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 3949: (eq:SI (match_dup 2) (const_int 0)))] ! 3950: "" ! 3951: " ! 3952: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3953: operands[1] = gen_rtx (COMPARE, mode, ! 3954: rs6000_compare_op0, rs6000_compare_op1); ! 3955: operands[2] = gen_reg_rtx (mode); ! 3956: }") ! 3957: ! 3958: (define_expand "sne" ! 3959: [(set (match_dup 2) (match_dup 1)) ! 3960: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 3961: (ne:SI (match_dup 2) (const_int 0)))] ! 3962: "" ! 3963: " ! 3964: { if (! rs6000_compare_fp_p) ! 3965: FAIL; ! 3966: ! 3967: operands[1] = gen_rtx (COMPARE, CCFPmode, ! 3968: rs6000_compare_op0, rs6000_compare_op1); ! 3969: operands[2] = gen_reg_rtx (CCFPmode); ! 3970: }") ! 3971: ! 3972: ;; A > 0 is best done using the portable sequence, so fail in that case. ! 3973: (define_expand "sgt" ! 3974: [(set (match_dup 2) (match_dup 1)) ! 3975: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 3976: (gt:SI (match_dup 2) (const_int 0)))] ! 3977: "" ! 3978: " ! 3979: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3980: ! 3981: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) ! 3982: FAIL; ! 3983: ! 3984: operands[1] = gen_rtx (COMPARE, mode, ! 3985: rs6000_compare_op0, rs6000_compare_op1); ! 3986: operands[2] = gen_reg_rtx (mode); ! 3987: }") ! 3988: ! 3989: ;; A < 0 is best done in the portable way for A an integer. ! 3990: (define_expand "slt" ! 3991: [(set (match_dup 2) (match_dup 1)) ! 3992: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 3993: (lt:SI (match_dup 2) (const_int 0)))] ! 3994: "" ! 3995: " ! 3996: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 3997: ! 3998: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) ! 3999: FAIL; ! 4000: ! 4001: operands[1] = gen_rtx (COMPARE, mode, ! 4002: rs6000_compare_op0, rs6000_compare_op1); ! 4003: operands[2] = gen_reg_rtx (mode); ! 4004: }") ! 4005: ! 4006: (define_expand "sge" ! 4007: [(set (match_dup 2) (match_dup 1)) ! 4008: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 4009: (ge:SI (match_dup 2) (const_int 0)))] ! 4010: "" ! 4011: " ! 4012: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 4013: operands[1] = gen_rtx (COMPARE, mode, ! 4014: rs6000_compare_op0, rs6000_compare_op1); ! 4015: operands[2] = gen_reg_rtx (mode); ! 4016: }") ! 4017: ! 4018: ;; A <= 0 is best done the portable way for A an integer. ! 4019: (define_expand "sle" ! 4020: [(set (match_dup 2) (match_dup 1)) ! 4021: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 4022: (le:SI (match_dup 2) (const_int 0)))] ! 4023: "" ! 4024: " ! 4025: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; ! 4026: ! 4027: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) ! 4028: FAIL; ! 4029: ! 4030: operands[1] = gen_rtx (COMPARE, mode, ! 4031: rs6000_compare_op0, rs6000_compare_op1); ! 4032: operands[2] = gen_reg_rtx (mode); ! 4033: }") ! 4034: ! 4035: (define_expand "sgtu" ! 4036: [(set (match_dup 2) (match_dup 1)) ! 4037: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 4038: (gtu:SI (match_dup 2) (const_int 0)))] ! 4039: "" ! 4040: " ! 4041: { operands[1] = gen_rtx (COMPARE, CCUNSmode, ! 4042: rs6000_compare_op0, rs6000_compare_op1); ! 4043: operands[2] = gen_reg_rtx (CCUNSmode); ! 4044: }") ! 4045: ! 4046: (define_expand "sltu" ! 4047: [(set (match_dup 2) (match_dup 1)) ! 4048: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 4049: (ltu:SI (match_dup 2) (const_int 0)))] ! 4050: "" ! 4051: " ! 4052: { operands[1] = gen_rtx (COMPARE, CCUNSmode, ! 4053: rs6000_compare_op0, rs6000_compare_op1); ! 4054: operands[2] = gen_reg_rtx (CCUNSmode); ! 4055: }") ! 4056: ! 4057: (define_expand "sgeu" ! 4058: [(set (match_dup 2) (match_dup 1)) ! 4059: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 4060: (geu:SI (match_dup 2) (const_int 0)))] ! 4061: "" ! 4062: " ! 4063: { operands[1] = gen_rtx (COMPARE, CCUNSmode, ! 4064: rs6000_compare_op0, rs6000_compare_op1); ! 4065: operands[2] = gen_reg_rtx (CCUNSmode); ! 4066: }") ! 4067: ! 4068: (define_expand "sleu" ! 4069: [(set (match_dup 2) (match_dup 1)) ! 4070: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 4071: (leu:SI (match_dup 2) (const_int 0)))] ! 4072: "" ! 4073: " ! 4074: { operands[1] = gen_rtx (COMPARE, CCUNSmode, ! 4075: rs6000_compare_op0, rs6000_compare_op1); ! 4076: operands[2] = gen_reg_rtx (CCUNSmode); ! 4077: }") ! 4078: ! 4079: ;; Here are the actual compare insns. ! 4080: (define_insn "" ! 4081: [(set (match_operand:CC 0 "cc_reg_operand" "=y") ! 4082: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") ! 4083: (match_operand:SI 2 "reg_or_short_operand" "rI")))] ! 4084: "" ! 4085: "{cmp%I2|cmpw%I2} %0,%1,%2" ! 4086: [(set_attr "type" "compare")]) ! 4087: ! 4088: ;; If we are comparing a register for equality with a large constant, ! 4089: ;; we can do this with an XOR followed by a compare. But we need a scratch ! 4090: ;; register for the result of the XOR. ! 4091: ! 4092: (define_split ! 4093: [(set (match_operand:CC 0 "cc_reg_operand" "") ! 4094: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") ! 4095: (match_operand:SI 2 "non_short_cint_operand" ""))) ! 4096: (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] ! 4097: "find_single_use (operands[0], insn, 0) ! 4098: && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ ! 4099: || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" ! 4100: [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) ! 4101: (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] ! 4102: " ! 4103: { ! 4104: /* Get the constant we are comparing against, C, and see what it looks like ! 4105: sign-extended to 16 bits. Then see what constant could be XOR'ed ! 4106: with C to get the sign-extended value. */ ! 4107: ! 4108: int c = INTVAL (operands[2]); ! 4109: int sextc = (c << 16) >> 16; ! 4110: int xorv = c ^ sextc; ! 4111: ! 4112: operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv); ! 4113: operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc); ! 4114: }") ! 4115: ! 4116: (define_insn "" ! 4117: [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") ! 4118: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") ! 4119: (match_operand:SI 2 "reg_or_u_short_operand" "rI")))] ! 4120: "" ! 4121: "{cmpl%I2|cmplw%I2} %0,%1,%W2" ! 4122: [(set_attr "type" "compare")]) ! 4123: ! 4124: ;; The following two insns don't exist as single insns, but if we provide ! 4125: ;; them, we can swap an add and compare, which will enable us to overlap more ! 4126: ;; of the required delay between a compare and branch. We generate code for ! 4127: ;; them by splitting. ! 4128: ! 4129: (define_insn "" ! 4130: [(set (match_operand:CC 3 "cc_reg_operand" "=y") ! 4131: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") ! 4132: (match_operand:SI 2 "short_cint_operand" "i"))) ! 4133: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4134: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] ! 4135: "" ! 4136: "#" ! 4137: [(set_attr "length" "8")]) ! 4138: ! 4139: (define_insn "" ! 4140: [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") ! 4141: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") ! 4142: (match_operand:SI 2 "u_short_cint_operand" "i"))) ! 4143: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4144: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] ! 4145: "" ! 4146: "#" ! 4147: [(set_attr "length" "8")]) ! 4148: ! 4149: (define_split ! 4150: [(set (match_operand:CC 3 "cc_reg_operand" "") ! 4151: (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") ! 4152: (match_operand:SI 2 "short_cint_operand" ""))) ! 4153: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 4154: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] ! 4155: "" ! 4156: [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) ! 4157: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) ! 4158: ! 4159: (define_split ! 4160: [(set (match_operand:CCUNS 3 "cc_reg_operand" "") ! 4161: (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") ! 4162: (match_operand:SI 2 "u_short_cint_operand" ""))) ! 4163: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 4164: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] ! 4165: "" ! 4166: [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) ! 4167: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) ! 4168: ! 4169: (define_insn "" ! 4170: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") ! 4171: (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") ! 4172: (match_operand:SF 2 "gpc_reg_operand" "f")))] ! 4173: "" ! 4174: "fcmpu %0,%1,%2" ! 4175: [(set_attr "type" "fpcompare")]) ! 4176: ! 4177: (define_insn "" ! 4178: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") ! 4179: (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") ! 4180: (match_operand:DF 2 "gpc_reg_operand" "f")))] ! 4181: "" ! 4182: "fcmpu %0,%1,%2" ! 4183: [(set_attr "type" "fpcompare")]) ! 4184: ! 4185: ;; Now we have the scc insns. We can do some combinations because of the ! 4186: ;; way the machine works. ! 4187: ;; ! 4188: ;; Note that this is probably faster if we can put an insn between the ! 4189: ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most ! 4190: ;; cases the insns below which don't use an intermediate CR field will ! 4191: ;; be used instead. ! 4192: (define_insn "" ! 4193: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4194: (match_operator:SI 1 "scc_comparison_operator" ! 4195: [(match_operand 2 "cc_reg_operand" "y") ! 4196: (const_int 0)]))] ! 4197: "" ! 4198: "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" ! 4199: [(set_attr "length" "12")]) ! 4200: ! 4201: (define_insn "" ! 4202: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 4203: (compare:CC (match_operator:SI 1 "scc_comparison_operator" ! 4204: [(match_operand 2 "cc_reg_operand" "y") ! 4205: (const_int 0)]) ! 4206: (const_int 0))) ! 4207: (set (match_operand:SI 3 "gpc_reg_operand" "=r") ! 4208: (match_op_dup 1 [(match_dup 2) (const_int 0)]))] ! 4209: "" ! 4210: "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1" ! 4211: [(set_attr "type" "delayed_compare") ! 4212: (set_attr "length" "12")]) ! 4213: ! 4214: (define_insn "" ! 4215: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4216: (ashift:SI (match_operator:SI 1 "scc_comparison_operator" ! 4217: [(match_operand 2 "cc_reg_operand" "y") ! 4218: (const_int 0)]) ! 4219: (match_operand:SI 3 "const_int_operand" "n")))] ! 4220: "" ! 4221: "* ! 4222: { ! 4223: int is_bit = ccr_bit (operands[1], 1); ! 4224: int put_bit = 31 - (INTVAL (operands[3]) & 31); ! 4225: int count; ! 4226: ! 4227: if (is_bit >= put_bit) ! 4228: count = is_bit - put_bit; ! 4229: else ! 4230: count = 32 - (put_bit - is_bit); ! 4231: ! 4232: operands[4] = gen_rtx (CONST_INT, VOIDmode, count); ! 4233: operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit); ! 4234: ! 4235: return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; ! 4236: }" ! 4237: [(set_attr "length" "12")]) ! 4238: ! 4239: (define_insn "" ! 4240: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 4241: (compare:CC ! 4242: (ashift:SI (match_operator:SI 1 "scc_comparison_operator" ! 4243: [(match_operand 2 "cc_reg_operand" "y") ! 4244: (const_int 0)]) ! 4245: (match_operand:SI 3 "const_int_operand" "n")) ! 4246: (const_int 0))) ! 4247: (set (match_operand:SI 4 "gpc_reg_operand" "=r") ! 4248: (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) ! 4249: (match_dup 3)))] ! 4250: "" ! 4251: "* ! 4252: { ! 4253: int is_bit = ccr_bit (operands[1], 1); ! 4254: int put_bit = 31 - (INTVAL (operands[3]) & 31); ! 4255: int count; ! 4256: ! 4257: if (is_bit >= put_bit) ! 4258: count = is_bit - put_bit; ! 4259: else ! 4260: count = 32 - (put_bit - is_bit); ! 4261: ! 4262: operands[5] = gen_rtx (CONST_INT, VOIDmode, count); ! 4263: operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit); ! 4264: ! 4265: return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; ! 4266: }" ! 4267: [(set_attr "type" "delayed_compare") ! 4268: (set_attr "length" "12")]) ! 4269: ! 4270: ;; If we are comparing the result of two comparisons, this can be done ! 4271: ;; using creqv or crxor. ! 4272: ! 4273: (define_insn "" ! 4274: [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") ! 4275: (compare:CCEQ (match_operator 1 "scc_comparison_operator" ! 4276: [(match_operand 2 "cc_reg_operand" "y") ! 4277: (const_int 0)]) ! 4278: (match_operator 3 "scc_comparison_operator" ! 4279: [(match_operand 4 "cc_reg_operand" "y") ! 4280: (const_int 0)])))] ! 4281: "REGNO (operands[2]) != REGNO (operands[4])" ! 4282: "* ! 4283: { ! 4284: enum rtx_code code1, code2; ! 4285: ! 4286: code1 = GET_CODE (operands[1]); ! 4287: code2 = GET_CODE (operands[3]); ! 4288: ! 4289: if ((code1 == EQ || code1 == LT || code1 == GT ! 4290: || code1 == LTU || code1 == GTU ! 4291: || (code1 != NE && GET_MODE (operands[2]) == CCFPmode)) ! 4292: != ! 4293: (code2 == EQ || code2 == LT || code2 == GT ! 4294: || code2 == LTU || code2 == GTU ! 4295: || (code2 != NE && GET_MODE (operands[4]) == CCFPmode))) ! 4296: return \"%C1%C3crxor %E0,%j1,%j3\"; ! 4297: else ! 4298: return \"%C1%C3creqv %E0,%j1,%j3\"; ! 4299: }" ! 4300: [(set_attr "length" "12")]) ! 4301: ! 4302: ;; There is a 3 cycle delay between consecutive mfcr instructions ! 4303: ;; so it is useful to combine 2 scc instructions to use only one mfcr. ! 4304: ! 4305: (define_peephole ! 4306: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4307: (match_operator:SI 1 "scc_comparison_operator" ! 4308: [(match_operand 2 "cc_reg_operand" "y") ! 4309: (const_int 0)])) ! 4310: (set (match_operand:SI 3 "gpc_reg_operand" "=r") ! 4311: (match_operator:SI 4 "scc_comparison_operator" ! 4312: [(match_operand 5 "cc_reg_operand" "y") ! 4313: (const_int 0)]))] ! 4314: "REGNO (operands[2]) != REGNO (operands[5])" ! 4315: "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" ! 4316: [(set_attr "length" "20")]) ! 4317: ! 4318: ;; There are some scc insns that can be done directly, without a compare. ! 4319: ;; These are faster because they don't involve the communications between ! 4320: ;; the FXU and branch units. In fact, we will be replacing all of the ! 4321: ;; integer scc insns here or in the portable methods in emit_store_flag. ! 4322: ;; ! 4323: ;; Also support (neg (scc ..)) since that construct is used to replace ! 4324: ;; branches, (plus (scc ..) ..) since that construct is common and ! 4325: ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the ! 4326: ;; cases where it is no more expensive than (neg (scc ..)). ! 4327: ! 4328: ;; Have reload force a constant into a register for the simple insns that ! 4329: ;; otherwise won't accept constants. We do this because it is faster than ! 4330: ;; the cmp/mfcr sequence we would otherwise generate. ! 4331: ! 4332: (define_insn "" ! 4333: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") ! 4334: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") ! 4335: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))) ! 4336: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] ! 4337: "" ! 4338: "@ ! 4339: xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 ! 4340: {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 ! 4341: {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 ! 4342: {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 ! 4343: {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" ! 4344: [(set_attr "length" "12,8,12,12,12")]) ! 4345: ! 4346: (define_insn "" ! 4347: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x") ! 4348: (compare:CC ! 4349: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") ! 4350: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) ! 4351: (const_int 0))) ! 4352: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") ! 4353: (eq:SI (match_dup 1) (match_dup 2))) ! 4354: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] ! 4355: "" ! 4356: "@ ! 4357: xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 ! 4358: {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 ! 4359: {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 ! 4360: {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 ! 4361: {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0" ! 4362: [(set_attr "type" "compare") ! 4363: (set_attr "length" "12,8,12,12,12")]) ! 4364: ! 4365: ;; We have insns of the form shown by the first define_insn below. If ! 4366: ;; there is something inside the comparison operation, we must split it. ! 4367: (define_split ! 4368: [(set (match_operand:SI 0 "gpc_reg_operand" "") ! 4369: (plus:SI (match_operator 1 "comparison_operator" ! 4370: [(match_operand:SI 2 "" "") ! 4371: (match_operand:SI 3 ! 4372: "reg_or_cint_operand" "")]) ! 4373: (match_operand:SI 4 "gpc_reg_operand" ""))) ! 4374: (clobber (match_operand:SI 5 "register_operand" ""))] ! 4375: "! gpc_reg_operand (operands[2], SImode)" ! 4376: [(set (match_dup 5) (match_dup 2)) ! 4377: (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) ! 4378: (match_dup 4)))]) ! 4379: ! 4380: (define_insn "" ! 4381: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") ! 4382: (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") ! 4383: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) ! 4384: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))) ! 4385: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] ! 4386: "" ! 4387: "@ ! 4388: xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 ! 4389: {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3 ! 4390: {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 ! 4391: {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 ! 4392: {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" ! 4393: [(set_attr "length" "12,8,12,12,12")]) ! 4394: ! 4395: (define_insn "" ! 4396: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x") ! 4397: (compare:CC ! 4398: (plus:SI ! 4399: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") ! 4400: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) ! 4401: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) ! 4402: (const_int 0))) ! 4403: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] ! 4404: "" ! 4405: "@ ! 4406: xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 ! 4407: {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3 ! 4408: {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 ! 4409: {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 ! 4410: {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" ! 4411: [(set_attr "type" "compare") ! 4412: (set_attr "length" "12,8,12,12,12")]) ! 4413: ! 4414: (define_insn "" ! 4415: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x") ! 4416: (compare:CC ! 4417: (plus:SI ! 4418: (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") ! 4419: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) ! 4420: (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) ! 4421: (const_int 0))) ! 4422: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") ! 4423: (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 4424: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] ! 4425: "" ! 4426: "@ ! 4427: xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 ! 4428: {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 ! 4429: {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 ! 4430: {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 ! 4431: {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" ! 4432: [(set_attr "type" "compare") ! 4433: (set_attr "length" "12,8,12,12,12")]) ! 4434: ! 4435: (define_insn "" ! 4436: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") ! 4437: (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r") ! 4438: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))] ! 4439: "" ! 4440: "@ ! 4441: xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 ! 4442: {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 ! 4443: {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 ! 4444: {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 ! 4445: {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" ! 4446: [(set_attr "length" "12,8,12,12,12")]) ! 4447: ! 4448: ;; This is what (plus (ne X (const_int 0)) Y) looks like. ! 4449: (define_insn "" ! 4450: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4451: (plus:SI (lshiftrt:SI ! 4452: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) ! 4453: (const_int 31)) ! 4454: (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 4455: (clobber (match_scratch:SI 3 "=&r"))] ! 4456: "" ! 4457: "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" ! 4458: [(set_attr "length" "8")]) ! 4459: ! 4460: (define_insn "" ! 4461: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 4462: (compare:CC ! 4463: (plus:SI (lshiftrt:SI ! 4464: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) ! 4465: (const_int 31)) ! 4466: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 4467: (const_int 0))) ! 4468: (clobber (match_scratch:SI 3 "=&r"))] ! 4469: "" ! 4470: "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2" ! 4471: [(set_attr "type" "compare") ! 4472: (set_attr "length" "8")]) ! 4473: ! 4474: (define_insn "" ! 4475: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 4476: (compare:CC ! 4477: (plus:SI (lshiftrt:SI ! 4478: (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) ! 4479: (const_int 31)) ! 4480: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 4481: (const_int 0))) ! 4482: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4483: (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) ! 4484: (match_dup 2))) ! 4485: (clobber (match_scratch:SI 3 "=&r"))] ! 4486: "" ! 4487: "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2" ! 4488: [(set_attr "type" "compare") ! 4489: (set_attr "length" "8")]) ! 4490: ! 4491: (define_insn "" ! 4492: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4493: (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4494: (match_operand:SI 2 "reg_or_short_operand" "r,O"))) ! 4495: (clobber (match_scratch:SI 3 "=r,X"))] ! 4496: "TARGET_POWER" ! 4497: "@ ! 4498: doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 ! 4499: {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" ! 4500: [(set_attr "length" "12")]) ! 4501: ! 4502: (define_insn "" ! 4503: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x") ! 4504: (compare:CC ! 4505: (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4506: (match_operand:SI 2 "reg_or_short_operand" "r,O")) ! 4507: (const_int 0))) ! 4508: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4509: (le:SI (match_dup 1) (match_dup 2))) ! 4510: (clobber (match_scratch:SI 3 "=r,X"))] ! 4511: "TARGET_POWER" ! 4512: "@ ! 4513: doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 ! 4514: {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31" ! 4515: [(set_attr "type" "delayed_compare,compare") ! 4516: (set_attr "length" "12")]) ! 4517: ! 4518: (define_insn "" ! 4519: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4520: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4521: (match_operand:SI 2 "reg_or_short_operand" "r,O")) ! 4522: (match_operand:SI 3 "gpc_reg_operand" "r,r"))) ! 4523: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 4524: "TARGET_POWER" ! 4525: "@ ! 4526: doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 ! 4527: {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3" ! 4528: [(set_attr "length" "12")]) ! 4529: ! 4530: (define_insn "" ! 4531: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") ! 4532: (compare:CC ! 4533: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4534: (match_operand:SI 2 "reg_or_short_operand" "r,O")) ! 4535: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 4536: (const_int 0))) ! 4537: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 4538: "TARGET_POWER" ! 4539: "@ ! 4540: doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 ! 4541: {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3" ! 4542: [(set_attr "type" "compare") ! 4543: (set_attr "length" "12")]) ! 4544: ! 4545: (define_insn "" ! 4546: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") ! 4547: (compare:CC ! 4548: (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4549: (match_operand:SI 2 "reg_or_short_operand" "r,O")) ! 4550: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 4551: (const_int 0))) ! 4552: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4553: (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 4554: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 4555: "TARGET_POWER" ! 4556: "@ ! 4557: doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 ! 4558: {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3" ! 4559: [(set_attr "type" "compare") ! 4560: (set_attr "length" "12")]) ! 4561: ! 4562: (define_insn "" ! 4563: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4564: (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4565: (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] ! 4566: "TARGET_POWER" ! 4567: "@ ! 4568: doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 ! 4569: {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" ! 4570: [(set_attr "length" "12")]) ! 4571: ! 4572: (define_insn "" ! 4573: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4574: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4575: (match_operand:SI 2 "reg_or_short_operand" "rI")))] ! 4576: "" ! 4577: "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" ! 4578: [(set_attr "length" "12")]) ! 4579: ! 4580: (define_insn "" ! 4581: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 4582: (compare:CC ! 4583: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4584: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4585: (const_int 0))) ! 4586: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4587: (leu:SI (match_dup 1) (match_dup 2)))] ! 4588: "" ! 4589: "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" ! 4590: [(set_attr "type" "compare") ! 4591: (set_attr "length" "12")]) ! 4592: ! 4593: (define_insn "" ! 4594: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4595: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4596: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4597: (match_operand:SI 3 "gpc_reg_operand" "r"))) ! 4598: (clobber (match_scratch:SI 4 "=&r"))] ! 4599: "" ! 4600: "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3" ! 4601: [(set_attr "length" "8")]) ! 4602: ! 4603: (define_insn "" ! 4604: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 4605: (compare:CC ! 4606: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4607: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4608: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 4609: (const_int 0))) ! 4610: (clobber (match_scratch:SI 4 "=&r"))] ! 4611: "" ! 4612: "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3" ! 4613: [(set_attr "type" "compare") ! 4614: (set_attr "length" "8")]) ! 4615: ! 4616: (define_insn "" ! 4617: [(set (match_operand:CC 5 "cc_reg_operand" "=x") ! 4618: (compare:CC ! 4619: (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4620: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4621: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 4622: (const_int 0))) ! 4623: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4624: (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 4625: (clobber (match_scratch:SI 4 "=&r"))] ! 4626: "" ! 4627: "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3" ! 4628: [(set_attr "type" "compare") ! 4629: (set_attr "length" "8")]) ! 4630: ! 4631: (define_insn "" ! 4632: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4633: (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4634: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] ! 4635: "" ! 4636: "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" ! 4637: [(set_attr "length" "12")]) ! 4638: ! 4639: (define_insn "" ! 4640: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4641: (and:SI (neg:SI ! 4642: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4643: (match_operand:SI 2 "reg_or_short_operand" "rI"))) ! 4644: (match_operand:SI 3 "gpc_reg_operand" "r"))) ! 4645: (clobber (match_scratch:SI 4 "=&r"))] ! 4646: "" ! 4647: "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" ! 4648: [(set_attr "length" "12")]) ! 4649: ! 4650: (define_insn "" ! 4651: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 4652: (compare:CC ! 4653: (and:SI (neg:SI ! 4654: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4655: (match_operand:SI 2 "reg_or_short_operand" "rI"))) ! 4656: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 4657: (const_int 0))) ! 4658: (clobber (match_scratch:SI 4 "=&r"))] ! 4659: "" ! 4660: "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" ! 4661: [(set_attr "type" "compare") ! 4662: (set_attr "length" "12")]) ! 4663: ! 4664: (define_insn "" ! 4665: [(set (match_operand:CC 5 "cc_reg_operand" "=x") ! 4666: (compare:CC ! 4667: (and:SI (neg:SI ! 4668: (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4669: (match_operand:SI 2 "reg_or_short_operand" "rI"))) ! 4670: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 4671: (const_int 0))) ! 4672: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4673: (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) ! 4674: (clobber (match_scratch:SI 4 "=&r"))] ! 4675: "" ! 4676: "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" ! 4677: [(set_attr "type" "compare") ! 4678: (set_attr "length" "12")]) ! 4679: ! 4680: (define_insn "" ! 4681: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4682: (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4683: (match_operand:SI 2 "reg_or_short_operand" "rI")))] ! 4684: "TARGET_POWER" ! 4685: "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" ! 4686: [(set_attr "length" "12")]) ! 4687: ! 4688: (define_insn "" ! 4689: [(set (match_operand:SI 3 "cc_reg_operand" "=x") ! 4690: (compare:CC ! 4691: (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4692: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4693: (const_int 0))) ! 4694: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4695: (lt:SI (match_dup 1) (match_dup 2)))] ! 4696: "TARGET_POWER" ! 4697: "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" ! 4698: [(set_attr "type" "delayed_compare") ! 4699: (set_attr "length" "12")]) ! 4700: ! 4701: (define_insn "" ! 4702: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4703: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4704: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4705: (match_operand:SI 3 "gpc_reg_operand" "r"))) ! 4706: (clobber (match_scratch:SI 4 "=&r"))] ! 4707: "TARGET_POWER" ! 4708: "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" ! 4709: [(set_attr "length" "12")]) ! 4710: ! 4711: (define_insn "" ! 4712: [(set (match_operand:SI 0 "cc_reg_operand" "=x") ! 4713: (compare:CC ! 4714: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4715: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4716: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 4717: (const_int 0))) ! 4718: (clobber (match_scratch:SI 4 "=&r"))] ! 4719: "TARGET_POWER" ! 4720: "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" ! 4721: [(set_attr "type" "compare") ! 4722: (set_attr "length" "12")]) ! 4723: ! 4724: (define_insn "" ! 4725: [(set (match_operand:SI 5 "cc_reg_operand" "=x") ! 4726: (compare:CC ! 4727: (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4728: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4729: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 4730: (const_int 0))) ! 4731: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4732: (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 4733: (clobber (match_scratch:SI 4 "=&r"))] ! 4734: "TARGET_POWER" ! 4735: "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" ! 4736: [(set_attr "type" "compare") ! 4737: (set_attr "length" "12")]) ! 4738: ! 4739: (define_insn "" ! 4740: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4741: (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4742: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] ! 4743: "TARGET_POWER" ! 4744: "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" ! 4745: [(set_attr "length" "12")]) ! 4746: ! 4747: (define_insn "" ! 4748: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4749: (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4750: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] ! 4751: "" ! 4752: "@ ! 4753: {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 ! 4754: {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" ! 4755: [(set_attr "length" "12")]) ! 4756: ! 4757: (define_insn "" ! 4758: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") ! 4759: (compare:CC ! 4760: (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4761: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) ! 4762: (const_int 0))) ! 4763: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4764: (ltu:SI (match_dup 1) (match_dup 2)))] ! 4765: "" ! 4766: "@ ! 4767: {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 ! 4768: {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" ! 4769: [(set_attr "type" "compare") ! 4770: (set_attr "length" "12")]) ! 4771: ! 4772: (define_insn "" ! 4773: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") ! 4774: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") ! 4775: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) ! 4776: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))) ! 4777: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))] ! 4778: "" ! 4779: "@ ! 4780: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 ! 4781: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 ! 4782: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 ! 4783: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" ! 4784: [(set_attr "length" "12")]) ! 4785: ! 4786: (define_insn "" ! 4787: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") ! 4788: (compare:CC ! 4789: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4790: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) ! 4791: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 4792: (const_int 0))) ! 4793: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 4794: "" ! 4795: "@ ! 4796: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 ! 4797: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3" ! 4798: [(set_attr "type" "compare") ! 4799: (set_attr "length" "12")]) ! 4800: ! 4801: (define_insn "" ! 4802: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") ! 4803: (compare:CC ! 4804: (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4805: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) ! 4806: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 4807: (const_int 0))) ! 4808: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4809: (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 4810: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 4811: "" ! 4812: "@ ! 4813: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 ! 4814: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" ! 4815: [(set_attr "type" "compare") ! 4816: (set_attr "length" "12")]) ! 4817: ! 4818: (define_insn "" ! 4819: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4820: (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4821: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] ! 4822: "" ! 4823: "@ ! 4824: {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 ! 4825: {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" ! 4826: [(set_attr "length" "8")]) ! 4827: ! 4828: (define_insn "" ! 4829: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4830: (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4831: (match_operand:SI 2 "reg_or_short_operand" "rI"))) ! 4832: (clobber (match_scratch:SI 3 "=r"))] ! 4833: "TARGET_POWER" ! 4834: "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" ! 4835: [(set_attr "length" "12")]) ! 4836: ! 4837: (define_insn "" ! 4838: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 4839: (compare:CC ! 4840: (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4841: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4842: (const_int 0))) ! 4843: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4844: (ge:SI (match_dup 1) (match_dup 2))) ! 4845: (clobber (match_scratch:SI 3 "=r"))] ! 4846: "TARGET_POWER" ! 4847: "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3" ! 4848: [(set_attr "type" "compare") ! 4849: (set_attr "length" "12")]) ! 4850: ! 4851: (define_insn "" ! 4852: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4853: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4854: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4855: (match_operand:SI 3 "gpc_reg_operand" "r"))) ! 4856: (clobber (match_scratch:SI 4 "=&r"))] ! 4857: "TARGET_POWER" ! 4858: "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" ! 4859: [(set_attr "length" "12")]) ! 4860: ! 4861: (define_insn "" ! 4862: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 4863: (compare:CC ! 4864: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4865: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4866: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 4867: (const_int 0))) ! 4868: (clobber (match_scratch:SI 4 "=&r"))] ! 4869: "TARGET_POWER" ! 4870: "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" ! 4871: [(set_attr "type" "compare") ! 4872: (set_attr "length" "12")]) ! 4873: ! 4874: (define_insn "" ! 4875: [(set (match_operand:CC 5 "cc_reg_operand" "=x") ! 4876: (compare:CC ! 4877: (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4878: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 4879: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 4880: (const_int 0))) ! 4881: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4882: (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 4883: (clobber (match_scratch:SI 4 "=&r"))] ! 4884: "TARGET_POWER" ! 4885: "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" ! 4886: [(set_attr "type" "compare") ! 4887: (set_attr "length" "12")]) ! 4888: ! 4889: (define_insn "" ! 4890: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4891: (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 4892: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] ! 4893: "TARGET_POWER" ! 4894: "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" ! 4895: [(set_attr "length" "12")]) ! 4896: ! 4897: ;; This is (and (neg (ge X (const_int 0))) Y). ! 4898: (define_insn "" ! 4899: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4900: (and:SI (neg:SI ! 4901: (lshiftrt:SI ! 4902: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 4903: (const_int 31))) ! 4904: (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 4905: (clobber (match_scratch:SI 3 "=&r"))] ! 4906: "" ! 4907: "{srai|srawi} %3,%1,31\;andc %0,%2,%3" ! 4908: [(set_attr "length" "8")]) ! 4909: ! 4910: (define_insn "" ! 4911: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 4912: (compare:CC ! 4913: (and:SI (neg:SI ! 4914: (lshiftrt:SI ! 4915: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 4916: (const_int 31))) ! 4917: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 4918: (const_int 0))) ! 4919: (clobber (match_scratch:SI 3 "=&r"))] ! 4920: "" ! 4921: "{srai|srawi} %3,%1,31\;andc. %3,%2,%3" ! 4922: [(set_attr "type" "compare") ! 4923: (set_attr "length" "8")]) ! 4924: ! 4925: (define_insn "" ! 4926: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 4927: (compare:CC ! 4928: (and:SI (neg:SI ! 4929: (lshiftrt:SI ! 4930: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) ! 4931: (const_int 31))) ! 4932: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 4933: (const_int 0))) ! 4934: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 4935: (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) ! 4936: (const_int 31))) ! 4937: (match_dup 2))) ! 4938: (clobber (match_scratch:SI 3 "=&r"))] ! 4939: "" ! 4940: "{srai|srawi} %3,%1,31\;andc. %0,%2,%3" ! 4941: [(set_attr "type" "compare") ! 4942: (set_attr "length" "8")]) ! 4943: ! 4944: (define_insn "" ! 4945: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4946: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4947: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] ! 4948: "" ! 4949: "@ ! 4950: {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 ! 4951: {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" ! 4952: [(set_attr "length" "12")]) ! 4953: ! 4954: (define_insn "" ! 4955: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") ! 4956: (compare:CC ! 4957: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4958: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) ! 4959: (const_int 0))) ! 4960: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4961: (geu:SI (match_dup 1) (match_dup 2)))] ! 4962: "" ! 4963: "@ ! 4964: {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 ! 4965: {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" ! 4966: [(set_attr "type" "compare") ! 4967: (set_attr "length" "12")]) ! 4968: ! 4969: (define_insn "" ! 4970: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 4971: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4972: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) ! 4973: (match_operand:SI 3 "gpc_reg_operand" "r,r"))) ! 4974: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 4975: "" ! 4976: "@ ! 4977: {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3 ! 4978: {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3" ! 4979: [(set_attr "length" "8")]) ! 4980: ! 4981: (define_insn "" ! 4982: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") ! 4983: (compare:CC ! 4984: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 4985: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) ! 4986: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 4987: (const_int 0))) ! 4988: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 4989: "" ! 4990: "@ ! 4991: {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 ! 4992: {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3" ! 4993: [(set_attr "type" "compare") ! 4994: (set_attr "length" "8")]) ! 4995: ! 4996: (define_insn "" ! 4997: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") ! 4998: (compare:CC ! 4999: (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 5000: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) ! 5001: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 5002: (const_int 0))) ! 5003: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 5004: (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 5005: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 5006: "" ! 5007: "@ ! 5008: {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 ! 5009: {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3" ! 5010: [(set_attr "type" "compare") ! 5011: (set_attr "length" "8")]) ! 5012: ! 5013: (define_insn "" ! 5014: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 5015: (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 5016: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] ! 5017: "" ! 5018: "@ ! 5019: {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 ! 5020: {sfi|subfic} %0,%1,-1\;a%I2 %0,%0,%2\;{sfe|subfe} %0,%0,%0" ! 5021: [(set_attr "length" "12")]) ! 5022: ! 5023: (define_insn "" ! 5024: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 5025: (and:SI (neg:SI ! 5026: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 5027: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) ! 5028: (match_operand:SI 3 "gpc_reg_operand" "r,r"))) ! 5029: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 5030: "" ! 5031: "@ ! 5032: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4 ! 5033: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" ! 5034: [(set_attr "length" "12")]) ! 5035: ! 5036: (define_insn "" ! 5037: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") ! 5038: (compare:CC ! 5039: (and:SI (neg:SI ! 5040: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 5041: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) ! 5042: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 5043: (const_int 0))) ! 5044: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 5045: "" ! 5046: "@ ! 5047: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 ! 5048: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" ! 5049: [(set_attr "type" "compare") ! 5050: (set_attr "length" "12")]) ! 5051: ! 5052: (define_insn "" ! 5053: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") ! 5054: (compare:CC ! 5055: (and:SI (neg:SI ! 5056: (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 5057: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) ! 5058: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 5059: (const_int 0))) ! 5060: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 5061: (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) ! 5062: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 5063: "" ! 5064: "@ ! 5065: {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 ! 5066: {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" ! 5067: [(set_attr "type" "compare") ! 5068: (set_attr "length" "12")]) ! 5069: ! 5070: (define_insn "" ! 5071: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 5072: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 5073: (const_int 0)))] ! 5074: "" ! 5075: "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" ! 5076: [(set_attr "length" "12")]) ! 5077: ! 5078: (define_insn "" ! 5079: [(set (match_operand:CC 2 "cc_reg_operand" "=x") ! 5080: (compare:CC ! 5081: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 5082: (const_int 0)) ! 5083: (const_int 0))) ! 5084: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 5085: (gt:SI (match_dup 1) (const_int 0)))] ! 5086: "" ! 5087: "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31" ! 5088: [(set_attr "type" "delayed_compare") ! 5089: (set_attr "length" "12")]) ! 5090: ! 5091: (define_insn "" ! 5092: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 5093: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 5094: (match_operand:SI 2 "reg_or_short_operand" "r")))] ! 5095: "TARGET_POWER" ! 5096: "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" ! 5097: [(set_attr "length" "12")]) ! 5098: ! 5099: (define_insn "" ! 5100: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 5101: (compare:CC ! 5102: (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 5103: (match_operand:SI 2 "reg_or_short_operand" "r")) ! 5104: (const_int 0))) ! 5105: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 5106: (gt:SI (match_dup 1) (match_dup 2)))] ! 5107: "TARGET_POWER" ! 5108: "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" ! 5109: [(set_attr "type" "delayed_compare") ! 5110: (set_attr "length" "12")]) ! 5111: ! 5112: (define_insn "" ! 5113: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 5114: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 5115: (const_int 0)) ! 5116: (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 5117: (clobber (match_scratch:SI 3 "=&r"))] ! 5118: "" ! 5119: "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2" ! 5120: [(set_attr "length" "12")]) ! 5121: ! 5122: (define_insn "" ! 5123: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 5124: (compare:CC ! 5125: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 5126: (const_int 0)) ! 5127: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 5128: (const_int 0))) ! 5129: (clobber (match_scratch:SI 3 "=&r"))] ! 5130: "" ! 5131: "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2" ! 5132: [(set_attr "type" "compare") ! 5133: (set_attr "length" "12")]) ! 5134: ! 5135: (define_insn "" ! 5136: [(set (match_operand:CC 4 "cc_reg_operand" "=x") ! 5137: (compare:CC ! 5138: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 5139: (const_int 0)) ! 5140: (match_operand:SI 2 "gpc_reg_operand" "r")) ! 5141: (const_int 0))) ! 5142: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 5143: (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) ! 5144: (clobber (match_scratch:SI 3 "=&r"))] ! 5145: "" ! 5146: "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2" ! 5147: [(set_attr "type" "compare") ! 5148: (set_attr "length" "12")]) ! 5149: ! 5150: (define_insn "" ! 5151: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 5152: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 5153: (match_operand:SI 2 "reg_or_short_operand" "r")) ! 5154: (match_operand:SI 3 "gpc_reg_operand" "r"))) ! 5155: (clobber (match_scratch:SI 4 "=&r"))] ! 5156: "TARGET_POWER" ! 5157: "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" ! 5158: [(set_attr "length" "12")]) ! 5159: ! 5160: (define_insn "" ! 5161: [(set (match_operand:CC 0 "cc_reg_operand" "=x") ! 5162: (compare:CC ! 5163: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 5164: (match_operand:SI 2 "reg_or_short_operand" "r")) ! 5165: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 5166: (const_int 0))) ! 5167: (clobber (match_scratch:SI 4 "=&r"))] ! 5168: "TARGET_POWER" ! 5169: "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" ! 5170: [(set_attr "type" "compare") ! 5171: (set_attr "length" "12")]) ! 5172: ! 5173: (define_insn "" ! 5174: [(set (match_operand:CC 5 "cc_reg_operand" "=x") ! 5175: (compare:CC ! 5176: (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 5177: (match_operand:SI 2 "reg_or_short_operand" "r")) ! 5178: (match_operand:SI 3 "gpc_reg_operand" "r")) ! 5179: (const_int 0))) ! 5180: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 5181: (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 5182: (clobber (match_scratch:SI 4 "=&r"))] ! 5183: "TARGET_POWER" ! 5184: "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" ! 5185: [(set_attr "type" "compare") ! 5186: (set_attr "length" "12")]) ! 5187: ! 5188: (define_insn "" ! 5189: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 5190: (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 5191: (const_int 0))))] ! 5192: "" ! 5193: "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" ! 5194: [(set_attr "length" "12")]) ! 5195: ! 5196: (define_insn "" ! 5197: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 5198: (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 5199: (match_operand:SI 2 "reg_or_short_operand" "r"))))] ! 5200: "TARGET_POWER" ! 5201: "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" ! 5202: [(set_attr "length" "12")]) ! 5203: ! 5204: (define_insn "" ! 5205: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 5206: (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 5207: (match_operand:SI 2 "reg_or_short_operand" "rI")))] ! 5208: "" ! 5209: "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" ! 5210: [(set_attr "length" "12")]) ! 5211: ! 5212: (define_insn "" ! 5213: [(set (match_operand:CC 3 "cc_reg_operand" "=x") ! 5214: (compare:CC ! 5215: (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 5216: (match_operand:SI 2 "reg_or_short_operand" "rI")) ! 5217: (const_int 0))) ! 5218: (set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 5219: (gtu:SI (match_dup 1) (match_dup 2)))] ! 5220: "" ! 5221: "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" ! 5222: [(set_attr "type" "compare") ! 5223: (set_attr "length" "12")]) ! 5224: ! 5225: (define_insn "" ! 5226: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") ! 5227: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") ! 5228: (match_operand:SI 2 "reg_or_short_operand" "I,r,rI")) ! 5229: (match_operand:SI 3 "reg_or_short_operand" "r,r,I"))) ! 5230: (clobber (match_scratch:SI 4 "=&r,&r,&r"))] ! 5231: "" ! 5232: "@ ! 5233: {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3 ! 5234: {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 ! 5235: {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" ! 5236: [(set_attr "length" "8,12,12")]) ! 5237: ! 5238: (define_insn "" ! 5239: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") ! 5240: (compare:CC ! 5241: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 5242: (match_operand:SI 2 "reg_or_short_operand" "I,r")) ! 5243: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 5244: (const_int 0))) ! 5245: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 5246: "" ! 5247: "@ ! 5248: {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 ! 5249: {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" ! 5250: [(set_attr "type" "compare") ! 5251: (set_attr "length" "8,12")]) ! 5252: ! 5253: (define_insn "" ! 5254: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") ! 5255: (compare:CC ! 5256: (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") ! 5257: (match_operand:SI 2 "reg_or_short_operand" "I,r")) ! 5258: (match_operand:SI 3 "gpc_reg_operand" "r,r")) ! 5259: (const_int 0))) ! 5260: (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 5261: (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) ! 5262: (clobber (match_scratch:SI 4 "=&r,&r"))] ! 5263: "" ! 5264: "@ ! 5265: {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 ! 5266: {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" ! 5267: [(set_attr "type" "compare") ! 5268: (set_attr "length" "8,12")]) ! 5269: ! 5270: (define_insn "" ! 5271: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 5272: (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") ! 5273: (match_operand:SI 2 "reg_or_short_operand" "rI"))))] ! 5274: "" ! 5275: "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" ! 5276: [(set_attr "length" "8")]) ! 5277: ! 5278: ;; Define both directions of branch and return. If we need a reload ! 5279: ;; register, we'd rather use CR0 since it is much easier to copy a ! 5280: ;; register CC value to there. ! 5281: ! 5282: (define_insn "" ! 5283: [(set (pc) ! 5284: (if_then_else (match_operator 1 "branch_comparison_operator" ! 5285: [(match_operand 2 ! 5286: "cc_reg_operand" "x,?y") ! 5287: (const_int 0)]) ! 5288: (label_ref (match_operand 0 "" "")) ! 5289: (pc)))] ! 5290: "" ! 5291: "* ! 5292: { ! 5293: if (get_attr_length (insn) == 8) ! 5294: return \"%C1bc %t1,%j1,%l0\"; ! 5295: else ! 5296: return \"%C1bc %T1,%j1,$+8\;b %l0\"; ! 5297: }" ! 5298: [(set_attr "type" "branch")]) ! 5299: ! 5300: ! 5301: (define_insn "" ! 5302: [(set (pc) ! 5303: (if_then_else (match_operator 0 "branch_comparison_operator" ! 5304: [(match_operand 1 ! 5305: "cc_reg_operand" "x,?y") ! 5306: (const_int 0)]) ! 5307: (return) ! 5308: (pc)))] ! 5309: "direct_return ()" ! 5310: "{%C0bcr|%C0bclr} %t0,%j0" ! 5311: [(set_attr "length" "8")]) ! 5312: ! 5313: (define_insn "" ! 5314: [(set (pc) ! 5315: (if_then_else (match_operator 1 "branch_comparison_operator" ! 5316: [(match_operand 2 ! 5317: "cc_reg_operand" "x,?y") ! 5318: (const_int 0)]) ! 5319: (pc) ! 5320: (label_ref (match_operand 0 "" ""))))] ! 5321: "" ! 5322: "* ! 5323: { ! 5324: if (get_attr_length (insn) == 8) ! 5325: return \"%C1bc %T1,%j1,%l0\"; ! 5326: else ! 5327: return \"%C1bc %t1,%j1,$+8\;b %l0\"; ! 5328: }" ! 5329: [(set_attr "type" "branch")]) ! 5330: ! 5331: (define_insn "" ! 5332: [(set (pc) ! 5333: (if_then_else (match_operator 0 "branch_comparison_operator" ! 5334: [(match_operand 1 ! 5335: "cc_reg_operand" "x,?y") ! 5336: (const_int 0)]) ! 5337: (pc) ! 5338: (return)))] ! 5339: "direct_return ()" ! 5340: "{%C0bcr|%C0bclr} %T0,%j0" ! 5341: [(set_attr "length" "8")]) ! 5342: ! 5343: ;; Unconditional branch and return. ! 5344: ! 5345: (define_insn "jump" ! 5346: [(set (pc) ! 5347: (label_ref (match_operand 0 "" "")))] ! 5348: "" ! 5349: "b %l0") ! 5350: ! 5351: (define_insn "return" ! 5352: [(return)] ! 5353: "direct_return ()" ! 5354: "{br|blr}") ! 5355: ! 5356: (define_insn "indirect_jump" ! 5357: [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))] ! 5358: "" ! 5359: "@ ! 5360: bctr ! 5361: {br|blr}") ! 5362: ! 5363: ;; Table jump for switch statements: ! 5364: (define_expand "tablejump" ! 5365: [(set (match_dup 3) ! 5366: (plus:SI (match_operand:SI 0 "" "") ! 5367: (match_dup 2))) ! 5368: (parallel [(set (pc) (match_dup 3)) ! 5369: (use (label_ref (match_operand 1 "" "")))])] ! 5370: "" ! 5371: " ! 5372: { operands[0] = force_reg (SImode, operands[0]); ! 5373: operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1])); ! 5374: operands[3] = gen_reg_rtx (SImode); ! 5375: }") ! 5376: ! 5377: (define_insn "" ! 5378: [(set (pc) ! 5379: (match_operand:SI 0 "register_operand" "c,l")) ! 5380: (use (label_ref (match_operand 1 "" "")))] ! 5381: "" ! 5382: "@ ! 5383: bctr ! 5384: {br|blr}") ! 5385: ! 5386: (define_insn "nop" ! 5387: [(const_int 0)] ! 5388: "" ! 5389: "{cror 0,0,0|nop}") ! 5390: ! 5391: ;; Define the subtract-one-and-jump insns, starting with the template ! 5392: ;; so loop.c knows what to generate. ! 5393: ! 5394: (define_expand "decrement_and_branchsi" ! 5395: [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "c") ! 5396: (const_int 1)) ! 5397: (label_ref (match_operand 1 "" "")) ! 5398: (pc))) ! 5399: (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))])] ! 5400: "" ! 5401: "") ! 5402: ! 5403: ;; We need to be able to do this for any operand, including MEM, or we ! 5404: ;; will cause reload to blow up since we don't allow output reloads on ! 5405: ;; JUMP_INSNs. ! 5406: (define_insn "" ! 5407: [(set (pc) ! 5408: (if_then_else (ne (match_operand:SI 1 "register_operand" "0,*r,*r") ! 5409: (const_int 1)) ! 5410: (label_ref (match_operand 2 "" "")) ! 5411: (pc))) ! 5412: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l") ! 5413: (plus:SI (match_dup 1) (const_int -1))) ! 5414: (clobber (match_scratch:CC 3 "=X,&x,&x")) ! 5415: (clobber (match_scratch:SI 4 "=X,X,r"))] ! 5416: "" ! 5417: "* ! 5418: { ! 5419: if (which_alternative != 0) ! 5420: return \"#\"; ! 5421: else if (get_attr_length (insn) == 8) ! 5422: return \"{bdn|bdnz} %l2\"; ! 5423: else ! 5424: return \"bdz $+8\;b %l2\"; ! 5425: }" ! 5426: [(set_attr "type" "branch") ! 5427: (set_attr "length" "*,12,16")]) ! 5428: ! 5429: ;; Similar, but we can use GE since we have a REG_NONNEG. ! 5430: (define_insn "" ! 5431: [(set (pc) ! 5432: (if_then_else (ge (match_operand:SI 1 "register_operand" "0,*r,*r") ! 5433: (const_int 0)) ! 5434: (label_ref (match_operand 2 "" "")) ! 5435: (pc))) ! 5436: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l") ! 5437: (plus:SI (match_dup 1) (const_int -1))) ! 5438: (clobber (match_scratch:CC 3 "=X,&x,&X")) ! 5439: (clobber (match_scratch:SI 4 "=X,X,r"))] ! 5440: "find_reg_note (insn, REG_NONNEG, 0)" ! 5441: "* ! 5442: { ! 5443: if (which_alternative != 0) ! 5444: return \"#\"; ! 5445: else if (get_attr_length (insn) == 8) ! 5446: return \"{bdn|bdnz} %l2\"; ! 5447: else ! 5448: return \"bdz $+8\;b %l2\"; ! 5449: }" ! 5450: [(set_attr "type" "branch") ! 5451: (set_attr "length" "*,12,16")]) ! 5452: ! 5453: (define_insn "" ! 5454: [(set (pc) ! 5455: (if_then_else (eq (match_operand:SI 1 "register_operand" "0,*r,*r") ! 5456: (const_int 1)) ! 5457: (label_ref (match_operand 2 "" "")) ! 5458: (pc))) ! 5459: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l") ! 5460: (plus:SI (match_dup 1) (const_int -1))) ! 5461: (clobber (match_scratch:CC 3 "=X,&x,&x")) ! 5462: (clobber (match_scratch:SI 4 "=X,X,r"))] ! 5463: "" ! 5464: "* ! 5465: { ! 5466: if (which_alternative != 0) ! 5467: return \"#\"; ! 5468: else if (get_attr_length (insn) == 8) ! 5469: return \"bdz %l2\"; ! 5470: else ! 5471: return \"{bdn|bdnz} $+8\;b %l2\"; ! 5472: }" ! 5473: [(set_attr "type" "branch") ! 5474: (set_attr "length" "*,12,16")]) ! 5475: ! 5476: (define_split ! 5477: [(set (pc) ! 5478: (if_then_else (match_operator 2 "comparison_operator" ! 5479: [(match_operand:SI 1 "gpc_reg_operand" "") ! 5480: (const_int 1)]) ! 5481: (match_operand 5 "" "") ! 5482: (match_operand 6 "" ""))) ! 5483: (set (match_operand:SI 0 "gpc_reg_operand" "") ! 5484: (plus:SI (match_dup 1) (const_int -1))) ! 5485: (clobber (match_scratch:CC 3 "")) ! 5486: (clobber (match_scratch:SI 4 ""))] ! 5487: "reload_completed" ! 5488: [(parallel [(set (match_dup 3) ! 5489: (compare:CC (plus:SI (match_dup 1) (const_int -1)) ! 5490: (const_int 0))) ! 5491: (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))]) ! 5492: (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))] ! 5493: " ! 5494: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], ! 5495: const0_rtx); }") ! 5496: ! 5497: (define_split ! 5498: [(set (pc) ! 5499: (if_then_else (match_operator 2 "comparison_operator" ! 5500: [(match_operand:SI 1 "gpc_reg_operand" "") ! 5501: (const_int 1)]) ! 5502: (match_operand 5 "" "") ! 5503: (match_operand 6 "" ""))) ! 5504: (set (match_operand:SI 0 "general_operand" "") ! 5505: (plus:SI (match_dup 1) (const_int -1))) ! 5506: (clobber (match_scratch:CC 3 "")) ! 5507: (clobber (match_scratch:SI 4 ""))] ! 5508: "reload_completed && ! gpc_reg_operand (operands[0], SImode)" ! 5509: [(parallel [(set (match_dup 3) ! 5510: (compare:CC (plus:SI (match_dup 1) (const_int -1)) ! 5511: (const_int 0))) ! 5512: (set (match_dup 4) (plus:SI (match_dup 1) (const_int -1)))]) ! 5513: (set (match_dup 0) (match_dup 4)) ! 5514: (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))] ! 5515: " ! 5516: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], ! 5517: const0_rtx); }")
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